1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * Copyright 2020, 2024 NXP 21 * 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/cleanup.h> 27 #include <linux/completion.h> 28 #include <linux/delay.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/dmaengine.h> 31 #include <linux/dmapool.h> 32 #include <linux/err.h> 33 #include <linux/errno.h> 34 #include <linux/gpio/consumer.h> 35 #include <linux/i2c.h> 36 #include <linux/init.h> 37 #include <linux/interrupt.h> 38 #include <linux/io.h> 39 #include <linux/iopoll.h> 40 #include <linux/kernel.h> 41 #include <linux/spinlock.h> 42 #include <linux/hrtimer.h> 43 #include <linux/module.h> 44 #include <linux/of.h> 45 #include <linux/of_dma.h> 46 #include <linux/pinctrl/consumer.h> 47 #include <linux/platform_data/i2c-imx.h> 48 #include <linux/platform_device.h> 49 #include <linux/pm_runtime.h> 50 #include <linux/sched.h> 51 #include <linux/slab.h> 52 53 /* This will be the driver name the kernel reports */ 54 #define DRIVER_NAME "imx-i2c" 55 56 #define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */ 57 58 /* 59 * Enable DMA if transfer byte size is bigger than this threshold. 60 * As the hardware request, it must bigger than 4 bytes.\ 61 * I have set '16' here, maybe it's not the best but I think it's 62 * the appropriate. 63 */ 64 #define DMA_THRESHOLD 16 65 #define DMA_TIMEOUT 1000 66 67 /* IMX I2C registers: 68 * the I2C register offset is different between SoCs, 69 * to provide support for all these chips, split the 70 * register offset into a fixed base address and a 71 * variable shift value, then the full register offset 72 * will be calculated by 73 * reg_off = ( reg_base_addr << reg_shift) 74 */ 75 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 76 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 77 #define IMX_I2C_I2CR 0x02 /* i2c control */ 78 #define IMX_I2C_I2SR 0x03 /* i2c status */ 79 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 80 81 /* 82 * All of the layerscape series SoCs support IBIC register. 83 */ 84 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 85 86 #define IMX_I2C_REGSHIFT 2 87 #define VF610_I2C_REGSHIFT 0 88 #define S32G_I2C_REGSHIFT 0 89 90 /* Bits of IMX I2C registers */ 91 #define I2SR_RXAK 0x01 92 #define I2SR_IIF 0x02 93 #define I2SR_SRW 0x04 94 #define I2SR_IAL 0x10 95 #define I2SR_IBB 0x20 96 #define I2SR_IAAS 0x40 97 #define I2SR_ICF 0x80 98 #define I2CR_DMAEN 0x02 99 #define I2CR_RSTA 0x04 100 #define I2CR_TXAK 0x08 101 #define I2CR_MTX 0x10 102 #define I2CR_MSTA 0x20 103 #define I2CR_IIEN 0x40 104 #define I2CR_IEN 0x80 105 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 106 107 /* register bits different operating codes definition: 108 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 109 * - write zero to clear(w0c) INT flag on i.MX, 110 * - but write one to clear(w1c) INT flag on Vybrid. 111 * 2) I2CR: I2C module enable operation also differ between SoCs: 112 * - set I2CR_IEN bit enable the module on i.MX, 113 * - but clear I2CR_IEN bit enable the module on Vybrid. 114 */ 115 #define I2SR_CLR_OPCODE_W0C 0x0 116 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 117 #define I2CR_IEN_OPCODE_0 0x0 118 #define I2CR_IEN_OPCODE_1 I2CR_IEN 119 120 #define I2C_PM_TIMEOUT 10 /* ms */ 121 122 /* 123 * sorted list of clock divider, register value pairs 124 * taken from table 26-5, p.26-9, Freescale i.MX 125 * Integrated Portable System Processor Reference Manual 126 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 127 * 128 * Duplicated divider values removed from list 129 */ 130 struct imx_i2c_clk_pair { 131 u16 div; 132 u16 val; 133 }; 134 135 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 136 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 137 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 138 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 139 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 140 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 141 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 142 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 143 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 144 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 145 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 146 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 147 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 148 { 3072, 0x1E }, { 3840, 0x1F } 149 }; 150 151 /* Vybrid VF610 clock divider, register value pairs */ 152 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 153 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 154 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 155 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 156 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 157 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 158 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 159 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 160 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 161 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 162 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 163 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 164 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 165 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 166 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 167 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 168 }; 169 170 /* S32G2/S32G3 clock divider, register value pairs */ 171 static struct imx_i2c_clk_pair s32g2_i2c_clk_div[] = { 172 { 34, 0x00 }, { 36, 0x01 }, { 38, 0x02 }, { 40, 0x03 }, 173 { 42, 0x04 }, { 44, 0x05 }, { 46, 0x06 }, { 48, 0x09 }, 174 { 52, 0x0A }, { 54, 0x07 }, { 56, 0x0B }, { 60, 0x0C }, 175 { 64, 0x0D }, { 68, 0x40 }, { 72, 0x0E }, { 76, 0x42 }, 176 { 80, 0x12 }, { 84, 0x0F }, { 88, 0x13 }, { 96, 0x14 }, 177 { 104, 0x15 }, { 108, 0x47 }, { 112, 0x19 }, { 120, 0x16 }, 178 { 128, 0x1A }, { 136, 0x80 }, { 144, 0x17 }, { 152, 0x82 }, 179 { 160, 0x1C }, { 168, 0x84 }, { 176, 0x1D }, { 192, 0x21 }, 180 { 208, 0x1E }, { 216, 0x87 }, { 224, 0x22 }, { 240, 0x56 }, 181 { 256, 0x1F }, { 288, 0x24 }, { 320, 0x25 }, { 336, 0x8F }, 182 { 352, 0x93 }, { 356, 0x5D }, { 358, 0x98 }, { 384, 0x26 }, 183 { 416, 0x56 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 184 { 576, 0x2C }, { 640, 0x2D }, { 704, 0x9D }, { 768, 0x2E }, 185 { 832, 0x9D }, { 896, 0x32 }, { 960, 0x2F }, { 1024, 0x33 }, 186 { 1152, 0x34 }, { 1280, 0x35 }, { 1536, 0x36 }, { 1792, 0x3A }, 187 { 1920, 0x37 }, { 2048, 0x3B }, { 2304, 0x74 }, { 2560, 0x3D }, 188 { 3072, 0x3E }, { 3584, 0x7A }, { 3840, 0x3F }, { 4096, 0x7B }, 189 { 4608, 0x7C }, { 5120, 0x7D }, { 6144, 0x7E }, { 7168, 0xBA }, 190 { 7680, 0x7F }, { 8192, 0xBB }, { 9216, 0xBC }, { 10240, 0xBD }, 191 { 12288, 0xBE }, { 15360, 0xBF }, 192 }; 193 194 enum imx_i2c_type { 195 IMX1_I2C, 196 IMX21_I2C, 197 S32G_I2C, 198 VF610_I2C, 199 }; 200 201 struct imx_i2c_hwdata { 202 enum imx_i2c_type devtype; 203 unsigned int regshift; 204 struct imx_i2c_clk_pair *clk_div; 205 unsigned int ndivs; 206 unsigned int i2sr_clr_opcode; 207 unsigned int i2cr_ien_opcode; 208 /* 209 * Errata ERR007805 or e7805: 210 * I2C: When the I2C clock speed is configured for 400 kHz, 211 * the SCL low period violates the I2C spec of 1.3 uS min. 212 */ 213 bool has_err007805; 214 }; 215 216 struct imx_i2c_dma { 217 struct dma_chan *chan_tx; 218 struct dma_chan *chan_rx; 219 struct dma_chan *chan_using; 220 struct completion cmd_complete; 221 dma_addr_t dma_buf; 222 unsigned int dma_len; 223 enum dma_transfer_direction dma_transfer_dir; 224 enum dma_data_direction dma_data_dir; 225 }; 226 227 enum imx_i2c_state { 228 IMX_I2C_STATE_DONE, 229 IMX_I2C_STATE_FAILED, 230 IMX_I2C_STATE_WRITE, 231 IMX_I2C_STATE_DMA, 232 IMX_I2C_STATE_READ, 233 IMX_I2C_STATE_READ_CONTINUE, 234 IMX_I2C_STATE_READ_BLOCK_DATA, 235 IMX_I2C_STATE_READ_BLOCK_DATA_LEN, 236 }; 237 238 struct imx_i2c_struct { 239 struct i2c_adapter adapter; 240 struct clk *clk; 241 struct notifier_block clk_change_nb; 242 void __iomem *base; 243 wait_queue_head_t queue; 244 unsigned long i2csr; 245 unsigned int disable_delay; 246 int stopped; 247 unsigned int ifdr; /* IMX_I2C_IFDR */ 248 unsigned int cur_clk; 249 unsigned int bitrate; 250 const struct imx_i2c_hwdata *hwdata; 251 struct i2c_bus_recovery_info rinfo; 252 253 struct imx_i2c_dma *dma; 254 struct i2c_client *slave; 255 enum i2c_slave_event last_slave_event; 256 257 struct i2c_msg *msg; 258 unsigned int msg_buf_idx; 259 int isr_result; 260 bool is_lastmsg; 261 enum imx_i2c_state state; 262 263 bool multi_master; 264 265 /* For checking slave events. */ 266 spinlock_t slave_lock; 267 struct hrtimer slave_timer; 268 }; 269 270 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 271 .devtype = IMX1_I2C, 272 .regshift = IMX_I2C_REGSHIFT, 273 .clk_div = imx_i2c_clk_div, 274 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 275 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 276 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 277 278 }; 279 280 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 281 .devtype = IMX21_I2C, 282 .regshift = IMX_I2C_REGSHIFT, 283 .clk_div = imx_i2c_clk_div, 284 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 285 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 286 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 287 288 }; 289 290 static const struct imx_i2c_hwdata imx6_i2c_hwdata = { 291 .devtype = IMX21_I2C, 292 .regshift = IMX_I2C_REGSHIFT, 293 .clk_div = imx_i2c_clk_div, 294 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 295 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 296 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 297 .has_err007805 = true, 298 }; 299 300 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 301 .devtype = VF610_I2C, 302 .regshift = VF610_I2C_REGSHIFT, 303 .clk_div = vf610_i2c_clk_div, 304 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 305 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 306 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 307 }; 308 309 static const struct imx_i2c_hwdata s32g2_i2c_hwdata = { 310 .devtype = S32G_I2C, 311 .regshift = S32G_I2C_REGSHIFT, 312 .clk_div = s32g2_i2c_clk_div, 313 .ndivs = ARRAY_SIZE(s32g2_i2c_clk_div), 314 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 315 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 316 }; 317 318 static const struct platform_device_id imx_i2c_devtype[] = { 319 { 320 .name = "imx1-i2c", 321 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 322 }, { 323 .name = "imx21-i2c", 324 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 325 }, { 326 /* sentinel */ 327 } 328 }; 329 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 330 331 static const struct of_device_id i2c_imx_dt_ids[] = { 332 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 333 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 334 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, }, 335 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, }, 336 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, }, 337 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, }, 338 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, }, 339 { .compatible = "fsl,imx7d-i2c", .data = &imx6_i2c_hwdata, }, 340 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, }, 341 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, }, 342 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, }, 343 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, }, 344 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, }, 345 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 346 { .compatible = "nxp,s32g2-i2c", .data = &s32g2_i2c_hwdata, }, 347 { /* sentinel */ } 348 }; 349 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 350 351 static const struct acpi_device_id i2c_imx_acpi_ids[] = { 352 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 353 { } 354 }; 355 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 356 357 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 358 { 359 return i2c_imx->hwdata->devtype == IMX1_I2C; 360 } 361 362 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 363 { 364 return i2c_imx->hwdata->devtype == VF610_I2C; 365 } 366 367 static inline void imx_i2c_write_reg(unsigned int val, 368 struct imx_i2c_struct *i2c_imx, unsigned int reg) 369 { 370 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 371 } 372 373 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 374 unsigned int reg) 375 { 376 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 377 } 378 379 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 380 { 381 unsigned int temp; 382 383 /* 384 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 385 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 386 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 387 */ 388 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 389 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 390 } 391 392 /* Set up i2c controller register and i2c status register to default value. */ 393 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 394 { 395 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 396 i2c_imx, IMX_I2C_I2CR); 397 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 398 } 399 400 /* Functions for DMA support */ 401 static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, dma_addr_t phy_addr) 402 { 403 struct imx_i2c_dma *dma; 404 struct dma_slave_config dma_sconfig = {}; 405 struct device *dev = i2c_imx->adapter.dev.parent; 406 int ret; 407 408 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 409 if (!dma) 410 return -ENOMEM; 411 412 dma->chan_tx = dma_request_chan(dev, "tx"); 413 if (IS_ERR(dma->chan_tx)) { 414 ret = PTR_ERR(dma->chan_tx); 415 if (ret != -ENODEV && ret != -EPROBE_DEFER) 416 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 417 goto fail_al; 418 } 419 420 dma_sconfig.dst_addr = phy_addr + 421 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 422 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 423 dma_sconfig.dst_maxburst = 1; 424 dma_sconfig.direction = DMA_MEM_TO_DEV; 425 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 426 if (ret < 0) { 427 dev_err(dev, "can't configure tx channel (%d)\n", ret); 428 goto fail_tx; 429 } 430 431 dma->chan_rx = dma_request_chan(dev, "rx"); 432 if (IS_ERR(dma->chan_rx)) { 433 ret = PTR_ERR(dma->chan_rx); 434 if (ret != -ENODEV && ret != -EPROBE_DEFER) 435 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 436 goto fail_tx; 437 } 438 439 dma_sconfig.src_addr = phy_addr + 440 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 441 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 442 dma_sconfig.src_maxburst = 1; 443 dma_sconfig.direction = DMA_DEV_TO_MEM; 444 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 445 if (ret < 0) { 446 dev_err(dev, "can't configure rx channel (%d)\n", ret); 447 goto fail_rx; 448 } 449 450 i2c_imx->dma = dma; 451 init_completion(&dma->cmd_complete); 452 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 453 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 454 455 return 0; 456 457 fail_rx: 458 dma_release_channel(dma->chan_rx); 459 fail_tx: 460 dma_release_channel(dma->chan_tx); 461 fail_al: 462 devm_kfree(dev, dma); 463 464 return ret; 465 } 466 467 static void i2c_imx_dma_callback(void *arg) 468 { 469 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 470 struct imx_i2c_dma *dma = i2c_imx->dma; 471 472 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 473 dma->dma_len, dma->dma_data_dir); 474 complete(&dma->cmd_complete); 475 } 476 477 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 478 struct i2c_msg *msgs) 479 { 480 struct imx_i2c_dma *dma = i2c_imx->dma; 481 struct dma_async_tx_descriptor *txdesc; 482 struct device *dev = &i2c_imx->adapter.dev; 483 struct device *chan_dev = dma->chan_using->device->dev; 484 485 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 486 dma->dma_len, dma->dma_data_dir); 487 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 488 dev_err(dev, "DMA mapping failed\n"); 489 goto err_map; 490 } 491 492 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 493 dma->dma_len, dma->dma_transfer_dir, 494 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 495 if (!txdesc) { 496 dev_err(dev, "Not able to get desc for DMA xfer\n"); 497 goto err_desc; 498 } 499 500 reinit_completion(&dma->cmd_complete); 501 txdesc->callback = i2c_imx_dma_callback; 502 txdesc->callback_param = i2c_imx; 503 if (dma_submit_error(dmaengine_submit(txdesc))) { 504 dev_err(dev, "DMA submit failed\n"); 505 goto err_submit; 506 } 507 508 dma_async_issue_pending(dma->chan_using); 509 return 0; 510 511 err_submit: 512 dmaengine_terminate_sync(dma->chan_using); 513 err_desc: 514 dma_unmap_single(chan_dev, dma->dma_buf, 515 dma->dma_len, dma->dma_data_dir); 516 err_map: 517 return -EINVAL; 518 } 519 520 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 521 { 522 struct imx_i2c_dma *dma = i2c_imx->dma; 523 524 dma->dma_buf = 0; 525 dma->dma_len = 0; 526 527 dma_release_channel(dma->chan_tx); 528 dma->chan_tx = NULL; 529 530 dma_release_channel(dma->chan_rx); 531 dma->chan_rx = NULL; 532 533 dma->chan_using = NULL; 534 } 535 536 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 537 { 538 bool multi_master = i2c_imx->multi_master; 539 unsigned long orig_jiffies = jiffies; 540 unsigned int temp; 541 542 while (1) { 543 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 544 545 /* check for arbitration lost */ 546 if (multi_master && (temp & I2SR_IAL)) { 547 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 548 return -EAGAIN; 549 } 550 551 if (for_busy && (!multi_master || (temp & I2SR_IBB))) { 552 i2c_imx->stopped = 0; 553 break; 554 } 555 if (!for_busy && !(temp & I2SR_IBB)) { 556 i2c_imx->stopped = 1; 557 break; 558 } 559 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 560 dev_dbg(&i2c_imx->adapter.dev, 561 "<%s> I2C bus is busy\n", __func__); 562 return -ETIMEDOUT; 563 } 564 if (atomic) 565 udelay(100); 566 else 567 schedule(); 568 } 569 570 return 0; 571 } 572 573 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 574 { 575 if (atomic) { 576 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 577 unsigned int regval; 578 579 /* 580 * The formula for the poll timeout is documented in the RM 581 * Rev.5 on page 1878: 582 * T_min = 10/F_scl 583 * Set the value hard as it is done for the non-atomic use-case. 584 * Use 10 kHz for the calculation since this is the minimum 585 * allowed SMBus frequency. Also add an offset of 100us since it 586 * turned out that the I2SR_IIF bit isn't set correctly within 587 * the minimum timeout in polling mode. 588 */ 589 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 590 i2c_imx->i2csr = regval; 591 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 592 } else { 593 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 594 } 595 596 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 597 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 598 return -ETIMEDOUT; 599 } 600 601 /* In multi-master mode check for arbitration lost */ 602 if (i2c_imx->multi_master && (i2c_imx->i2csr & I2SR_IAL)) { 603 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 604 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 605 606 i2c_imx->i2csr = 0; 607 return -EAGAIN; 608 } 609 610 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 611 i2c_imx->i2csr = 0; 612 return 0; 613 } 614 615 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 616 { 617 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 618 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 619 return -ENXIO; /* No ACK */ 620 } 621 622 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 623 return 0; 624 } 625 626 static int i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 627 unsigned int i2c_clk_rate) 628 { 629 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 630 unsigned int div; 631 int i; 632 633 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) { 634 dev_dbg(&i2c_imx->adapter.dev, 635 "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n", 636 i2c_imx->bitrate); 637 i2c_imx->bitrate = 384000; 638 } 639 640 /* Divider value calculation */ 641 if (i2c_imx->cur_clk == i2c_clk_rate) 642 return 0; 643 644 /* Keep the denominator of the following program always NOT equal to 0. */ 645 if (!(i2c_clk_rate / 2)) 646 return -EINVAL; 647 648 i2c_imx->cur_clk = i2c_clk_rate; 649 650 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate); 651 if (div < i2c_clk_div[0].div) 652 i = 0; 653 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 654 i = i2c_imx->hwdata->ndivs - 1; 655 else 656 for (i = 0; i2c_clk_div[i].div < div; i++) 657 ; 658 659 /* Store divider value */ 660 i2c_imx->ifdr = i2c_clk_div[i].val; 661 662 /* 663 * There dummy delay is calculated. 664 * It should be about one I2C clock period long. 665 * This delay is used in I2C bus disable function 666 * to fix chip hardware bug. 667 */ 668 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div, 669 i2c_clk_rate / 2); 670 671 #ifdef CONFIG_I2C_DEBUG_BUS 672 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 673 i2c_clk_rate, div); 674 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 675 i2c_clk_div[i].val, i2c_clk_div[i].div); 676 #endif 677 678 return 0; 679 } 680 681 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 682 unsigned long action, void *data) 683 { 684 struct clk_notifier_data *ndata = data; 685 struct imx_i2c_struct *i2c_imx = container_of(nb, 686 struct imx_i2c_struct, 687 clk_change_nb); 688 int ret = 0; 689 690 if (action & POST_RATE_CHANGE) 691 ret = i2c_imx_set_clk(i2c_imx, ndata->new_rate); 692 693 return notifier_from_errno(ret); 694 } 695 696 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 697 { 698 unsigned int temp = 0; 699 int result; 700 701 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 702 /* Enable I2C controller */ 703 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 704 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 705 706 /* Wait controller to be stable */ 707 if (atomic) 708 udelay(50); 709 else 710 usleep_range(50, 150); 711 712 /* Start I2C transaction */ 713 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 714 temp |= I2CR_MSTA; 715 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 716 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 717 if (result) 718 return result; 719 720 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 721 if (atomic) 722 temp &= ~I2CR_IIEN; /* Disable interrupt */ 723 724 temp &= ~I2CR_DMAEN; 725 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 726 return result; 727 } 728 729 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 730 { 731 unsigned int temp = 0; 732 733 if (!i2c_imx->stopped) { 734 /* Stop I2C transaction */ 735 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 736 if (!(temp & I2CR_MSTA)) 737 i2c_imx->stopped = 1; 738 temp &= ~(I2CR_MSTA | I2CR_MTX); 739 if (i2c_imx->dma) 740 temp &= ~I2CR_DMAEN; 741 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 742 } 743 if (is_imx1_i2c(i2c_imx)) { 744 /* 745 * This delay caused by an i.MXL hardware bug. 746 * If no (or too short) delay, no "STOP" bit will be generated. 747 */ 748 udelay(i2c_imx->disable_delay); 749 } 750 751 if (!i2c_imx->stopped) 752 i2c_imx_bus_busy(i2c_imx, 0, atomic); 753 754 /* Disable I2C controller */ 755 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN; 756 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 757 } 758 759 /* 760 * Enable bus idle interrupts 761 * Note: IBIC register will be cleared after disabled i2c module. 762 * All of layerscape series SoCs support IBIC register. 763 */ 764 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 765 { 766 if (is_vf610_i2c(i2c_imx)) { 767 unsigned int temp; 768 769 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 770 temp |= IBIC_BIIE; 771 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 772 } 773 } 774 775 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx, 776 enum i2c_slave_event event, u8 *val) 777 { 778 i2c_slave_event(i2c_imx->slave, event, val); 779 i2c_imx->last_slave_event = event; 780 } 781 782 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx) 783 { 784 u8 val = 0; 785 786 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) { 787 switch (i2c_imx->last_slave_event) { 788 case I2C_SLAVE_READ_REQUESTED: 789 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED, 790 &val); 791 break; 792 793 case I2C_SLAVE_WRITE_REQUESTED: 794 case I2C_SLAVE_READ_PROCESSED: 795 case I2C_SLAVE_WRITE_RECEIVED: 796 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val); 797 break; 798 799 case I2C_SLAVE_STOP: 800 break; 801 } 802 } 803 } 804 805 /* Returns true if the timer should be restarted, false if not. */ 806 static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx, 807 unsigned int status, unsigned int ctl) 808 { 809 u8 value = 0; 810 811 if (status & I2SR_IAL) { /* Arbitration lost */ 812 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 813 if (!(status & I2SR_IAAS)) 814 return IRQ_HANDLED; 815 } 816 817 if (!(status & I2SR_IBB)) { 818 /* No master on the bus, that could mean a stop condition. */ 819 i2c_imx_slave_finish_op(i2c_imx); 820 return IRQ_HANDLED; 821 } 822 823 if (!(status & I2SR_ICF)) 824 /* Data transfer still in progress, ignore this. */ 825 goto out; 826 827 if (status & I2SR_IAAS) { /* Addressed as a slave */ 828 i2c_imx_slave_finish_op(i2c_imx); 829 if (status & I2SR_SRW) { /* Master wants to read from us*/ 830 dev_dbg(&i2c_imx->adapter.dev, "read requested"); 831 i2c_imx_slave_event(i2c_imx, 832 I2C_SLAVE_READ_REQUESTED, &value); 833 834 /* Slave transmit */ 835 ctl |= I2CR_MTX; 836 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 837 838 /* Send data */ 839 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 840 } else { /* Master wants to write to us */ 841 dev_dbg(&i2c_imx->adapter.dev, "write requested"); 842 i2c_imx_slave_event(i2c_imx, 843 I2C_SLAVE_WRITE_REQUESTED, &value); 844 845 /* Slave receive */ 846 ctl &= ~I2CR_MTX; 847 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 848 /* Dummy read */ 849 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 850 } 851 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 852 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 853 i2c_imx_slave_event(i2c_imx, 854 I2C_SLAVE_WRITE_RECEIVED, &value); 855 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 856 ctl |= I2CR_MTX; 857 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 858 859 i2c_imx_slave_event(i2c_imx, 860 I2C_SLAVE_READ_PROCESSED, &value); 861 862 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 863 } else { /* Transmit mode received NAK, operation is done */ 864 ctl &= ~I2CR_MTX; 865 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 866 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 867 868 /* flag the last byte as processed */ 869 i2c_imx_slave_event(i2c_imx, 870 I2C_SLAVE_READ_PROCESSED, &value); 871 872 i2c_imx_slave_finish_op(i2c_imx); 873 return IRQ_HANDLED; 874 } 875 876 out: 877 /* 878 * No need to check the return value here. If it returns 0 or 879 * 1, then everything is fine. If it returns -1, then the 880 * timer is running in the handler. This will still work, 881 * though it may be redone (or already have been done) by the 882 * timer function. 883 */ 884 hrtimer_try_to_cancel(&i2c_imx->slave_timer); 885 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY); 886 hrtimer_restart(&i2c_imx->slave_timer); 887 return IRQ_HANDLED; 888 } 889 890 static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t) 891 { 892 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct, 893 slave_timer); 894 unsigned int ctl, status; 895 896 guard(spinlock_irqsave)(&i2c_imx->slave_lock); 897 898 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 899 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 900 i2c_imx_slave_handle(i2c_imx, status, ctl); 901 902 return HRTIMER_NORESTART; 903 } 904 905 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 906 { 907 int temp; 908 909 /* Set slave addr. */ 910 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 911 912 i2c_imx_reset_regs(i2c_imx); 913 914 /* Enable module */ 915 temp = i2c_imx->hwdata->i2cr_ien_opcode; 916 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 917 918 /* Enable interrupt from i2c module */ 919 temp |= I2CR_IIEN; 920 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 921 922 i2c_imx_enable_bus_idle(i2c_imx); 923 } 924 925 static int i2c_imx_reg_slave(struct i2c_client *client) 926 { 927 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 928 int ret; 929 930 if (i2c_imx->slave) 931 return -EBUSY; 932 933 /* Resume */ 934 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 935 if (ret < 0) { 936 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 937 return ret; 938 } 939 940 scoped_guard(spinlock_irqsave, &i2c_imx->slave_lock) { 941 i2c_imx->slave = client; 942 i2c_imx->last_slave_event = I2C_SLAVE_STOP; 943 } 944 945 i2c_imx_slave_init(i2c_imx); 946 947 return 0; 948 } 949 950 static int i2c_imx_unreg_slave(struct i2c_client *client) 951 { 952 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 953 int ret; 954 955 if (!i2c_imx->slave) 956 return -EINVAL; 957 958 /* Reset slave address. */ 959 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 960 961 i2c_imx_reset_regs(i2c_imx); 962 963 hrtimer_cancel(&i2c_imx->slave_timer); 964 i2c_imx->slave = NULL; 965 966 /* Suspend */ 967 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 968 if (ret < 0) 969 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 970 971 return ret; 972 } 973 974 static inline int i2c_imx_isr_acked(struct imx_i2c_struct *i2c_imx) 975 { 976 i2c_imx->isr_result = 0; 977 978 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 979 i2c_imx->state = IMX_I2C_STATE_FAILED; 980 i2c_imx->isr_result = -ENXIO; 981 wake_up(&i2c_imx->queue); 982 } 983 984 return i2c_imx->isr_result; 985 } 986 987 static inline int i2c_imx_isr_write(struct imx_i2c_struct *i2c_imx) 988 { 989 int result; 990 991 result = i2c_imx_isr_acked(i2c_imx); 992 if (result) 993 return result; 994 995 if (i2c_imx->msg->len == i2c_imx->msg_buf_idx) 996 return 0; 997 998 imx_i2c_write_reg(i2c_imx->msg->buf[i2c_imx->msg_buf_idx++], i2c_imx, IMX_I2C_I2DR); 999 1000 return 1; 1001 } 1002 1003 static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx) 1004 { 1005 int result; 1006 unsigned int temp; 1007 1008 result = i2c_imx_isr_acked(i2c_imx); 1009 if (result) 1010 return result; 1011 1012 /* setup bus to read data */ 1013 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1014 temp &= ~I2CR_MTX; 1015 if ((i2c_imx->msg->len - 1) || (i2c_imx->msg->flags & I2C_M_RECV_LEN)) 1016 temp &= ~I2CR_TXAK; 1017 1018 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1019 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1020 1021 return 0; 1022 } 1023 1024 static inline enum imx_i2c_state i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx) 1025 { 1026 enum imx_i2c_state next_state = IMX_I2C_STATE_READ_CONTINUE; 1027 unsigned int temp; 1028 1029 if ((i2c_imx->msg->len - 1) == i2c_imx->msg_buf_idx) { 1030 if (i2c_imx->is_lastmsg) { 1031 /* 1032 * It must generate STOP before read I2DR to prevent 1033 * controller from generating another clock cycle 1034 */ 1035 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1036 if (!(temp & I2CR_MSTA)) 1037 i2c_imx->stopped = 1; 1038 temp &= ~(I2CR_MSTA | I2CR_MTX); 1039 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1040 1041 return IMX_I2C_STATE_DONE; 1042 } 1043 /* 1044 * For i2c master receiver repeat restart operation like: 1045 * read -> repeat MSTA -> read/write 1046 * The controller must set MTX before read the last byte in 1047 * the first read operation, otherwise the first read cost 1048 * one extra clock cycle. 1049 */ 1050 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1051 temp |= I2CR_MTX; 1052 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1053 next_state = IMX_I2C_STATE_DONE; 1054 } else if (i2c_imx->msg_buf_idx == (i2c_imx->msg->len - 2)) { 1055 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1056 temp |= I2CR_TXAK; 1057 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1058 } 1059 1060 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1061 return next_state; 1062 } 1063 1064 static inline void i2c_imx_isr_read_block_data_len(struct imx_i2c_struct *i2c_imx) 1065 { 1066 u8 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1067 unsigned int temp; 1068 1069 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) { 1070 /* 1071 * SMBus 3.1 6.5.7: support count byte of 0. 1072 * I2C_SMBUS_BLOCK_MAX case should not hold the SDA either. 1073 * So NACK it (TXAK) to not hold the bus. 1074 */ 1075 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1076 temp |= I2CR_TXAK; 1077 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1078 1079 if (len == 0) { 1080 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = 0; 1081 i2c_imx->msg->len = 2; 1082 return; 1083 } 1084 1085 i2c_imx->isr_result = -EPROTO; 1086 i2c_imx->state = IMX_I2C_STATE_FAILED; 1087 wake_up(&i2c_imx->queue); 1088 return; 1089 } 1090 i2c_imx->msg->len += len; 1091 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = len; 1092 } 1093 1094 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 1095 { 1096 /* 1097 * This state machine handles I2C reception and transmission in non-DMA 1098 * mode. We must process all the data in the ISR to reduce the delay 1099 * between two consecutive messages. If the data is not processed in 1100 * the ISR, SMBus devices may timeout, leading to a bus error. 1101 */ 1102 switch (i2c_imx->state) { 1103 case IMX_I2C_STATE_DMA: 1104 i2c_imx->i2csr = status; 1105 wake_up(&i2c_imx->queue); 1106 break; 1107 1108 case IMX_I2C_STATE_READ: 1109 if (i2c_imx_isr_read(i2c_imx)) 1110 break; 1111 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE; 1112 break; 1113 1114 case IMX_I2C_STATE_READ_CONTINUE: 1115 i2c_imx->state = i2c_imx_isr_read_continue(i2c_imx); 1116 if (i2c_imx->state == IMX_I2C_STATE_DONE) 1117 wake_up(&i2c_imx->queue); 1118 break; 1119 1120 case IMX_I2C_STATE_READ_BLOCK_DATA: 1121 if (i2c_imx_isr_read(i2c_imx)) 1122 break; 1123 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA_LEN; 1124 break; 1125 1126 case IMX_I2C_STATE_READ_BLOCK_DATA_LEN: 1127 i2c_imx_isr_read_block_data_len(i2c_imx); 1128 if (i2c_imx->state == IMX_I2C_STATE_READ_BLOCK_DATA_LEN) 1129 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE; 1130 break; 1131 1132 case IMX_I2C_STATE_WRITE: 1133 if (i2c_imx_isr_write(i2c_imx)) 1134 break; 1135 i2c_imx->state = IMX_I2C_STATE_DONE; 1136 wake_up(&i2c_imx->queue); 1137 break; 1138 1139 default: 1140 i2c_imx->i2csr = status; 1141 i2c_imx->state = IMX_I2C_STATE_FAILED; 1142 i2c_imx->isr_result = -EINVAL; 1143 wake_up(&i2c_imx->queue); 1144 } 1145 1146 return IRQ_HANDLED; 1147 } 1148 1149 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 1150 { 1151 struct imx_i2c_struct *i2c_imx = dev_id; 1152 unsigned int ctl, status; 1153 1154 scoped_guard(spinlock_irqsave, &i2c_imx->slave_lock) { 1155 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1156 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1157 1158 if (!(status & I2SR_IIF)) 1159 return IRQ_NONE; 1160 1161 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 1162 1163 if (i2c_imx->slave) { 1164 if (!(ctl & I2CR_MSTA)) 1165 return i2c_imx_slave_handle(i2c_imx, 1166 status, ctl); 1167 1168 i2c_imx_slave_finish_op(i2c_imx); 1169 } 1170 } 1171 1172 return i2c_imx_master_isr(i2c_imx, status); 1173 } 1174 1175 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 1176 struct i2c_msg *msgs) 1177 { 1178 int result; 1179 unsigned long time_left; 1180 unsigned int temp = 0; 1181 unsigned long orig_jiffies = jiffies; 1182 struct imx_i2c_dma *dma = i2c_imx->dma; 1183 struct device *dev = &i2c_imx->adapter.dev; 1184 1185 i2c_imx->state = IMX_I2C_STATE_DMA; 1186 1187 dma->chan_using = dma->chan_tx; 1188 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 1189 dma->dma_data_dir = DMA_TO_DEVICE; 1190 dma->dma_len = msgs->len - 1; 1191 result = i2c_imx_dma_xfer(i2c_imx, msgs); 1192 if (result) 1193 return result; 1194 1195 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1196 temp |= I2CR_DMAEN; 1197 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1198 1199 /* 1200 * Write slave address. 1201 * The first byte must be transmitted by the CPU. 1202 */ 1203 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1204 time_left = wait_for_completion_timeout( 1205 &i2c_imx->dma->cmd_complete, 1206 msecs_to_jiffies(DMA_TIMEOUT)); 1207 if (time_left == 0) { 1208 dmaengine_terminate_sync(dma->chan_using); 1209 return -ETIMEDOUT; 1210 } 1211 1212 /* Waiting for transfer complete. */ 1213 while (1) { 1214 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1215 if (temp & I2SR_ICF) 1216 break; 1217 if (time_after(jiffies, orig_jiffies + 1218 msecs_to_jiffies(DMA_TIMEOUT))) { 1219 dev_dbg(dev, "<%s> Timeout\n", __func__); 1220 return -ETIMEDOUT; 1221 } 1222 schedule(); 1223 } 1224 1225 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1226 temp &= ~I2CR_DMAEN; 1227 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1228 1229 /* The last data byte must be transferred by the CPU. */ 1230 imx_i2c_write_reg(msgs->buf[msgs->len-1], 1231 i2c_imx, IMX_I2C_I2DR); 1232 result = i2c_imx_trx_complete(i2c_imx, false); 1233 if (result) 1234 return result; 1235 1236 return i2c_imx_acked(i2c_imx); 1237 } 1238 1239 static int i2c_imx_prepare_read(struct imx_i2c_struct *i2c_imx, 1240 struct i2c_msg *msgs, bool use_dma) 1241 { 1242 int result; 1243 unsigned int temp = 0; 1244 1245 /* write slave address */ 1246 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1247 result = i2c_imx_trx_complete(i2c_imx, !use_dma); 1248 if (result) 1249 return result; 1250 result = i2c_imx_acked(i2c_imx); 1251 if (result) 1252 return result; 1253 1254 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 1255 1256 /* setup bus to read data */ 1257 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1258 temp &= ~I2CR_MTX; 1259 1260 /* 1261 * Reset the I2CR_TXAK flag initially for SMBus block read since the 1262 * length is unknown 1263 */ 1264 if (msgs->len - 1) 1265 temp &= ~I2CR_TXAK; 1266 if (use_dma) 1267 temp |= I2CR_DMAEN; 1268 1269 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1270 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1271 1272 return 0; 1273 } 1274 1275 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 1276 struct i2c_msg *msgs, bool is_lastmsg) 1277 { 1278 int result; 1279 unsigned long time_left; 1280 unsigned int temp; 1281 unsigned long orig_jiffies = jiffies; 1282 struct imx_i2c_dma *dma = i2c_imx->dma; 1283 struct device *dev = &i2c_imx->adapter.dev; 1284 1285 i2c_imx->state = IMX_I2C_STATE_DMA; 1286 1287 result = i2c_imx_prepare_read(i2c_imx, msgs, true); 1288 if (result) 1289 return result; 1290 1291 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1292 1293 dma->chan_using = dma->chan_rx; 1294 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 1295 dma->dma_data_dir = DMA_FROM_DEVICE; 1296 /* The last two data bytes must be transferred by the CPU. */ 1297 dma->dma_len = msgs->len - 2; 1298 result = i2c_imx_dma_xfer(i2c_imx, msgs); 1299 if (result) 1300 return result; 1301 1302 time_left = wait_for_completion_timeout( 1303 &i2c_imx->dma->cmd_complete, 1304 msecs_to_jiffies(DMA_TIMEOUT)); 1305 if (time_left == 0) { 1306 dmaengine_terminate_sync(dma->chan_using); 1307 return -ETIMEDOUT; 1308 } 1309 1310 /* waiting for transfer complete. */ 1311 while (1) { 1312 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1313 if (temp & I2SR_ICF) 1314 break; 1315 if (time_after(jiffies, orig_jiffies + 1316 msecs_to_jiffies(DMA_TIMEOUT))) { 1317 dev_dbg(dev, "<%s> Timeout\n", __func__); 1318 return -ETIMEDOUT; 1319 } 1320 schedule(); 1321 } 1322 1323 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1324 temp &= ~I2CR_DMAEN; 1325 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1326 1327 /* read n-1 byte data */ 1328 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1329 temp |= I2CR_TXAK; 1330 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1331 1332 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1333 /* read n byte data */ 1334 result = i2c_imx_trx_complete(i2c_imx, false); 1335 if (result) 1336 return result; 1337 1338 if (is_lastmsg) { 1339 /* 1340 * It must generate STOP before read I2DR to prevent 1341 * controller from generating another clock cycle 1342 */ 1343 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 1344 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1345 if (!(temp & I2CR_MSTA)) 1346 i2c_imx->stopped = 1; 1347 temp &= ~(I2CR_MSTA | I2CR_MTX); 1348 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1349 if (!i2c_imx->stopped) 1350 i2c_imx_bus_busy(i2c_imx, 0, false); 1351 } else { 1352 /* 1353 * For i2c master receiver repeat restart operation like: 1354 * read -> repeat MSTA -> read/write 1355 * The controller must set MTX before read the last byte in 1356 * the first read operation, otherwise the first read cost 1357 * one extra clock cycle. 1358 */ 1359 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1360 temp |= I2CR_MTX; 1361 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1362 } 1363 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1364 1365 return 0; 1366 } 1367 1368 static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx, 1369 struct i2c_msg *msgs) 1370 { 1371 int i, result; 1372 1373 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1374 __func__, i2c_8bit_addr_from_msg(msgs)); 1375 1376 /* write slave address */ 1377 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1378 result = i2c_imx_trx_complete(i2c_imx, true); 1379 if (result) 1380 return result; 1381 result = i2c_imx_acked(i2c_imx); 1382 if (result) 1383 return result; 1384 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 1385 1386 /* write data */ 1387 for (i = 0; i < msgs->len; i++) { 1388 dev_dbg(&i2c_imx->adapter.dev, 1389 "<%s> write byte: B%d=0x%X\n", 1390 __func__, i, msgs->buf[i]); 1391 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 1392 result = i2c_imx_trx_complete(i2c_imx, true); 1393 if (result) 1394 return result; 1395 result = i2c_imx_acked(i2c_imx); 1396 if (result) 1397 return result; 1398 } 1399 return 0; 1400 } 1401 1402 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 1403 { 1404 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1405 __func__, i2c_8bit_addr_from_msg(msgs)); 1406 1407 i2c_imx->state = IMX_I2C_STATE_WRITE; 1408 i2c_imx->msg = msgs; 1409 i2c_imx->msg_buf_idx = 0; 1410 1411 /* 1412 * By writing the device address we start the state machine in the ISR. 1413 * The ISR will report when it is done or when it fails. 1414 */ 1415 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1416 wait_event_timeout(i2c_imx->queue, 1417 i2c_imx->state == IMX_I2C_STATE_DONE || 1418 i2c_imx->state == IMX_I2C_STATE_FAILED, 1419 (msgs->len + 1) * HZ / 10); 1420 if (i2c_imx->state == IMX_I2C_STATE_FAILED) { 1421 dev_dbg(&i2c_imx->adapter.dev, "<%s> write failed with %d\n", 1422 __func__, i2c_imx->isr_result); 1423 return i2c_imx->isr_result; 1424 } 1425 if (i2c_imx->state != IMX_I2C_STATE_DONE) { 1426 dev_err(&i2c_imx->adapter.dev, "<%s> write timedout\n", __func__); 1427 return -ETIMEDOUT; 1428 } 1429 return 0; 1430 } 1431 1432 static int i2c_imx_atomic_read(struct imx_i2c_struct *i2c_imx, 1433 struct i2c_msg *msgs, bool is_lastmsg) 1434 { 1435 int i, result; 1436 unsigned int temp; 1437 int block_data = msgs->flags & I2C_M_RECV_LEN; 1438 int block_err = 0; 1439 1440 result = i2c_imx_prepare_read(i2c_imx, msgs, false); 1441 if (result) 1442 return result; 1443 1444 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1445 1446 /* read data */ 1447 for (i = 0; i < msgs->len; i++) { 1448 u8 len = 0; 1449 1450 result = i2c_imx_trx_complete(i2c_imx, true); 1451 if (result) 1452 return result; 1453 /* 1454 * First byte is the length of remaining packet 1455 * in the SMBus block data read. Add it to 1456 * msgs->len. 1457 */ 1458 if ((!i) && block_data) { 1459 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1460 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) { 1461 /* 1462 * SMBus 3.1 6.5.7: support count byte of 0. 1463 * I2C_SMBUS_BLOCK_MAX case should not hold the SDA either. 1464 */ 1465 if (len > I2C_SMBUS_BLOCK_MAX) 1466 block_err = -EPROTO; 1467 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1468 temp |= I2CR_TXAK; 1469 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1470 msgs->buf[0] = 0; 1471 msgs->len = 2; 1472 continue; 1473 } 1474 dev_dbg(&i2c_imx->adapter.dev, 1475 "<%s> read length: 0x%X\n", 1476 __func__, len); 1477 msgs->len += len; 1478 } 1479 if (i == (msgs->len - 1)) { 1480 if (is_lastmsg) { 1481 /* 1482 * It must generate STOP before read I2DR to prevent 1483 * controller from generating another clock cycle 1484 */ 1485 dev_dbg(&i2c_imx->adapter.dev, 1486 "<%s> clear MSTA\n", __func__); 1487 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1488 if (!(temp & I2CR_MSTA)) 1489 i2c_imx->stopped = 1; 1490 temp &= ~(I2CR_MSTA | I2CR_MTX); 1491 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1492 if (!i2c_imx->stopped) 1493 i2c_imx_bus_busy(i2c_imx, 0, true); 1494 } else { 1495 /* 1496 * For i2c master receiver repeat restart operation like: 1497 * read -> repeat MSTA -> read/write 1498 * The controller must set MTX before read the last byte in 1499 * the first read operation, otherwise the first read cost 1500 * one extra clock cycle. 1501 */ 1502 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1503 temp |= I2CR_MTX; 1504 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1505 } 1506 } else if (i == (msgs->len - 2)) { 1507 dev_dbg(&i2c_imx->adapter.dev, 1508 "<%s> set TXAK\n", __func__); 1509 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1510 temp |= I2CR_TXAK; 1511 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1512 } 1513 if ((!i) && block_data) 1514 msgs->buf[0] = len; 1515 else 1516 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1517 dev_dbg(&i2c_imx->adapter.dev, 1518 "<%s> read byte: B%d=0x%X\n", 1519 __func__, i, msgs->buf[i]); 1520 } 1521 return block_err; 1522 } 1523 1524 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1525 bool is_lastmsg) 1526 { 1527 int block_data = msgs->flags & I2C_M_RECV_LEN; 1528 int ret = 0; 1529 1530 dev_dbg(&i2c_imx->adapter.dev, 1531 "<%s> write slave address: addr=0x%x\n", 1532 __func__, i2c_8bit_addr_from_msg(msgs)); 1533 1534 i2c_imx->is_lastmsg = is_lastmsg; 1535 1536 if (block_data) 1537 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA; 1538 else 1539 i2c_imx->state = IMX_I2C_STATE_READ; 1540 i2c_imx->msg = msgs; 1541 i2c_imx->msg_buf_idx = 0; 1542 1543 /* 1544 * By writing the device address we start the state machine in the ISR. 1545 * The ISR will report when it is done or when it fails. 1546 */ 1547 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1548 wait_event_timeout(i2c_imx->queue, 1549 i2c_imx->state == IMX_I2C_STATE_DONE || 1550 i2c_imx->state == IMX_I2C_STATE_FAILED, 1551 (msgs->len + 1) * HZ / 10); 1552 if (i2c_imx->state == IMX_I2C_STATE_FAILED) { 1553 dev_dbg(&i2c_imx->adapter.dev, "<%s> read failed with %d\n", 1554 __func__, i2c_imx->isr_result); 1555 return i2c_imx->isr_result; 1556 } 1557 if (i2c_imx->state != IMX_I2C_STATE_DONE) { 1558 dev_err(&i2c_imx->adapter.dev, "<%s> read timedout\n", __func__); 1559 return -ETIMEDOUT; 1560 } 1561 if (i2c_imx->is_lastmsg) { 1562 if (!i2c_imx->stopped) 1563 ret = i2c_imx_bus_busy(i2c_imx, 0, false); 1564 /* 1565 * Only read the last byte of the last message after the bus is 1566 * not busy. Else the controller generates another clock which 1567 * might confuse devices. 1568 */ 1569 if (!ret) 1570 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, 1571 IMX_I2C_I2DR); 1572 } 1573 1574 return ret; 1575 } 1576 1577 static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 1578 struct i2c_msg *msgs, int num, bool atomic) 1579 { 1580 unsigned int i, temp; 1581 int result; 1582 bool is_lastmsg = false; 1583 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1584 int use_dma = 0; 1585 1586 /* Start I2C transfer */ 1587 result = i2c_imx_start(i2c_imx, atomic); 1588 if (result) { 1589 /* 1590 * Bus recovery uses gpiod_get_value_cansleep() which is not 1591 * allowed within atomic context. 1592 */ 1593 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 1594 i2c_recover_bus(&i2c_imx->adapter); 1595 result = i2c_imx_start(i2c_imx, atomic); 1596 } 1597 } 1598 1599 if (result) 1600 goto fail0; 1601 1602 /* read/write data */ 1603 for (i = 0; i < num; i++) { 1604 if (i == num - 1) 1605 is_lastmsg = true; 1606 1607 if (i) { 1608 dev_dbg(&i2c_imx->adapter.dev, 1609 "<%s> repeated start\n", __func__); 1610 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1611 temp |= I2CR_RSTA; 1612 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1613 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 1614 if (result) 1615 goto fail0; 1616 } 1617 dev_dbg(&i2c_imx->adapter.dev, 1618 "<%s> transfer message: %d\n", __func__, i); 1619 /* write/read data */ 1620 #ifdef CONFIG_I2C_DEBUG_BUS 1621 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1622 dev_dbg(&i2c_imx->adapter.dev, 1623 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 1624 __func__, 1625 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1626 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1627 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1628 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1629 dev_dbg(&i2c_imx->adapter.dev, 1630 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1631 __func__, 1632 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1633 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1634 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1635 (temp & I2SR_RXAK ? 1 : 0)); 1636 #endif 1637 1638 use_dma = i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD && 1639 msgs[i].flags & I2C_M_DMA_SAFE; 1640 if (msgs[i].flags & I2C_M_RD) { 1641 int block_data = msgs->flags & I2C_M_RECV_LEN; 1642 1643 if (atomic) 1644 result = i2c_imx_atomic_read(i2c_imx, &msgs[i], is_lastmsg); 1645 else if (use_dma && !block_data) 1646 result = i2c_imx_dma_read(i2c_imx, &msgs[i], is_lastmsg); 1647 else 1648 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 1649 } else { 1650 if (atomic) 1651 result = i2c_imx_atomic_write(i2c_imx, &msgs[i]); 1652 else if (use_dma) 1653 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1654 else 1655 result = i2c_imx_write(i2c_imx, &msgs[i]); 1656 } 1657 if (result) 1658 goto fail0; 1659 } 1660 1661 fail0: 1662 /* Stop I2C transfer */ 1663 i2c_imx_stop(i2c_imx, atomic); 1664 1665 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1666 (result < 0) ? "error" : "success msg", 1667 (result < 0) ? result : num); 1668 /* After data is transferred, switch to slave mode(as a receiver) */ 1669 if (i2c_imx->slave) 1670 i2c_imx_slave_init(i2c_imx); 1671 1672 return (result < 0) ? result : num; 1673 } 1674 1675 static int i2c_imx_xfer(struct i2c_adapter *adapter, 1676 struct i2c_msg *msgs, int num) 1677 { 1678 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1679 int result; 1680 1681 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 1682 if (result < 0) 1683 return result; 1684 1685 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1686 1687 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1688 1689 return result; 1690 } 1691 1692 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1693 struct i2c_msg *msgs, int num) 1694 { 1695 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1696 int result; 1697 1698 result = clk_enable(i2c_imx->clk); 1699 if (result) 1700 return result; 1701 1702 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1703 1704 clk_disable(i2c_imx->clk); 1705 1706 return result; 1707 } 1708 1709 /* 1710 * We switch SCL and SDA to their GPIO function and do some bitbanging 1711 * for bus recovery. These alternative pinmux settings can be 1712 * described in the device tree by a separate pinctrl state "gpio". If 1713 * this is missing this is not a big problem, the only implication is 1714 * that we can't do bus recovery. 1715 */ 1716 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1717 struct platform_device *pdev) 1718 { 1719 struct i2c_bus_recovery_info *bri = &i2c_imx->rinfo; 1720 1721 bri->pinctrl = devm_pinctrl_get(&pdev->dev); 1722 if (IS_ERR(bri->pinctrl)) 1723 return PTR_ERR(bri->pinctrl); 1724 1725 i2c_imx->adapter.bus_recovery_info = bri; 1726 1727 return 0; 1728 } 1729 1730 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1731 { 1732 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1733 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1734 } 1735 1736 static const struct i2c_algorithm i2c_imx_algo = { 1737 .xfer = i2c_imx_xfer, 1738 .xfer_atomic = i2c_imx_xfer_atomic, 1739 .functionality = i2c_imx_func, 1740 .reg_slave = i2c_imx_reg_slave, 1741 .unreg_slave = i2c_imx_unreg_slave, 1742 }; 1743 1744 static int i2c_imx_probe(struct platform_device *pdev) 1745 { 1746 struct imx_i2c_struct *i2c_imx; 1747 struct resource *res; 1748 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1749 void __iomem *base; 1750 int irq, ret; 1751 dma_addr_t phy_addr; 1752 const struct imx_i2c_hwdata *match; 1753 1754 irq = platform_get_irq(pdev, 0); 1755 if (irq < 0) 1756 return irq; 1757 1758 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1759 if (IS_ERR(base)) 1760 return dev_err_probe(&pdev->dev, PTR_ERR(base), "can't get IO memory\n"); 1761 1762 phy_addr = (dma_addr_t)res->start; 1763 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1764 if (!i2c_imx) 1765 return -ENOMEM; 1766 1767 spin_lock_init(&i2c_imx->slave_lock); 1768 hrtimer_setup(&i2c_imx->slave_timer, i2c_imx_slave_timeout, CLOCK_MONOTONIC, 1769 HRTIMER_MODE_ABS); 1770 1771 match = device_get_match_data(&pdev->dev); 1772 if (match) 1773 i2c_imx->hwdata = match; 1774 else 1775 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1776 platform_get_device_id(pdev)->driver_data; 1777 1778 /* Setup i2c_imx driver structure */ 1779 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1780 i2c_imx->adapter.owner = THIS_MODULE; 1781 i2c_imx->adapter.algo = &i2c_imx_algo; 1782 i2c_imx->adapter.dev.parent = &pdev->dev; 1783 i2c_imx->adapter.nr = pdev->id; 1784 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1785 i2c_imx->base = base; 1786 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1787 1788 /* Get I2C clock */ 1789 i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1790 if (IS_ERR(i2c_imx->clk)) 1791 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1792 "can't get I2C clock\n"); 1793 1794 /* Init queue */ 1795 init_waitqueue_head(&i2c_imx->queue); 1796 1797 /* Set up adapter data */ 1798 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1799 1800 /* Set up platform driver data */ 1801 platform_set_drvdata(pdev, i2c_imx); 1802 1803 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1804 pm_runtime_use_autosuspend(&pdev->dev); 1805 pm_runtime_set_active(&pdev->dev); 1806 pm_runtime_enable(&pdev->dev); 1807 1808 ret = pm_runtime_get_sync(&pdev->dev); 1809 if (ret < 0) 1810 goto rpm_disable; 1811 1812 /* Request IRQ */ 1813 ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED | IRQF_NO_SUSPEND, 1814 pdev->name, i2c_imx); 1815 if (ret) { 1816 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1817 goto rpm_disable; 1818 } 1819 1820 /* 1821 * We use the single-master property for backward compatibility. 1822 * By default multi master mode is enabled. 1823 */ 1824 i2c_imx->multi_master = !of_property_read_bool(pdev->dev.of_node, "single-master"); 1825 1826 /* Set up clock divider */ 1827 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1828 ret = of_property_read_u32(pdev->dev.of_node, 1829 "clock-frequency", &i2c_imx->bitrate); 1830 if (ret < 0 && pdata && pdata->bitrate) 1831 i2c_imx->bitrate = pdata->bitrate; 1832 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1833 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1834 ret = i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1835 if (ret < 0) { 1836 dev_err(&pdev->dev, "can't get I2C clock\n"); 1837 goto clk_notifier_unregister; 1838 } 1839 1840 i2c_imx_reset_regs(i2c_imx); 1841 1842 /* Init optional bus recovery function */ 1843 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1844 /* Give it another chance if pinctrl used is not ready yet */ 1845 if (ret == -EPROBE_DEFER) 1846 goto clk_notifier_unregister; 1847 1848 /* 1849 * DMA mode should be optional for I2C, when encountering DMA errors, 1850 * no need to exit I2C probe. Only print warning to show DMA error and 1851 * use PIO mode directly to ensure I2C bus available as much as possible. 1852 */ 1853 ret = i2c_imx_dma_request(i2c_imx, phy_addr); 1854 if (ret) { 1855 if (ret == -EPROBE_DEFER) { 1856 dev_err_probe(&pdev->dev, ret, "can't get DMA channels\n"); 1857 goto clk_notifier_unregister; 1858 } else if (ret == -ENODEV) { 1859 dev_dbg(&pdev->dev, "Only use PIO mode\n"); 1860 } else { 1861 dev_warn(&pdev->dev, "Failed to setup DMA (%pe), only use PIO mode\n", 1862 ERR_PTR(ret)); 1863 } 1864 } 1865 1866 /* Add I2C adapter */ 1867 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1868 if (ret < 0) 1869 goto clk_notifier_unregister; 1870 1871 pm_runtime_put_autosuspend(&pdev->dev); 1872 1873 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1874 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1875 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1876 i2c_imx->adapter.name); 1877 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1878 1879 return 0; /* Return OK */ 1880 1881 clk_notifier_unregister: 1882 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1883 free_irq(irq, i2c_imx); 1884 rpm_disable: 1885 pm_runtime_put_noidle(&pdev->dev); 1886 pm_runtime_disable(&pdev->dev); 1887 pm_runtime_set_suspended(&pdev->dev); 1888 pm_runtime_dont_use_autosuspend(&pdev->dev); 1889 return ret; 1890 } 1891 1892 static void i2c_imx_remove(struct platform_device *pdev) 1893 { 1894 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1895 int irq, ret; 1896 1897 ret = pm_runtime_get_sync(&pdev->dev); 1898 1899 hrtimer_cancel(&i2c_imx->slave_timer); 1900 1901 /* remove adapter */ 1902 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1903 i2c_del_adapter(&i2c_imx->adapter); 1904 1905 if (i2c_imx->dma) 1906 i2c_imx_dma_free(i2c_imx); 1907 1908 if (ret >= 0) { 1909 /* setup chip registers to defaults */ 1910 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1911 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1912 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1913 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1914 } 1915 1916 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1917 irq = platform_get_irq(pdev, 0); 1918 if (irq >= 0) 1919 free_irq(irq, i2c_imx); 1920 1921 pm_runtime_put_noidle(&pdev->dev); 1922 pm_runtime_disable(&pdev->dev); 1923 } 1924 1925 static int i2c_imx_runtime_suspend(struct device *dev) 1926 { 1927 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1928 int ret; 1929 1930 ret = pinctrl_pm_select_sleep_state(dev); 1931 if (ret) 1932 return ret; 1933 1934 clk_disable(i2c_imx->clk); 1935 1936 return 0; 1937 } 1938 1939 static int i2c_imx_runtime_resume(struct device *dev) 1940 { 1941 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1942 int ret; 1943 1944 ret = pinctrl_pm_select_default_state(dev); 1945 if (ret) 1946 return ret; 1947 1948 ret = clk_enable(i2c_imx->clk); 1949 if (ret) { 1950 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1951 pinctrl_pm_select_sleep_state(dev); 1952 return ret; 1953 } 1954 1955 return 0; 1956 } 1957 1958 static int __maybe_unused i2c_imx_suspend_noirq(struct device *dev) 1959 { 1960 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1961 int ret; 1962 1963 i2c_mark_adapter_suspended(&i2c_imx->adapter); 1964 1965 /* 1966 * Cancel the slave timer before powering down to prevent 1967 * i2c_imx_slave_timeout() from accessing hardware registers 1968 * while the clock is disabled. 1969 */ 1970 hrtimer_cancel(&i2c_imx->slave_timer); 1971 1972 ret = pm_runtime_force_suspend(dev); 1973 if (ret) { 1974 i2c_mark_adapter_resumed(&i2c_imx->adapter); 1975 if (i2c_imx->slave) { 1976 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY); 1977 hrtimer_restart(&i2c_imx->slave_timer); 1978 } 1979 return ret; 1980 } 1981 1982 return 0; 1983 } 1984 1985 static int __maybe_unused i2c_imx_resume_noirq(struct device *dev) 1986 { 1987 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1988 int ret; 1989 1990 ret = pm_runtime_force_resume(dev); 1991 if (ret) 1992 return ret; 1993 1994 i2c_mark_adapter_resumed(&i2c_imx->adapter); 1995 1996 return 0; 1997 } 1998 1999 static int i2c_imx_suspend(struct device *dev) 2000 { 2001 /* 2002 * Some I2C devices may need the I2C controller to remain active 2003 * during resume_noirq() or suspend_noirq(). If the controller is 2004 * autosuspended, there is no way to wake it up once runtime PM is 2005 * disabled (in suspend_late()). 2006 * 2007 * During system resume, the I2C controller will be available only 2008 * after runtime PM is re-enabled (in resume_early()). However, this 2009 * may be too late for some devices. 2010 * 2011 * Wake up the controller in the suspend() callback while runtime PM 2012 * is still enabled. The I2C controller will remain available until 2013 * the suspend_noirq() callback (pm_runtime_force_suspend()) is 2014 * called. During resume, the I2C controller can be restored by the 2015 * resume_noirq() callback (pm_runtime_force_resume()). 2016 * 2017 * Finally, the resume() callback re-enables autosuspend, ensuring 2018 * the I2C controller remains available until the system enters 2019 * suspend_noirq() and from resume_noirq(). 2020 */ 2021 return pm_runtime_resume_and_get(dev); 2022 } 2023 2024 static int i2c_imx_resume(struct device *dev) 2025 { 2026 pm_runtime_put_autosuspend(dev); 2027 2028 return 0; 2029 } 2030 2031 static const struct dev_pm_ops i2c_imx_pm_ops = { 2032 NOIRQ_SYSTEM_SLEEP_PM_OPS(i2c_imx_suspend_noirq, 2033 i2c_imx_resume_noirq) 2034 SYSTEM_SLEEP_PM_OPS(i2c_imx_suspend, i2c_imx_resume) 2035 RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL) 2036 }; 2037 2038 static struct platform_driver i2c_imx_driver = { 2039 .probe = i2c_imx_probe, 2040 .remove = i2c_imx_remove, 2041 .driver = { 2042 .name = DRIVER_NAME, 2043 .pm = pm_ptr(&i2c_imx_pm_ops), 2044 .of_match_table = i2c_imx_dt_ids, 2045 .acpi_match_table = i2c_imx_acpi_ids, 2046 }, 2047 .id_table = imx_i2c_devtype, 2048 }; 2049 2050 static int __init i2c_adap_imx_init(void) 2051 { 2052 return platform_driver_register(&i2c_imx_driver); 2053 } 2054 subsys_initcall(i2c_adap_imx_init); 2055 2056 static void __exit i2c_adap_imx_exit(void) 2057 { 2058 platform_driver_unregister(&i2c_imx_driver); 2059 } 2060 module_exit(i2c_adap_imx_exit); 2061 2062 MODULE_LICENSE("GPL"); 2063 MODULE_AUTHOR("Darius Augulis"); 2064 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 2065 MODULE_ALIAS("platform:" DRIVER_NAME); 2066