1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * This is i.MX low power i2c controller driver. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/errno.h> 13 #include <linux/i2c.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/sched.h> 25 #include <linux/slab.h> 26 27 #define DRIVER_NAME "imx-lpi2c" 28 29 #define LPI2C_PARAM 0x04 /* i2c RX/TX FIFO size */ 30 #define LPI2C_MCR 0x10 /* i2c contrl register */ 31 #define LPI2C_MSR 0x14 /* i2c status register */ 32 #define LPI2C_MIER 0x18 /* i2c interrupt enable */ 33 #define LPI2C_MCFGR0 0x20 /* i2c master configuration */ 34 #define LPI2C_MCFGR1 0x24 /* i2c master configuration */ 35 #define LPI2C_MCFGR2 0x28 /* i2c master configuration */ 36 #define LPI2C_MCFGR3 0x2C /* i2c master configuration */ 37 #define LPI2C_MCCR0 0x48 /* i2c master clk configuration */ 38 #define LPI2C_MCCR1 0x50 /* i2c master clk configuration */ 39 #define LPI2C_MFCR 0x58 /* i2c master FIFO control */ 40 #define LPI2C_MFSR 0x5C /* i2c master FIFO status */ 41 #define LPI2C_MTDR 0x60 /* i2c master TX data register */ 42 #define LPI2C_MRDR 0x70 /* i2c master RX data register */ 43 44 /* i2c command */ 45 #define TRAN_DATA 0X00 46 #define RECV_DATA 0X01 47 #define GEN_STOP 0X02 48 #define RECV_DISCARD 0X03 49 #define GEN_START 0X04 50 #define START_NACK 0X05 51 #define START_HIGH 0X06 52 #define START_HIGH_NACK 0X07 53 54 #define MCR_MEN BIT(0) 55 #define MCR_RST BIT(1) 56 #define MCR_DOZEN BIT(2) 57 #define MCR_DBGEN BIT(3) 58 #define MCR_RTF BIT(8) 59 #define MCR_RRF BIT(9) 60 #define MSR_TDF BIT(0) 61 #define MSR_RDF BIT(1) 62 #define MSR_SDF BIT(9) 63 #define MSR_NDF BIT(10) 64 #define MSR_ALF BIT(11) 65 #define MSR_MBF BIT(24) 66 #define MSR_BBF BIT(25) 67 #define MIER_TDIE BIT(0) 68 #define MIER_RDIE BIT(1) 69 #define MIER_SDIE BIT(9) 70 #define MIER_NDIE BIT(10) 71 #define MCFGR1_AUTOSTOP BIT(8) 72 #define MCFGR1_IGNACK BIT(9) 73 #define MRDR_RXEMPTY BIT(14) 74 75 #define I2C_CLK_RATIO 2 76 #define CHUNK_DATA 256 77 78 #define I2C_PM_TIMEOUT 10 /* ms */ 79 80 enum lpi2c_imx_mode { 81 STANDARD, /* 100+Kbps */ 82 FAST, /* 400+Kbps */ 83 FAST_PLUS, /* 1.0+Mbps */ 84 HS, /* 3.4+Mbps */ 85 ULTRA_FAST, /* 5.0+Mbps */ 86 }; 87 88 enum lpi2c_imx_pincfg { 89 TWO_PIN_OD, 90 TWO_PIN_OO, 91 TWO_PIN_PP, 92 FOUR_PIN_PP, 93 }; 94 95 struct lpi2c_imx_struct { 96 struct i2c_adapter adapter; 97 struct clk *clk; 98 void __iomem *base; 99 __u8 *rx_buf; 100 __u8 *tx_buf; 101 struct completion complete; 102 unsigned int msglen; 103 unsigned int delivered; 104 unsigned int block_data; 105 unsigned int bitrate; 106 unsigned int txfifosize; 107 unsigned int rxfifosize; 108 enum lpi2c_imx_mode mode; 109 }; 110 111 static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx, 112 unsigned int enable) 113 { 114 writel(enable, lpi2c_imx->base + LPI2C_MIER); 115 } 116 117 static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx) 118 { 119 unsigned long orig_jiffies = jiffies; 120 unsigned int temp; 121 122 while (1) { 123 temp = readl(lpi2c_imx->base + LPI2C_MSR); 124 125 /* check for arbitration lost, clear if set */ 126 if (temp & MSR_ALF) { 127 writel(temp, lpi2c_imx->base + LPI2C_MSR); 128 return -EAGAIN; 129 } 130 131 if (temp & (MSR_BBF | MSR_MBF)) 132 break; 133 134 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 135 dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n"); 136 return -ETIMEDOUT; 137 } 138 schedule(); 139 } 140 141 return 0; 142 } 143 144 static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx) 145 { 146 unsigned int bitrate = lpi2c_imx->bitrate; 147 enum lpi2c_imx_mode mode; 148 149 if (bitrate < I2C_MAX_FAST_MODE_FREQ) 150 mode = STANDARD; 151 else if (bitrate < I2C_MAX_FAST_MODE_PLUS_FREQ) 152 mode = FAST; 153 else if (bitrate < I2C_MAX_HIGH_SPEED_MODE_FREQ) 154 mode = FAST_PLUS; 155 else if (bitrate < I2C_MAX_ULTRA_FAST_MODE_FREQ) 156 mode = HS; 157 else 158 mode = ULTRA_FAST; 159 160 lpi2c_imx->mode = mode; 161 } 162 163 static int lpi2c_imx_start(struct lpi2c_imx_struct *lpi2c_imx, 164 struct i2c_msg *msgs) 165 { 166 unsigned int temp; 167 168 temp = readl(lpi2c_imx->base + LPI2C_MCR); 169 temp |= MCR_RRF | MCR_RTF; 170 writel(temp, lpi2c_imx->base + LPI2C_MCR); 171 writel(0x7f00, lpi2c_imx->base + LPI2C_MSR); 172 173 temp = i2c_8bit_addr_from_msg(msgs) | (GEN_START << 8); 174 writel(temp, lpi2c_imx->base + LPI2C_MTDR); 175 176 return lpi2c_imx_bus_busy(lpi2c_imx); 177 } 178 179 static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx) 180 { 181 unsigned long orig_jiffies = jiffies; 182 unsigned int temp; 183 184 writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR); 185 186 do { 187 temp = readl(lpi2c_imx->base + LPI2C_MSR); 188 if (temp & MSR_SDF) 189 break; 190 191 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 192 dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n"); 193 break; 194 } 195 schedule(); 196 197 } while (1); 198 } 199 200 /* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */ 201 static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx) 202 { 203 u8 prescale, filt, sethold, clkhi, clklo, datavd; 204 unsigned int clk_rate, clk_cycle; 205 enum lpi2c_imx_pincfg pincfg; 206 unsigned int temp; 207 208 lpi2c_imx_set_mode(lpi2c_imx); 209 210 clk_rate = clk_get_rate(lpi2c_imx->clk); 211 if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST) 212 filt = 0; 213 else 214 filt = 2; 215 216 for (prescale = 0; prescale <= 7; prescale++) { 217 clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate) 218 - 3 - (filt >> 1); 219 clkhi = (clk_cycle + I2C_CLK_RATIO) / (I2C_CLK_RATIO + 1); 220 clklo = clk_cycle - clkhi; 221 if (clklo < 64) 222 break; 223 } 224 225 if (prescale > 7) 226 return -EINVAL; 227 228 /* set MCFGR1: PINCFG, PRESCALE, IGNACK */ 229 if (lpi2c_imx->mode == ULTRA_FAST) 230 pincfg = TWO_PIN_OO; 231 else 232 pincfg = TWO_PIN_OD; 233 temp = prescale | pincfg << 24; 234 235 if (lpi2c_imx->mode == ULTRA_FAST) 236 temp |= MCFGR1_IGNACK; 237 238 writel(temp, lpi2c_imx->base + LPI2C_MCFGR1); 239 240 /* set MCFGR2: FILTSDA, FILTSCL */ 241 temp = (filt << 16) | (filt << 24); 242 writel(temp, lpi2c_imx->base + LPI2C_MCFGR2); 243 244 /* set MCCR: DATAVD, SETHOLD, CLKHI, CLKLO */ 245 sethold = clkhi; 246 datavd = clkhi >> 1; 247 temp = datavd << 24 | sethold << 16 | clkhi << 8 | clklo; 248 249 if (lpi2c_imx->mode == HS) 250 writel(temp, lpi2c_imx->base + LPI2C_MCCR1); 251 else 252 writel(temp, lpi2c_imx->base + LPI2C_MCCR0); 253 254 return 0; 255 } 256 257 static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx) 258 { 259 unsigned int temp; 260 int ret; 261 262 ret = pm_runtime_resume_and_get(lpi2c_imx->adapter.dev.parent); 263 if (ret < 0) 264 return ret; 265 266 temp = MCR_RST; 267 writel(temp, lpi2c_imx->base + LPI2C_MCR); 268 writel(0, lpi2c_imx->base + LPI2C_MCR); 269 270 ret = lpi2c_imx_config(lpi2c_imx); 271 if (ret) 272 goto rpm_put; 273 274 temp = readl(lpi2c_imx->base + LPI2C_MCR); 275 temp |= MCR_MEN; 276 writel(temp, lpi2c_imx->base + LPI2C_MCR); 277 278 return 0; 279 280 rpm_put: 281 pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent); 282 pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent); 283 284 return ret; 285 } 286 287 static int lpi2c_imx_master_disable(struct lpi2c_imx_struct *lpi2c_imx) 288 { 289 u32 temp; 290 291 temp = readl(lpi2c_imx->base + LPI2C_MCR); 292 temp &= ~MCR_MEN; 293 writel(temp, lpi2c_imx->base + LPI2C_MCR); 294 295 pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent); 296 pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent); 297 298 return 0; 299 } 300 301 static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx) 302 { 303 unsigned long timeout; 304 305 timeout = wait_for_completion_timeout(&lpi2c_imx->complete, HZ); 306 307 return timeout ? 0 : -ETIMEDOUT; 308 } 309 310 static int lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct *lpi2c_imx) 311 { 312 unsigned long orig_jiffies = jiffies; 313 u32 txcnt; 314 315 do { 316 txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff; 317 318 if (readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) { 319 dev_dbg(&lpi2c_imx->adapter.dev, "NDF detected\n"); 320 return -EIO; 321 } 322 323 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 324 dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n"); 325 return -ETIMEDOUT; 326 } 327 schedule(); 328 329 } while (txcnt); 330 331 return 0; 332 } 333 334 static void lpi2c_imx_set_tx_watermark(struct lpi2c_imx_struct *lpi2c_imx) 335 { 336 writel(lpi2c_imx->txfifosize >> 1, lpi2c_imx->base + LPI2C_MFCR); 337 } 338 339 static void lpi2c_imx_set_rx_watermark(struct lpi2c_imx_struct *lpi2c_imx) 340 { 341 unsigned int temp, remaining; 342 343 remaining = lpi2c_imx->msglen - lpi2c_imx->delivered; 344 345 if (remaining > (lpi2c_imx->rxfifosize >> 1)) 346 temp = lpi2c_imx->rxfifosize >> 1; 347 else 348 temp = 0; 349 350 writel(temp << 16, lpi2c_imx->base + LPI2C_MFCR); 351 } 352 353 static void lpi2c_imx_write_txfifo(struct lpi2c_imx_struct *lpi2c_imx) 354 { 355 unsigned int data, txcnt; 356 357 txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff; 358 359 while (txcnt < lpi2c_imx->txfifosize) { 360 if (lpi2c_imx->delivered == lpi2c_imx->msglen) 361 break; 362 363 data = lpi2c_imx->tx_buf[lpi2c_imx->delivered++]; 364 writel(data, lpi2c_imx->base + LPI2C_MTDR); 365 txcnt++; 366 } 367 368 if (lpi2c_imx->delivered < lpi2c_imx->msglen) 369 lpi2c_imx_intctrl(lpi2c_imx, MIER_TDIE | MIER_NDIE); 370 else 371 complete(&lpi2c_imx->complete); 372 } 373 374 static void lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct *lpi2c_imx) 375 { 376 unsigned int blocklen, remaining; 377 unsigned int temp, data; 378 379 do { 380 data = readl(lpi2c_imx->base + LPI2C_MRDR); 381 if (data & MRDR_RXEMPTY) 382 break; 383 384 lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff; 385 } while (1); 386 387 /* 388 * First byte is the length of remaining packet in the SMBus block 389 * data read. Add it to msgs->len. 390 */ 391 if (lpi2c_imx->block_data) { 392 blocklen = lpi2c_imx->rx_buf[0]; 393 lpi2c_imx->msglen += blocklen; 394 } 395 396 remaining = lpi2c_imx->msglen - lpi2c_imx->delivered; 397 398 if (!remaining) { 399 complete(&lpi2c_imx->complete); 400 return; 401 } 402 403 /* not finished, still waiting for rx data */ 404 lpi2c_imx_set_rx_watermark(lpi2c_imx); 405 406 /* multiple receive commands */ 407 if (lpi2c_imx->block_data) { 408 lpi2c_imx->block_data = 0; 409 temp = remaining; 410 temp |= (RECV_DATA << 8); 411 writel(temp, lpi2c_imx->base + LPI2C_MTDR); 412 } else if (!(lpi2c_imx->delivered & 0xff)) { 413 temp = (remaining > CHUNK_DATA ? CHUNK_DATA : remaining) - 1; 414 temp |= (RECV_DATA << 8); 415 writel(temp, lpi2c_imx->base + LPI2C_MTDR); 416 } 417 418 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE); 419 } 420 421 static void lpi2c_imx_write(struct lpi2c_imx_struct *lpi2c_imx, 422 struct i2c_msg *msgs) 423 { 424 lpi2c_imx->tx_buf = msgs->buf; 425 lpi2c_imx_set_tx_watermark(lpi2c_imx); 426 lpi2c_imx_write_txfifo(lpi2c_imx); 427 } 428 429 static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx, 430 struct i2c_msg *msgs) 431 { 432 unsigned int temp; 433 434 lpi2c_imx->rx_buf = msgs->buf; 435 lpi2c_imx->block_data = msgs->flags & I2C_M_RECV_LEN; 436 437 lpi2c_imx_set_rx_watermark(lpi2c_imx); 438 temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1; 439 temp |= (RECV_DATA << 8); 440 writel(temp, lpi2c_imx->base + LPI2C_MTDR); 441 442 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE); 443 } 444 445 static int lpi2c_imx_xfer(struct i2c_adapter *adapter, 446 struct i2c_msg *msgs, int num) 447 { 448 struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(adapter); 449 unsigned int temp; 450 int i, result; 451 452 result = lpi2c_imx_master_enable(lpi2c_imx); 453 if (result) 454 return result; 455 456 for (i = 0; i < num; i++) { 457 result = lpi2c_imx_start(lpi2c_imx, &msgs[i]); 458 if (result) 459 goto disable; 460 461 /* quick smbus */ 462 if (num == 1 && msgs[0].len == 0) 463 goto stop; 464 465 lpi2c_imx->delivered = 0; 466 lpi2c_imx->msglen = msgs[i].len; 467 init_completion(&lpi2c_imx->complete); 468 469 if (msgs[i].flags & I2C_M_RD) 470 lpi2c_imx_read(lpi2c_imx, &msgs[i]); 471 else 472 lpi2c_imx_write(lpi2c_imx, &msgs[i]); 473 474 result = lpi2c_imx_msg_complete(lpi2c_imx); 475 if (result) 476 goto stop; 477 478 if (!(msgs[i].flags & I2C_M_RD)) { 479 result = lpi2c_imx_txfifo_empty(lpi2c_imx); 480 if (result) 481 goto stop; 482 } 483 } 484 485 stop: 486 lpi2c_imx_stop(lpi2c_imx); 487 488 temp = readl(lpi2c_imx->base + LPI2C_MSR); 489 if ((temp & MSR_NDF) && !result) 490 result = -EIO; 491 492 disable: 493 lpi2c_imx_master_disable(lpi2c_imx); 494 495 dev_dbg(&lpi2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 496 (result < 0) ? "error" : "success msg", 497 (result < 0) ? result : num); 498 499 return (result < 0) ? result : num; 500 } 501 502 static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) 503 { 504 struct lpi2c_imx_struct *lpi2c_imx = dev_id; 505 unsigned int temp; 506 507 lpi2c_imx_intctrl(lpi2c_imx, 0); 508 temp = readl(lpi2c_imx->base + LPI2C_MSR); 509 510 if (temp & MSR_RDF) 511 lpi2c_imx_read_rxfifo(lpi2c_imx); 512 513 if (temp & MSR_TDF) 514 lpi2c_imx_write_txfifo(lpi2c_imx); 515 516 if (temp & MSR_NDF) 517 complete(&lpi2c_imx->complete); 518 519 return IRQ_HANDLED; 520 } 521 522 static u32 lpi2c_imx_func(struct i2c_adapter *adapter) 523 { 524 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 525 I2C_FUNC_SMBUS_READ_BLOCK_DATA; 526 } 527 528 static const struct i2c_algorithm lpi2c_imx_algo = { 529 .master_xfer = lpi2c_imx_xfer, 530 .functionality = lpi2c_imx_func, 531 }; 532 533 static const struct of_device_id lpi2c_imx_of_match[] = { 534 { .compatible = "fsl,imx7ulp-lpi2c" }, 535 { }, 536 }; 537 MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match); 538 539 static int lpi2c_imx_probe(struct platform_device *pdev) 540 { 541 struct lpi2c_imx_struct *lpi2c_imx; 542 unsigned int temp; 543 int irq, ret; 544 545 lpi2c_imx = devm_kzalloc(&pdev->dev, sizeof(*lpi2c_imx), GFP_KERNEL); 546 if (!lpi2c_imx) 547 return -ENOMEM; 548 549 lpi2c_imx->base = devm_platform_ioremap_resource(pdev, 0); 550 if (IS_ERR(lpi2c_imx->base)) 551 return PTR_ERR(lpi2c_imx->base); 552 553 irq = platform_get_irq(pdev, 0); 554 if (irq < 0) 555 return irq; 556 557 lpi2c_imx->adapter.owner = THIS_MODULE; 558 lpi2c_imx->adapter.algo = &lpi2c_imx_algo; 559 lpi2c_imx->adapter.dev.parent = &pdev->dev; 560 lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node; 561 strlcpy(lpi2c_imx->adapter.name, pdev->name, 562 sizeof(lpi2c_imx->adapter.name)); 563 564 lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 565 if (IS_ERR(lpi2c_imx->clk)) { 566 dev_err(&pdev->dev, "can't get I2C peripheral clock\n"); 567 return PTR_ERR(lpi2c_imx->clk); 568 } 569 570 ret = of_property_read_u32(pdev->dev.of_node, 571 "clock-frequency", &lpi2c_imx->bitrate); 572 if (ret) 573 lpi2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 574 575 ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0, 576 pdev->name, lpi2c_imx); 577 if (ret) { 578 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 579 return ret; 580 } 581 582 i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx); 583 platform_set_drvdata(pdev, lpi2c_imx); 584 585 ret = clk_prepare_enable(lpi2c_imx->clk); 586 if (ret) { 587 dev_err(&pdev->dev, "clk enable failed %d\n", ret); 588 return ret; 589 } 590 591 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 592 pm_runtime_use_autosuspend(&pdev->dev); 593 pm_runtime_get_noresume(&pdev->dev); 594 pm_runtime_set_active(&pdev->dev); 595 pm_runtime_enable(&pdev->dev); 596 597 temp = readl(lpi2c_imx->base + LPI2C_PARAM); 598 lpi2c_imx->txfifosize = 1 << (temp & 0x0f); 599 lpi2c_imx->rxfifosize = 1 << ((temp >> 8) & 0x0f); 600 601 ret = i2c_add_adapter(&lpi2c_imx->adapter); 602 if (ret) 603 goto rpm_disable; 604 605 pm_runtime_mark_last_busy(&pdev->dev); 606 pm_runtime_put_autosuspend(&pdev->dev); 607 608 dev_info(&lpi2c_imx->adapter.dev, "LPI2C adapter registered\n"); 609 610 return 0; 611 612 rpm_disable: 613 pm_runtime_put(&pdev->dev); 614 pm_runtime_disable(&pdev->dev); 615 pm_runtime_dont_use_autosuspend(&pdev->dev); 616 617 return ret; 618 } 619 620 static int lpi2c_imx_remove(struct platform_device *pdev) 621 { 622 struct lpi2c_imx_struct *lpi2c_imx = platform_get_drvdata(pdev); 623 624 i2c_del_adapter(&lpi2c_imx->adapter); 625 626 pm_runtime_disable(&pdev->dev); 627 pm_runtime_dont_use_autosuspend(&pdev->dev); 628 629 return 0; 630 } 631 632 static int __maybe_unused lpi2c_runtime_suspend(struct device *dev) 633 { 634 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 635 636 clk_disable_unprepare(lpi2c_imx->clk); 637 pinctrl_pm_select_sleep_state(dev); 638 639 return 0; 640 } 641 642 static int __maybe_unused lpi2c_runtime_resume(struct device *dev) 643 { 644 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 645 int ret; 646 647 pinctrl_pm_select_default_state(dev); 648 ret = clk_prepare_enable(lpi2c_imx->clk); 649 if (ret) { 650 dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret); 651 return ret; 652 } 653 654 return 0; 655 } 656 657 static const struct dev_pm_ops lpi2c_pm_ops = { 658 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 659 pm_runtime_force_resume) 660 SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend, 661 lpi2c_runtime_resume, NULL) 662 }; 663 664 static struct platform_driver lpi2c_imx_driver = { 665 .probe = lpi2c_imx_probe, 666 .remove = lpi2c_imx_remove, 667 .driver = { 668 .name = DRIVER_NAME, 669 .of_match_table = lpi2c_imx_of_match, 670 .pm = &lpi2c_pm_ops, 671 }, 672 }; 673 674 module_platform_driver(lpi2c_imx_driver); 675 676 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>"); 677 MODULE_DESCRIPTION("I2C adapter driver for LPI2C bus"); 678 MODULE_LICENSE("GPL"); 679