1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * This is i.MX low power i2c controller driver. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/errno.h> 13 #include <linux/i2c.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/sched.h> 25 #include <linux/slab.h> 26 27 #define DRIVER_NAME "imx-lpi2c" 28 29 #define LPI2C_PARAM 0x04 /* i2c RX/TX FIFO size */ 30 #define LPI2C_MCR 0x10 /* i2c contrl register */ 31 #define LPI2C_MSR 0x14 /* i2c status register */ 32 #define LPI2C_MIER 0x18 /* i2c interrupt enable */ 33 #define LPI2C_MCFGR0 0x20 /* i2c master configuration */ 34 #define LPI2C_MCFGR1 0x24 /* i2c master configuration */ 35 #define LPI2C_MCFGR2 0x28 /* i2c master configuration */ 36 #define LPI2C_MCFGR3 0x2C /* i2c master configuration */ 37 #define LPI2C_MCCR0 0x48 /* i2c master clk configuration */ 38 #define LPI2C_MCCR1 0x50 /* i2c master clk configuration */ 39 #define LPI2C_MFCR 0x58 /* i2c master FIFO control */ 40 #define LPI2C_MFSR 0x5C /* i2c master FIFO status */ 41 #define LPI2C_MTDR 0x60 /* i2c master TX data register */ 42 #define LPI2C_MRDR 0x70 /* i2c master RX data register */ 43 44 /* i2c command */ 45 #define TRAN_DATA 0X00 46 #define RECV_DATA 0X01 47 #define GEN_STOP 0X02 48 #define RECV_DISCARD 0X03 49 #define GEN_START 0X04 50 #define START_NACK 0X05 51 #define START_HIGH 0X06 52 #define START_HIGH_NACK 0X07 53 54 #define MCR_MEN BIT(0) 55 #define MCR_RST BIT(1) 56 #define MCR_DOZEN BIT(2) 57 #define MCR_DBGEN BIT(3) 58 #define MCR_RTF BIT(8) 59 #define MCR_RRF BIT(9) 60 #define MSR_TDF BIT(0) 61 #define MSR_RDF BIT(1) 62 #define MSR_SDF BIT(9) 63 #define MSR_NDF BIT(10) 64 #define MSR_ALF BIT(11) 65 #define MSR_MBF BIT(24) 66 #define MSR_BBF BIT(25) 67 #define MIER_TDIE BIT(0) 68 #define MIER_RDIE BIT(1) 69 #define MIER_SDIE BIT(9) 70 #define MIER_NDIE BIT(10) 71 #define MCFGR1_AUTOSTOP BIT(8) 72 #define MCFGR1_IGNACK BIT(9) 73 #define MRDR_RXEMPTY BIT(14) 74 75 #define I2C_CLK_RATIO 2 76 #define CHUNK_DATA 256 77 78 #define I2C_PM_TIMEOUT 10 /* ms */ 79 80 enum lpi2c_imx_mode { 81 STANDARD, /* 100+Kbps */ 82 FAST, /* 400+Kbps */ 83 FAST_PLUS, /* 1.0+Mbps */ 84 HS, /* 3.4+Mbps */ 85 ULTRA_FAST, /* 5.0+Mbps */ 86 }; 87 88 enum lpi2c_imx_pincfg { 89 TWO_PIN_OD, 90 TWO_PIN_OO, 91 TWO_PIN_PP, 92 FOUR_PIN_PP, 93 }; 94 95 struct lpi2c_imx_struct { 96 struct i2c_adapter adapter; 97 int num_clks; 98 struct clk_bulk_data *clks; 99 void __iomem *base; 100 __u8 *rx_buf; 101 __u8 *tx_buf; 102 struct completion complete; 103 unsigned int msglen; 104 unsigned int delivered; 105 unsigned int block_data; 106 unsigned int bitrate; 107 unsigned int txfifosize; 108 unsigned int rxfifosize; 109 enum lpi2c_imx_mode mode; 110 }; 111 112 static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx, 113 unsigned int enable) 114 { 115 writel(enable, lpi2c_imx->base + LPI2C_MIER); 116 } 117 118 static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx) 119 { 120 unsigned long orig_jiffies = jiffies; 121 unsigned int temp; 122 123 while (1) { 124 temp = readl(lpi2c_imx->base + LPI2C_MSR); 125 126 /* check for arbitration lost, clear if set */ 127 if (temp & MSR_ALF) { 128 writel(temp, lpi2c_imx->base + LPI2C_MSR); 129 return -EAGAIN; 130 } 131 132 if (temp & (MSR_BBF | MSR_MBF)) 133 break; 134 135 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 136 dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n"); 137 return -ETIMEDOUT; 138 } 139 schedule(); 140 } 141 142 return 0; 143 } 144 145 static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx) 146 { 147 unsigned int bitrate = lpi2c_imx->bitrate; 148 enum lpi2c_imx_mode mode; 149 150 if (bitrate < I2C_MAX_FAST_MODE_FREQ) 151 mode = STANDARD; 152 else if (bitrate < I2C_MAX_FAST_MODE_PLUS_FREQ) 153 mode = FAST; 154 else if (bitrate < I2C_MAX_HIGH_SPEED_MODE_FREQ) 155 mode = FAST_PLUS; 156 else if (bitrate < I2C_MAX_ULTRA_FAST_MODE_FREQ) 157 mode = HS; 158 else 159 mode = ULTRA_FAST; 160 161 lpi2c_imx->mode = mode; 162 } 163 164 static int lpi2c_imx_start(struct lpi2c_imx_struct *lpi2c_imx, 165 struct i2c_msg *msgs) 166 { 167 unsigned int temp; 168 169 temp = readl(lpi2c_imx->base + LPI2C_MCR); 170 temp |= MCR_RRF | MCR_RTF; 171 writel(temp, lpi2c_imx->base + LPI2C_MCR); 172 writel(0x7f00, lpi2c_imx->base + LPI2C_MSR); 173 174 temp = i2c_8bit_addr_from_msg(msgs) | (GEN_START << 8); 175 writel(temp, lpi2c_imx->base + LPI2C_MTDR); 176 177 return lpi2c_imx_bus_busy(lpi2c_imx); 178 } 179 180 static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx) 181 { 182 unsigned long orig_jiffies = jiffies; 183 unsigned int temp; 184 185 writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR); 186 187 do { 188 temp = readl(lpi2c_imx->base + LPI2C_MSR); 189 if (temp & MSR_SDF) 190 break; 191 192 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 193 dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n"); 194 break; 195 } 196 schedule(); 197 198 } while (1); 199 } 200 201 /* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */ 202 static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx) 203 { 204 u8 prescale, filt, sethold, datavd; 205 unsigned int clk_rate, clk_cycle, clkhi, clklo; 206 enum lpi2c_imx_pincfg pincfg; 207 unsigned int temp; 208 209 lpi2c_imx_set_mode(lpi2c_imx); 210 211 clk_rate = clk_get_rate(lpi2c_imx->clks[0].clk); 212 if (!clk_rate) 213 return -EINVAL; 214 215 if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST) 216 filt = 0; 217 else 218 filt = 2; 219 220 for (prescale = 0; prescale <= 7; prescale++) { 221 clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate) 222 - 3 - (filt >> 1); 223 clkhi = DIV_ROUND_UP(clk_cycle, I2C_CLK_RATIO + 1); 224 clklo = clk_cycle - clkhi; 225 if (clklo < 64) 226 break; 227 } 228 229 if (prescale > 7) 230 return -EINVAL; 231 232 /* set MCFGR1: PINCFG, PRESCALE, IGNACK */ 233 if (lpi2c_imx->mode == ULTRA_FAST) 234 pincfg = TWO_PIN_OO; 235 else 236 pincfg = TWO_PIN_OD; 237 temp = prescale | pincfg << 24; 238 239 if (lpi2c_imx->mode == ULTRA_FAST) 240 temp |= MCFGR1_IGNACK; 241 242 writel(temp, lpi2c_imx->base + LPI2C_MCFGR1); 243 244 /* set MCFGR2: FILTSDA, FILTSCL */ 245 temp = (filt << 16) | (filt << 24); 246 writel(temp, lpi2c_imx->base + LPI2C_MCFGR2); 247 248 /* set MCCR: DATAVD, SETHOLD, CLKHI, CLKLO */ 249 sethold = clkhi; 250 datavd = clkhi >> 1; 251 temp = datavd << 24 | sethold << 16 | clkhi << 8 | clklo; 252 253 if (lpi2c_imx->mode == HS) 254 writel(temp, lpi2c_imx->base + LPI2C_MCCR1); 255 else 256 writel(temp, lpi2c_imx->base + LPI2C_MCCR0); 257 258 return 0; 259 } 260 261 static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx) 262 { 263 unsigned int temp; 264 int ret; 265 266 ret = pm_runtime_resume_and_get(lpi2c_imx->adapter.dev.parent); 267 if (ret < 0) 268 return ret; 269 270 temp = MCR_RST; 271 writel(temp, lpi2c_imx->base + LPI2C_MCR); 272 writel(0, lpi2c_imx->base + LPI2C_MCR); 273 274 ret = lpi2c_imx_config(lpi2c_imx); 275 if (ret) 276 goto rpm_put; 277 278 temp = readl(lpi2c_imx->base + LPI2C_MCR); 279 temp |= MCR_MEN; 280 writel(temp, lpi2c_imx->base + LPI2C_MCR); 281 282 return 0; 283 284 rpm_put: 285 pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent); 286 pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent); 287 288 return ret; 289 } 290 291 static int lpi2c_imx_master_disable(struct lpi2c_imx_struct *lpi2c_imx) 292 { 293 u32 temp; 294 295 temp = readl(lpi2c_imx->base + LPI2C_MCR); 296 temp &= ~MCR_MEN; 297 writel(temp, lpi2c_imx->base + LPI2C_MCR); 298 299 pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent); 300 pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent); 301 302 return 0; 303 } 304 305 static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx) 306 { 307 unsigned long timeout; 308 309 timeout = wait_for_completion_timeout(&lpi2c_imx->complete, HZ); 310 311 return timeout ? 0 : -ETIMEDOUT; 312 } 313 314 static int lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct *lpi2c_imx) 315 { 316 unsigned long orig_jiffies = jiffies; 317 u32 txcnt; 318 319 do { 320 txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff; 321 322 if (readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) { 323 dev_dbg(&lpi2c_imx->adapter.dev, "NDF detected\n"); 324 return -EIO; 325 } 326 327 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 328 dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n"); 329 return -ETIMEDOUT; 330 } 331 schedule(); 332 333 } while (txcnt); 334 335 return 0; 336 } 337 338 static void lpi2c_imx_set_tx_watermark(struct lpi2c_imx_struct *lpi2c_imx) 339 { 340 writel(lpi2c_imx->txfifosize >> 1, lpi2c_imx->base + LPI2C_MFCR); 341 } 342 343 static void lpi2c_imx_set_rx_watermark(struct lpi2c_imx_struct *lpi2c_imx) 344 { 345 unsigned int temp, remaining; 346 347 remaining = lpi2c_imx->msglen - lpi2c_imx->delivered; 348 349 if (remaining > (lpi2c_imx->rxfifosize >> 1)) 350 temp = lpi2c_imx->rxfifosize >> 1; 351 else 352 temp = 0; 353 354 writel(temp << 16, lpi2c_imx->base + LPI2C_MFCR); 355 } 356 357 static void lpi2c_imx_write_txfifo(struct lpi2c_imx_struct *lpi2c_imx) 358 { 359 unsigned int data, txcnt; 360 361 txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff; 362 363 while (txcnt < lpi2c_imx->txfifosize) { 364 if (lpi2c_imx->delivered == lpi2c_imx->msglen) 365 break; 366 367 data = lpi2c_imx->tx_buf[lpi2c_imx->delivered++]; 368 writel(data, lpi2c_imx->base + LPI2C_MTDR); 369 txcnt++; 370 } 371 372 if (lpi2c_imx->delivered < lpi2c_imx->msglen) 373 lpi2c_imx_intctrl(lpi2c_imx, MIER_TDIE | MIER_NDIE); 374 else 375 complete(&lpi2c_imx->complete); 376 } 377 378 static void lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct *lpi2c_imx) 379 { 380 unsigned int blocklen, remaining; 381 unsigned int temp, data; 382 383 do { 384 data = readl(lpi2c_imx->base + LPI2C_MRDR); 385 if (data & MRDR_RXEMPTY) 386 break; 387 388 lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff; 389 } while (1); 390 391 /* 392 * First byte is the length of remaining packet in the SMBus block 393 * data read. Add it to msgs->len. 394 */ 395 if (lpi2c_imx->block_data) { 396 blocklen = lpi2c_imx->rx_buf[0]; 397 lpi2c_imx->msglen += blocklen; 398 } 399 400 remaining = lpi2c_imx->msglen - lpi2c_imx->delivered; 401 402 if (!remaining) { 403 complete(&lpi2c_imx->complete); 404 return; 405 } 406 407 /* not finished, still waiting for rx data */ 408 lpi2c_imx_set_rx_watermark(lpi2c_imx); 409 410 /* multiple receive commands */ 411 if (lpi2c_imx->block_data) { 412 lpi2c_imx->block_data = 0; 413 temp = remaining; 414 temp |= (RECV_DATA << 8); 415 writel(temp, lpi2c_imx->base + LPI2C_MTDR); 416 } else if (!(lpi2c_imx->delivered & 0xff)) { 417 temp = (remaining > CHUNK_DATA ? CHUNK_DATA : remaining) - 1; 418 temp |= (RECV_DATA << 8); 419 writel(temp, lpi2c_imx->base + LPI2C_MTDR); 420 } 421 422 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE); 423 } 424 425 static void lpi2c_imx_write(struct lpi2c_imx_struct *lpi2c_imx, 426 struct i2c_msg *msgs) 427 { 428 lpi2c_imx->tx_buf = msgs->buf; 429 lpi2c_imx_set_tx_watermark(lpi2c_imx); 430 lpi2c_imx_write_txfifo(lpi2c_imx); 431 } 432 433 static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx, 434 struct i2c_msg *msgs) 435 { 436 unsigned int temp; 437 438 lpi2c_imx->rx_buf = msgs->buf; 439 lpi2c_imx->block_data = msgs->flags & I2C_M_RECV_LEN; 440 441 lpi2c_imx_set_rx_watermark(lpi2c_imx); 442 temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1; 443 temp |= (RECV_DATA << 8); 444 writel(temp, lpi2c_imx->base + LPI2C_MTDR); 445 446 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE); 447 } 448 449 static int lpi2c_imx_xfer(struct i2c_adapter *adapter, 450 struct i2c_msg *msgs, int num) 451 { 452 struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(adapter); 453 unsigned int temp; 454 int i, result; 455 456 result = lpi2c_imx_master_enable(lpi2c_imx); 457 if (result) 458 return result; 459 460 for (i = 0; i < num; i++) { 461 result = lpi2c_imx_start(lpi2c_imx, &msgs[i]); 462 if (result) 463 goto disable; 464 465 /* quick smbus */ 466 if (num == 1 && msgs[0].len == 0) 467 goto stop; 468 469 lpi2c_imx->rx_buf = NULL; 470 lpi2c_imx->tx_buf = NULL; 471 lpi2c_imx->delivered = 0; 472 lpi2c_imx->msglen = msgs[i].len; 473 init_completion(&lpi2c_imx->complete); 474 475 if (msgs[i].flags & I2C_M_RD) 476 lpi2c_imx_read(lpi2c_imx, &msgs[i]); 477 else 478 lpi2c_imx_write(lpi2c_imx, &msgs[i]); 479 480 result = lpi2c_imx_msg_complete(lpi2c_imx); 481 if (result) 482 goto stop; 483 484 if (!(msgs[i].flags & I2C_M_RD)) { 485 result = lpi2c_imx_txfifo_empty(lpi2c_imx); 486 if (result) 487 goto stop; 488 } 489 } 490 491 stop: 492 lpi2c_imx_stop(lpi2c_imx); 493 494 temp = readl(lpi2c_imx->base + LPI2C_MSR); 495 if ((temp & MSR_NDF) && !result) 496 result = -EIO; 497 498 disable: 499 lpi2c_imx_master_disable(lpi2c_imx); 500 501 dev_dbg(&lpi2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 502 (result < 0) ? "error" : "success msg", 503 (result < 0) ? result : num); 504 505 return (result < 0) ? result : num; 506 } 507 508 static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) 509 { 510 struct lpi2c_imx_struct *lpi2c_imx = dev_id; 511 unsigned int enabled; 512 unsigned int temp; 513 514 enabled = readl(lpi2c_imx->base + LPI2C_MIER); 515 516 lpi2c_imx_intctrl(lpi2c_imx, 0); 517 temp = readl(lpi2c_imx->base + LPI2C_MSR); 518 temp &= enabled; 519 520 if (temp & MSR_RDF) 521 lpi2c_imx_read_rxfifo(lpi2c_imx); 522 523 if (temp & MSR_TDF) 524 lpi2c_imx_write_txfifo(lpi2c_imx); 525 526 if (temp & MSR_NDF) 527 complete(&lpi2c_imx->complete); 528 529 return IRQ_HANDLED; 530 } 531 532 static u32 lpi2c_imx_func(struct i2c_adapter *adapter) 533 { 534 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 535 I2C_FUNC_SMBUS_READ_BLOCK_DATA; 536 } 537 538 static const struct i2c_algorithm lpi2c_imx_algo = { 539 .master_xfer = lpi2c_imx_xfer, 540 .functionality = lpi2c_imx_func, 541 }; 542 543 static const struct of_device_id lpi2c_imx_of_match[] = { 544 { .compatible = "fsl,imx7ulp-lpi2c" }, 545 { }, 546 }; 547 MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match); 548 549 static int lpi2c_imx_probe(struct platform_device *pdev) 550 { 551 struct lpi2c_imx_struct *lpi2c_imx; 552 unsigned int temp; 553 int irq, ret; 554 555 lpi2c_imx = devm_kzalloc(&pdev->dev, sizeof(*lpi2c_imx), GFP_KERNEL); 556 if (!lpi2c_imx) 557 return -ENOMEM; 558 559 lpi2c_imx->base = devm_platform_ioremap_resource(pdev, 0); 560 if (IS_ERR(lpi2c_imx->base)) 561 return PTR_ERR(lpi2c_imx->base); 562 563 irq = platform_get_irq(pdev, 0); 564 if (irq < 0) 565 return irq; 566 567 lpi2c_imx->adapter.owner = THIS_MODULE; 568 lpi2c_imx->adapter.algo = &lpi2c_imx_algo; 569 lpi2c_imx->adapter.dev.parent = &pdev->dev; 570 lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node; 571 strscpy(lpi2c_imx->adapter.name, pdev->name, 572 sizeof(lpi2c_imx->adapter.name)); 573 574 ret = devm_clk_bulk_get_all(&pdev->dev, &lpi2c_imx->clks); 575 if (ret < 0) { 576 dev_err(&pdev->dev, "can't get I2C peripheral clock, ret=%d\n", ret); 577 return ret; 578 } 579 lpi2c_imx->num_clks = ret; 580 581 ret = of_property_read_u32(pdev->dev.of_node, 582 "clock-frequency", &lpi2c_imx->bitrate); 583 if (ret) 584 lpi2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 585 586 ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0, 587 pdev->name, lpi2c_imx); 588 if (ret) { 589 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 590 return ret; 591 } 592 593 i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx); 594 platform_set_drvdata(pdev, lpi2c_imx); 595 596 ret = clk_bulk_prepare_enable(lpi2c_imx->num_clks, lpi2c_imx->clks); 597 if (ret) 598 return ret; 599 600 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 601 pm_runtime_use_autosuspend(&pdev->dev); 602 pm_runtime_get_noresume(&pdev->dev); 603 pm_runtime_set_active(&pdev->dev); 604 pm_runtime_enable(&pdev->dev); 605 606 temp = readl(lpi2c_imx->base + LPI2C_PARAM); 607 lpi2c_imx->txfifosize = 1 << (temp & 0x0f); 608 lpi2c_imx->rxfifosize = 1 << ((temp >> 8) & 0x0f); 609 610 ret = i2c_add_adapter(&lpi2c_imx->adapter); 611 if (ret) 612 goto rpm_disable; 613 614 pm_runtime_mark_last_busy(&pdev->dev); 615 pm_runtime_put_autosuspend(&pdev->dev); 616 617 dev_info(&lpi2c_imx->adapter.dev, "LPI2C adapter registered\n"); 618 619 return 0; 620 621 rpm_disable: 622 pm_runtime_put(&pdev->dev); 623 pm_runtime_disable(&pdev->dev); 624 pm_runtime_dont_use_autosuspend(&pdev->dev); 625 626 return ret; 627 } 628 629 static void lpi2c_imx_remove(struct platform_device *pdev) 630 { 631 struct lpi2c_imx_struct *lpi2c_imx = platform_get_drvdata(pdev); 632 633 i2c_del_adapter(&lpi2c_imx->adapter); 634 635 pm_runtime_disable(&pdev->dev); 636 pm_runtime_dont_use_autosuspend(&pdev->dev); 637 } 638 639 static int __maybe_unused lpi2c_runtime_suspend(struct device *dev) 640 { 641 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 642 643 clk_bulk_disable(lpi2c_imx->num_clks, lpi2c_imx->clks); 644 pinctrl_pm_select_sleep_state(dev); 645 646 return 0; 647 } 648 649 static int __maybe_unused lpi2c_runtime_resume(struct device *dev) 650 { 651 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 652 int ret; 653 654 pinctrl_pm_select_default_state(dev); 655 ret = clk_bulk_enable(lpi2c_imx->num_clks, lpi2c_imx->clks); 656 if (ret) { 657 dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret); 658 return ret; 659 } 660 661 return 0; 662 } 663 664 static const struct dev_pm_ops lpi2c_pm_ops = { 665 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 666 pm_runtime_force_resume) 667 SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend, 668 lpi2c_runtime_resume, NULL) 669 }; 670 671 static struct platform_driver lpi2c_imx_driver = { 672 .probe = lpi2c_imx_probe, 673 .remove_new = lpi2c_imx_remove, 674 .driver = { 675 .name = DRIVER_NAME, 676 .of_match_table = lpi2c_imx_of_match, 677 .pm = &lpi2c_pm_ops, 678 }, 679 }; 680 681 module_platform_driver(lpi2c_imx_driver); 682 683 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>"); 684 MODULE_DESCRIPTION("I2C adapter driver for LPI2C bus"); 685 MODULE_LICENSE("GPL"); 686