1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 58 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 59 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 60 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 61 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 62 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 63 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 64 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 65 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 66 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 67 * 68 * Features supported by this driver: 69 * Software PEC no 70 * Hardware PEC yes 71 * Block buffer yes 72 * Block process call transaction no 73 * I2C block read transaction yes (doesn't use the block buffer) 74 * Slave mode no 75 * SMBus Host Notify yes 76 * Interrupt processing yes 77 * 78 * See the file Documentation/i2c/busses/i2c-i801 for details. 79 */ 80 81 #include <linux/interrupt.h> 82 #include <linux/module.h> 83 #include <linux/pci.h> 84 #include <linux/kernel.h> 85 #include <linux/stddef.h> 86 #include <linux/delay.h> 87 #include <linux/ioport.h> 88 #include <linux/init.h> 89 #include <linux/i2c.h> 90 #include <linux/i2c-smbus.h> 91 #include <linux/acpi.h> 92 #include <linux/io.h> 93 #include <linux/dmi.h> 94 #include <linux/slab.h> 95 #include <linux/wait.h> 96 #include <linux/err.h> 97 #include <linux/platform_device.h> 98 #include <linux/platform_data/itco_wdt.h> 99 #include <linux/pm_runtime.h> 100 101 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 102 #include <linux/gpio.h> 103 #include <linux/platform_data/i2c-mux-gpio.h> 104 #endif 105 106 /* I801 SMBus address offsets */ 107 #define SMBHSTSTS(p) (0 + (p)->smba) 108 #define SMBHSTCNT(p) (2 + (p)->smba) 109 #define SMBHSTCMD(p) (3 + (p)->smba) 110 #define SMBHSTADD(p) (4 + (p)->smba) 111 #define SMBHSTDAT0(p) (5 + (p)->smba) 112 #define SMBHSTDAT1(p) (6 + (p)->smba) 113 #define SMBBLKDAT(p) (7 + (p)->smba) 114 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 115 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 116 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 117 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 118 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 119 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 120 121 /* PCI Address Constants */ 122 #define SMBBAR 4 123 #define SMBPCICTL 0x004 124 #define SMBPCISTS 0x006 125 #define SMBHSTCFG 0x040 126 #define TCOBASE 0x050 127 #define TCOCTL 0x054 128 129 #define ACPIBASE 0x040 130 #define ACPIBASE_SMI_OFF 0x030 131 #define ACPICTRL 0x044 132 #define ACPICTRL_EN 0x080 133 134 #define SBREG_BAR 0x10 135 #define SBREG_SMBCTRL 0xc6000c 136 #define SBREG_SMBCTRL_DNV 0xcf000c 137 138 /* Host status bits for SMBPCISTS */ 139 #define SMBPCISTS_INTS BIT(3) 140 141 /* Control bits for SMBPCICTL */ 142 #define SMBPCICTL_INTDIS BIT(10) 143 144 /* Host configuration bits for SMBHSTCFG */ 145 #define SMBHSTCFG_HST_EN BIT(0) 146 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 147 #define SMBHSTCFG_I2C_EN BIT(2) 148 #define SMBHSTCFG_SPD_WD BIT(4) 149 150 /* TCO configuration bits for TCOCTL */ 151 #define TCOCTL_EN BIT(8) 152 153 /* Auxiliary status register bits, ICH4+ only */ 154 #define SMBAUXSTS_CRCE BIT(0) 155 #define SMBAUXSTS_STCO BIT(1) 156 157 /* Auxiliary control register bits, ICH4+ only */ 158 #define SMBAUXCTL_CRC BIT(0) 159 #define SMBAUXCTL_E32B BIT(1) 160 161 /* Other settings */ 162 #define MAX_RETRIES 400 163 164 /* I801 command constants */ 165 #define I801_QUICK 0x00 166 #define I801_BYTE 0x04 167 #define I801_BYTE_DATA 0x08 168 #define I801_WORD_DATA 0x0C 169 #define I801_PROC_CALL 0x10 /* unimplemented */ 170 #define I801_BLOCK_DATA 0x14 171 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 172 173 /* I801 Host Control register bits */ 174 #define SMBHSTCNT_INTREN BIT(0) 175 #define SMBHSTCNT_KILL BIT(1) 176 #define SMBHSTCNT_LAST_BYTE BIT(5) 177 #define SMBHSTCNT_START BIT(6) 178 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 179 180 /* I801 Hosts Status register bits */ 181 #define SMBHSTSTS_BYTE_DONE BIT(7) 182 #define SMBHSTSTS_INUSE_STS BIT(6) 183 #define SMBHSTSTS_SMBALERT_STS BIT(5) 184 #define SMBHSTSTS_FAILED BIT(4) 185 #define SMBHSTSTS_BUS_ERR BIT(3) 186 #define SMBHSTSTS_DEV_ERR BIT(2) 187 #define SMBHSTSTS_INTR BIT(1) 188 #define SMBHSTSTS_HOST_BUSY BIT(0) 189 190 /* Host Notify Status register bits */ 191 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 192 193 /* Host Notify Command register bits */ 194 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 195 196 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 197 SMBHSTSTS_DEV_ERR) 198 199 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 200 STATUS_ERROR_FLAGS) 201 202 /* Older devices have their ID defined in <linux/pci_ids.h> */ 203 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 204 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 205 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 206 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 207 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 208 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 209 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 210 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 212 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 213 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 214 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 215 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 216 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 217 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 218 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 219 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 220 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 221 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 222 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 223 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 224 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 225 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 226 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 227 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 228 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 229 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 230 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 231 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 232 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 233 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 234 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 235 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 236 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 237 238 struct i801_mux_config { 239 char *gpio_chip; 240 unsigned values[3]; 241 int n_values; 242 unsigned classes[3]; 243 unsigned gpios[2]; /* Relative to gpio_chip->base */ 244 int n_gpios; 245 }; 246 247 struct i801_priv { 248 struct i2c_adapter adapter; 249 unsigned long smba; 250 unsigned char original_hstcfg; 251 unsigned char original_slvcmd; 252 struct pci_dev *pci_dev; 253 unsigned int features; 254 255 /* isr processing */ 256 wait_queue_head_t waitq; 257 u8 status; 258 259 /* Command state used by isr for byte-by-byte block transactions */ 260 u8 cmd; 261 bool is_read; 262 int count; 263 int len; 264 u8 *data; 265 266 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 267 const struct i801_mux_config *mux_drvdata; 268 struct platform_device *mux_pdev; 269 #endif 270 struct platform_device *tco_pdev; 271 272 /* 273 * If set to true the host controller registers are reserved for 274 * ACPI AML use. Protected by acpi_lock. 275 */ 276 bool acpi_reserved; 277 struct mutex acpi_lock; 278 }; 279 280 #define FEATURE_SMBUS_PEC BIT(0) 281 #define FEATURE_BLOCK_BUFFER BIT(1) 282 #define FEATURE_BLOCK_PROC BIT(2) 283 #define FEATURE_I2C_BLOCK_READ BIT(3) 284 #define FEATURE_IRQ BIT(4) 285 #define FEATURE_HOST_NOTIFY BIT(5) 286 /* Not really a feature, but it's convenient to handle it as such */ 287 #define FEATURE_IDF BIT(15) 288 #define FEATURE_TCO BIT(16) 289 290 static const char *i801_feature_names[] = { 291 "SMBus PEC", 292 "Block buffer", 293 "Block process call", 294 "I2C block read", 295 "Interrupt", 296 "SMBus Host Notify", 297 }; 298 299 static unsigned int disable_features; 300 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 301 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 302 "\t\t 0x01 disable SMBus PEC\n" 303 "\t\t 0x02 disable the block buffer\n" 304 "\t\t 0x08 disable the I2C block read functionality\n" 305 "\t\t 0x10 don't use interrupts\n" 306 "\t\t 0x20 disable SMBus Host Notify "); 307 308 /* Make sure the SMBus host is ready to start transmitting. 309 Return 0 if it is, -EBUSY if it is not. */ 310 static int i801_check_pre(struct i801_priv *priv) 311 { 312 int status; 313 314 status = inb_p(SMBHSTSTS(priv)); 315 if (status & SMBHSTSTS_HOST_BUSY) { 316 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 317 return -EBUSY; 318 } 319 320 status &= STATUS_FLAGS; 321 if (status) { 322 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 323 status); 324 outb_p(status, SMBHSTSTS(priv)); 325 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 326 if (status) { 327 dev_err(&priv->pci_dev->dev, 328 "Failed clearing status flags (%02x)\n", 329 status); 330 return -EBUSY; 331 } 332 } 333 334 /* 335 * Clear CRC status if needed. 336 * During normal operation, i801_check_post() takes care 337 * of it after every operation. We do it here only in case 338 * the hardware was already in this state when the driver 339 * started. 340 */ 341 if (priv->features & FEATURE_SMBUS_PEC) { 342 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 343 if (status) { 344 dev_dbg(&priv->pci_dev->dev, 345 "Clearing aux status flags (%02x)\n", status); 346 outb_p(status, SMBAUXSTS(priv)); 347 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 348 if (status) { 349 dev_err(&priv->pci_dev->dev, 350 "Failed clearing aux status flags (%02x)\n", 351 status); 352 return -EBUSY; 353 } 354 } 355 } 356 357 return 0; 358 } 359 360 /* 361 * Convert the status register to an error code, and clear it. 362 * Note that status only contains the bits we want to clear, not the 363 * actual register value. 364 */ 365 static int i801_check_post(struct i801_priv *priv, int status) 366 { 367 int result = 0; 368 369 /* 370 * If the SMBus is still busy, we give up 371 * Note: This timeout condition only happens when using polling 372 * transactions. For interrupt operation, NAK/timeout is indicated by 373 * DEV_ERR. 374 */ 375 if (unlikely(status < 0)) { 376 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 377 /* try to stop the current command */ 378 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 379 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 380 SMBHSTCNT(priv)); 381 usleep_range(1000, 2000); 382 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 383 SMBHSTCNT(priv)); 384 385 /* Check if it worked */ 386 status = inb_p(SMBHSTSTS(priv)); 387 if ((status & SMBHSTSTS_HOST_BUSY) || 388 !(status & SMBHSTSTS_FAILED)) 389 dev_err(&priv->pci_dev->dev, 390 "Failed terminating the transaction\n"); 391 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 392 return -ETIMEDOUT; 393 } 394 395 if (status & SMBHSTSTS_FAILED) { 396 result = -EIO; 397 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 398 } 399 if (status & SMBHSTSTS_DEV_ERR) { 400 /* 401 * This may be a PEC error, check and clear it. 402 * 403 * AUXSTS is handled differently from HSTSTS. 404 * For HSTSTS, i801_isr() or i801_wait_intr() 405 * has already cleared the error bits in hardware, 406 * and we are passed a copy of the original value 407 * in "status". 408 * For AUXSTS, the hardware register is left 409 * for us to handle here. 410 * This is asymmetric, slightly iffy, but safe, 411 * since all this code is serialized and the CRCE 412 * bit is harmless as long as it's cleared before 413 * the next operation. 414 */ 415 if ((priv->features & FEATURE_SMBUS_PEC) && 416 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 417 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 418 result = -EBADMSG; 419 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 420 } else { 421 result = -ENXIO; 422 dev_dbg(&priv->pci_dev->dev, "No response\n"); 423 } 424 } 425 if (status & SMBHSTSTS_BUS_ERR) { 426 result = -EAGAIN; 427 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 428 } 429 430 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 431 outb_p(status, SMBHSTSTS(priv)); 432 433 return result; 434 } 435 436 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 437 static int i801_wait_intr(struct i801_priv *priv) 438 { 439 int timeout = 0; 440 int status; 441 442 /* We will always wait for a fraction of a second! */ 443 do { 444 usleep_range(250, 500); 445 status = inb_p(SMBHSTSTS(priv)); 446 } while (((status & SMBHSTSTS_HOST_BUSY) || 447 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 448 (timeout++ < MAX_RETRIES)); 449 450 if (timeout > MAX_RETRIES) { 451 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 452 return -ETIMEDOUT; 453 } 454 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 455 } 456 457 /* Wait for either BYTE_DONE or an error flag being set */ 458 static int i801_wait_byte_done(struct i801_priv *priv) 459 { 460 int timeout = 0; 461 int status; 462 463 /* We will always wait for a fraction of a second! */ 464 do { 465 usleep_range(250, 500); 466 status = inb_p(SMBHSTSTS(priv)); 467 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 468 (timeout++ < MAX_RETRIES)); 469 470 if (timeout > MAX_RETRIES) { 471 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 472 return -ETIMEDOUT; 473 } 474 return status & STATUS_ERROR_FLAGS; 475 } 476 477 static int i801_transaction(struct i801_priv *priv, int xact) 478 { 479 int status; 480 int result; 481 const struct i2c_adapter *adap = &priv->adapter; 482 483 result = i801_check_pre(priv); 484 if (result < 0) 485 return result; 486 487 if (priv->features & FEATURE_IRQ) { 488 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 489 SMBHSTCNT(priv)); 490 result = wait_event_timeout(priv->waitq, 491 (status = priv->status), 492 adap->timeout); 493 if (!result) { 494 status = -ETIMEDOUT; 495 dev_warn(&priv->pci_dev->dev, 496 "Timeout waiting for interrupt!\n"); 497 } 498 priv->status = 0; 499 return i801_check_post(priv, status); 500 } 501 502 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 503 * SMBSCMD are passed in xact */ 504 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 505 506 status = i801_wait_intr(priv); 507 return i801_check_post(priv, status); 508 } 509 510 static int i801_block_transaction_by_block(struct i801_priv *priv, 511 union i2c_smbus_data *data, 512 char read_write, int hwpec) 513 { 514 int i, len; 515 int status; 516 517 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 518 519 /* Use 32-byte buffer to process this transaction */ 520 if (read_write == I2C_SMBUS_WRITE) { 521 len = data->block[0]; 522 outb_p(len, SMBHSTDAT0(priv)); 523 for (i = 0; i < len; i++) 524 outb_p(data->block[i+1], SMBBLKDAT(priv)); 525 } 526 527 status = i801_transaction(priv, I801_BLOCK_DATA | 528 (hwpec ? SMBHSTCNT_PEC_EN : 0)); 529 if (status) 530 return status; 531 532 if (read_write == I2C_SMBUS_READ) { 533 len = inb_p(SMBHSTDAT0(priv)); 534 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 535 return -EPROTO; 536 537 data->block[0] = len; 538 for (i = 0; i < len; i++) 539 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 540 } 541 return 0; 542 } 543 544 static void i801_isr_byte_done(struct i801_priv *priv) 545 { 546 if (priv->is_read) { 547 /* For SMBus block reads, length is received with first byte */ 548 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 549 (priv->count == 0)) { 550 priv->len = inb_p(SMBHSTDAT0(priv)); 551 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 552 dev_err(&priv->pci_dev->dev, 553 "Illegal SMBus block read size %d\n", 554 priv->len); 555 /* FIXME: Recover */ 556 priv->len = I2C_SMBUS_BLOCK_MAX; 557 } else { 558 dev_dbg(&priv->pci_dev->dev, 559 "SMBus block read size is %d\n", 560 priv->len); 561 } 562 priv->data[-1] = priv->len; 563 } 564 565 /* Read next byte */ 566 if (priv->count < priv->len) 567 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 568 else 569 dev_dbg(&priv->pci_dev->dev, 570 "Discarding extra byte on block read\n"); 571 572 /* Set LAST_BYTE for last byte of read transaction */ 573 if (priv->count == priv->len - 1) 574 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 575 SMBHSTCNT(priv)); 576 } else if (priv->count < priv->len - 1) { 577 /* Write next byte, except for IRQ after last byte */ 578 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 579 } 580 581 /* Clear BYTE_DONE to continue with next byte */ 582 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 583 } 584 585 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 586 { 587 unsigned short addr; 588 589 addr = inb_p(SMBNTFDADD(priv)) >> 1; 590 591 /* 592 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 593 * always returns 0. Our current implementation doesn't provide 594 * data, so we just ignore it. 595 */ 596 i2c_handle_smbus_host_notify(&priv->adapter, addr); 597 598 /* clear Host Notify bit and return */ 599 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 600 return IRQ_HANDLED; 601 } 602 603 /* 604 * There are three kinds of interrupts: 605 * 606 * 1) i801 signals transaction completion with one of these interrupts: 607 * INTR - Success 608 * DEV_ERR - Invalid command, NAK or communication timeout 609 * BUS_ERR - SMI# transaction collision 610 * FAILED - transaction was canceled due to a KILL request 611 * When any of these occur, update ->status and wake up the waitq. 612 * ->status must be cleared before kicking off the next transaction. 613 * 614 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 615 * occurs for each byte of a byte-by-byte to prepare the next byte. 616 * 617 * 3) Host Notify interrupts 618 */ 619 static irqreturn_t i801_isr(int irq, void *dev_id) 620 { 621 struct i801_priv *priv = dev_id; 622 u16 pcists; 623 u8 status; 624 625 /* Confirm this is our interrupt */ 626 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 627 if (!(pcists & SMBPCISTS_INTS)) 628 return IRQ_NONE; 629 630 if (priv->features & FEATURE_HOST_NOTIFY) { 631 status = inb_p(SMBSLVSTS(priv)); 632 if (status & SMBSLVSTS_HST_NTFY_STS) 633 return i801_host_notify_isr(priv); 634 } 635 636 status = inb_p(SMBHSTSTS(priv)); 637 if (status & SMBHSTSTS_BYTE_DONE) 638 i801_isr_byte_done(priv); 639 640 /* 641 * Clear irq sources and report transaction result. 642 * ->status must be cleared before the next transaction is started. 643 */ 644 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 645 if (status) { 646 outb_p(status, SMBHSTSTS(priv)); 647 priv->status = status; 648 wake_up(&priv->waitq); 649 } 650 651 return IRQ_HANDLED; 652 } 653 654 /* 655 * For "byte-by-byte" block transactions: 656 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 657 * I2C read uses cmd=I801_I2C_BLOCK_DATA 658 */ 659 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 660 union i2c_smbus_data *data, 661 char read_write, int command, 662 int hwpec) 663 { 664 int i, len; 665 int smbcmd; 666 int status; 667 int result; 668 const struct i2c_adapter *adap = &priv->adapter; 669 670 result = i801_check_pre(priv); 671 if (result < 0) 672 return result; 673 674 len = data->block[0]; 675 676 if (read_write == I2C_SMBUS_WRITE) { 677 outb_p(len, SMBHSTDAT0(priv)); 678 outb_p(data->block[1], SMBBLKDAT(priv)); 679 } 680 681 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 682 read_write == I2C_SMBUS_READ) 683 smbcmd = I801_I2C_BLOCK_DATA; 684 else 685 smbcmd = I801_BLOCK_DATA; 686 687 if (priv->features & FEATURE_IRQ) { 688 priv->is_read = (read_write == I2C_SMBUS_READ); 689 if (len == 1 && priv->is_read) 690 smbcmd |= SMBHSTCNT_LAST_BYTE; 691 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 692 priv->len = len; 693 priv->count = 0; 694 priv->data = &data->block[1]; 695 696 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 697 result = wait_event_timeout(priv->waitq, 698 (status = priv->status), 699 adap->timeout); 700 if (!result) { 701 status = -ETIMEDOUT; 702 dev_warn(&priv->pci_dev->dev, 703 "Timeout waiting for interrupt!\n"); 704 } 705 priv->status = 0; 706 return i801_check_post(priv, status); 707 } 708 709 for (i = 1; i <= len; i++) { 710 if (i == len && read_write == I2C_SMBUS_READ) 711 smbcmd |= SMBHSTCNT_LAST_BYTE; 712 outb_p(smbcmd, SMBHSTCNT(priv)); 713 714 if (i == 1) 715 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 716 SMBHSTCNT(priv)); 717 718 status = i801_wait_byte_done(priv); 719 if (status) 720 goto exit; 721 722 if (i == 1 && read_write == I2C_SMBUS_READ 723 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 724 len = inb_p(SMBHSTDAT0(priv)); 725 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 726 dev_err(&priv->pci_dev->dev, 727 "Illegal SMBus block read size %d\n", 728 len); 729 /* Recover */ 730 while (inb_p(SMBHSTSTS(priv)) & 731 SMBHSTSTS_HOST_BUSY) 732 outb_p(SMBHSTSTS_BYTE_DONE, 733 SMBHSTSTS(priv)); 734 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 735 return -EPROTO; 736 } 737 data->block[0] = len; 738 } 739 740 /* Retrieve/store value in SMBBLKDAT */ 741 if (read_write == I2C_SMBUS_READ) 742 data->block[i] = inb_p(SMBBLKDAT(priv)); 743 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 744 outb_p(data->block[i+1], SMBBLKDAT(priv)); 745 746 /* signals SMBBLKDAT ready */ 747 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 748 } 749 750 status = i801_wait_intr(priv); 751 exit: 752 return i801_check_post(priv, status); 753 } 754 755 static int i801_set_block_buffer_mode(struct i801_priv *priv) 756 { 757 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 758 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 759 return -EIO; 760 return 0; 761 } 762 763 /* Block transaction function */ 764 static int i801_block_transaction(struct i801_priv *priv, 765 union i2c_smbus_data *data, char read_write, 766 int command, int hwpec) 767 { 768 int result = 0; 769 unsigned char hostc; 770 771 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 772 if (read_write == I2C_SMBUS_WRITE) { 773 /* set I2C_EN bit in configuration register */ 774 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 775 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 776 hostc | SMBHSTCFG_I2C_EN); 777 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 778 dev_err(&priv->pci_dev->dev, 779 "I2C block read is unsupported!\n"); 780 return -EOPNOTSUPP; 781 } 782 } 783 784 if (read_write == I2C_SMBUS_WRITE 785 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 786 if (data->block[0] < 1) 787 data->block[0] = 1; 788 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 789 data->block[0] = I2C_SMBUS_BLOCK_MAX; 790 } else { 791 data->block[0] = 32; /* max for SMBus block reads */ 792 } 793 794 /* Experience has shown that the block buffer can only be used for 795 SMBus (not I2C) block transactions, even though the datasheet 796 doesn't mention this limitation. */ 797 if ((priv->features & FEATURE_BLOCK_BUFFER) 798 && command != I2C_SMBUS_I2C_BLOCK_DATA 799 && i801_set_block_buffer_mode(priv) == 0) 800 result = i801_block_transaction_by_block(priv, data, 801 read_write, hwpec); 802 else 803 result = i801_block_transaction_byte_by_byte(priv, data, 804 read_write, 805 command, hwpec); 806 807 if (command == I2C_SMBUS_I2C_BLOCK_DATA 808 && read_write == I2C_SMBUS_WRITE) { 809 /* restore saved configuration register value */ 810 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 811 } 812 return result; 813 } 814 815 /* Return negative errno on error. */ 816 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 817 unsigned short flags, char read_write, u8 command, 818 int size, union i2c_smbus_data *data) 819 { 820 int hwpec; 821 int block = 0; 822 int ret = 0, xact = 0; 823 struct i801_priv *priv = i2c_get_adapdata(adap); 824 825 mutex_lock(&priv->acpi_lock); 826 if (priv->acpi_reserved) { 827 mutex_unlock(&priv->acpi_lock); 828 return -EBUSY; 829 } 830 831 pm_runtime_get_sync(&priv->pci_dev->dev); 832 833 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 834 && size != I2C_SMBUS_QUICK 835 && size != I2C_SMBUS_I2C_BLOCK_DATA; 836 837 switch (size) { 838 case I2C_SMBUS_QUICK: 839 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 840 SMBHSTADD(priv)); 841 xact = I801_QUICK; 842 break; 843 case I2C_SMBUS_BYTE: 844 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 845 SMBHSTADD(priv)); 846 if (read_write == I2C_SMBUS_WRITE) 847 outb_p(command, SMBHSTCMD(priv)); 848 xact = I801_BYTE; 849 break; 850 case I2C_SMBUS_BYTE_DATA: 851 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 852 SMBHSTADD(priv)); 853 outb_p(command, SMBHSTCMD(priv)); 854 if (read_write == I2C_SMBUS_WRITE) 855 outb_p(data->byte, SMBHSTDAT0(priv)); 856 xact = I801_BYTE_DATA; 857 break; 858 case I2C_SMBUS_WORD_DATA: 859 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 860 SMBHSTADD(priv)); 861 outb_p(command, SMBHSTCMD(priv)); 862 if (read_write == I2C_SMBUS_WRITE) { 863 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 864 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 865 } 866 xact = I801_WORD_DATA; 867 break; 868 case I2C_SMBUS_BLOCK_DATA: 869 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 870 SMBHSTADD(priv)); 871 outb_p(command, SMBHSTCMD(priv)); 872 block = 1; 873 break; 874 case I2C_SMBUS_I2C_BLOCK_DATA: 875 /* 876 * NB: page 240 of ICH5 datasheet shows that the R/#W 877 * bit should be cleared here, even when reading. 878 * However if SPD Write Disable is set (Lynx Point and later), 879 * the read will fail if we don't set the R/#W bit. 880 */ 881 outb_p(((addr & 0x7f) << 1) | 882 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 883 (read_write & 0x01) : 0), 884 SMBHSTADD(priv)); 885 if (read_write == I2C_SMBUS_READ) { 886 /* NB: page 240 of ICH5 datasheet also shows 887 * that DATA1 is the cmd field when reading */ 888 outb_p(command, SMBHSTDAT1(priv)); 889 } else 890 outb_p(command, SMBHSTCMD(priv)); 891 block = 1; 892 break; 893 default: 894 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 895 size); 896 ret = -EOPNOTSUPP; 897 goto out; 898 } 899 900 if (hwpec) /* enable/disable hardware PEC */ 901 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 902 else 903 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 904 SMBAUXCTL(priv)); 905 906 if (block) 907 ret = i801_block_transaction(priv, data, read_write, size, 908 hwpec); 909 else 910 ret = i801_transaction(priv, xact); 911 912 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 913 time, so we forcibly disable it after every transaction. Turn off 914 E32B for the same reason. */ 915 if (hwpec || block) 916 outb_p(inb_p(SMBAUXCTL(priv)) & 917 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 918 919 if (block) 920 goto out; 921 if (ret) 922 goto out; 923 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 924 goto out; 925 926 switch (xact & 0x7f) { 927 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 928 case I801_BYTE_DATA: 929 data->byte = inb_p(SMBHSTDAT0(priv)); 930 break; 931 case I801_WORD_DATA: 932 data->word = inb_p(SMBHSTDAT0(priv)) + 933 (inb_p(SMBHSTDAT1(priv)) << 8); 934 break; 935 } 936 937 out: 938 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 939 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 940 mutex_unlock(&priv->acpi_lock); 941 return ret; 942 } 943 944 945 static u32 i801_func(struct i2c_adapter *adapter) 946 { 947 struct i801_priv *priv = i2c_get_adapdata(adapter); 948 949 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 950 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 951 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 952 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 953 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 954 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 955 ((priv->features & FEATURE_HOST_NOTIFY) ? 956 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 957 } 958 959 static void i801_enable_host_notify(struct i2c_adapter *adapter) 960 { 961 struct i801_priv *priv = i2c_get_adapdata(adapter); 962 963 if (!(priv->features & FEATURE_HOST_NOTIFY)) 964 return; 965 966 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 967 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 968 SMBSLVCMD(priv)); 969 970 /* clear Host Notify bit to allow a new notification */ 971 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 972 } 973 974 static void i801_disable_host_notify(struct i801_priv *priv) 975 { 976 if (!(priv->features & FEATURE_HOST_NOTIFY)) 977 return; 978 979 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 980 } 981 982 static const struct i2c_algorithm smbus_algorithm = { 983 .smbus_xfer = i801_access, 984 .functionality = i801_func, 985 }; 986 987 static const struct pci_device_id i801_ids[] = { 988 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 989 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 990 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 991 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 992 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, 1036 { 0, } 1037 }; 1038 1039 MODULE_DEVICE_TABLE(pci, i801_ids); 1040 1041 #if defined CONFIG_X86 && defined CONFIG_DMI 1042 static unsigned char apanel_addr; 1043 1044 /* Scan the system ROM for the signature "FJKEYINF" */ 1045 static __init const void __iomem *bios_signature(const void __iomem *bios) 1046 { 1047 ssize_t offset; 1048 const unsigned char signature[] = "FJKEYINF"; 1049 1050 for (offset = 0; offset < 0x10000; offset += 0x10) { 1051 if (check_signature(bios + offset, signature, 1052 sizeof(signature)-1)) 1053 return bios + offset; 1054 } 1055 return NULL; 1056 } 1057 1058 static void __init input_apanel_init(void) 1059 { 1060 void __iomem *bios; 1061 const void __iomem *p; 1062 1063 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1064 p = bios_signature(bios); 1065 if (p) { 1066 /* just use the first address */ 1067 apanel_addr = readb(p + 8 + 3) >> 1; 1068 } 1069 iounmap(bios); 1070 } 1071 1072 struct dmi_onboard_device_info { 1073 const char *name; 1074 u8 type; 1075 unsigned short i2c_addr; 1076 const char *i2c_type; 1077 }; 1078 1079 static const struct dmi_onboard_device_info dmi_devices[] = { 1080 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1081 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1082 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1083 }; 1084 1085 static void dmi_check_onboard_device(u8 type, const char *name, 1086 struct i2c_adapter *adap) 1087 { 1088 int i; 1089 struct i2c_board_info info; 1090 1091 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1092 /* & ~0x80, ignore enabled/disabled bit */ 1093 if ((type & ~0x80) != dmi_devices[i].type) 1094 continue; 1095 if (strcasecmp(name, dmi_devices[i].name)) 1096 continue; 1097 1098 memset(&info, 0, sizeof(struct i2c_board_info)); 1099 info.addr = dmi_devices[i].i2c_addr; 1100 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1101 i2c_new_device(adap, &info); 1102 break; 1103 } 1104 } 1105 1106 /* We use our own function to check for onboard devices instead of 1107 dmi_find_device() as some buggy BIOS's have the devices we are interested 1108 in marked as disabled */ 1109 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1110 { 1111 int i, count; 1112 1113 if (dm->type != 10) 1114 return; 1115 1116 count = (dm->length - sizeof(struct dmi_header)) / 2; 1117 for (i = 0; i < count; i++) { 1118 const u8 *d = (char *)(dm + 1) + (i * 2); 1119 const char *name = ((char *) dm) + dm->length; 1120 u8 type = d[0]; 1121 u8 s = d[1]; 1122 1123 if (!s) 1124 continue; 1125 s--; 1126 while (s > 0 && name[0]) { 1127 name += strlen(name) + 1; 1128 s--; 1129 } 1130 if (name[0] == 0) /* Bogus string reference */ 1131 continue; 1132 1133 dmi_check_onboard_device(type, name, adap); 1134 } 1135 } 1136 1137 /* Register optional slaves */ 1138 static void i801_probe_optional_slaves(struct i801_priv *priv) 1139 { 1140 /* Only register slaves on main SMBus channel */ 1141 if (priv->features & FEATURE_IDF) 1142 return; 1143 1144 if (apanel_addr) { 1145 struct i2c_board_info info; 1146 1147 memset(&info, 0, sizeof(struct i2c_board_info)); 1148 info.addr = apanel_addr; 1149 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1150 i2c_new_device(&priv->adapter, &info); 1151 } 1152 1153 if (dmi_name_in_vendors("FUJITSU")) 1154 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1155 } 1156 #else 1157 static void __init input_apanel_init(void) {} 1158 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1159 #endif /* CONFIG_X86 && CONFIG_DMI */ 1160 1161 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1162 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1163 .gpio_chip = "gpio_ich", 1164 .values = { 0x02, 0x03 }, 1165 .n_values = 2, 1166 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1167 .gpios = { 52, 53 }, 1168 .n_gpios = 2, 1169 }; 1170 1171 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1172 .gpio_chip = "gpio_ich", 1173 .values = { 0x02, 0x03, 0x01 }, 1174 .n_values = 3, 1175 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1176 .gpios = { 52, 53 }, 1177 .n_gpios = 2, 1178 }; 1179 1180 static const struct dmi_system_id mux_dmi_table[] = { 1181 { 1182 .matches = { 1183 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1184 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1185 }, 1186 .driver_data = &i801_mux_config_asus_z8_d12, 1187 }, 1188 { 1189 .matches = { 1190 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1191 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1192 }, 1193 .driver_data = &i801_mux_config_asus_z8_d12, 1194 }, 1195 { 1196 .matches = { 1197 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1198 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1199 }, 1200 .driver_data = &i801_mux_config_asus_z8_d12, 1201 }, 1202 { 1203 .matches = { 1204 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1205 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1206 }, 1207 .driver_data = &i801_mux_config_asus_z8_d12, 1208 }, 1209 { 1210 .matches = { 1211 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1212 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1213 }, 1214 .driver_data = &i801_mux_config_asus_z8_d12, 1215 }, 1216 { 1217 .matches = { 1218 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1219 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1220 }, 1221 .driver_data = &i801_mux_config_asus_z8_d12, 1222 }, 1223 { 1224 .matches = { 1225 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1226 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1227 }, 1228 .driver_data = &i801_mux_config_asus_z8_d18, 1229 }, 1230 { 1231 .matches = { 1232 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1233 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1234 }, 1235 .driver_data = &i801_mux_config_asus_z8_d18, 1236 }, 1237 { 1238 .matches = { 1239 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1240 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1241 }, 1242 .driver_data = &i801_mux_config_asus_z8_d12, 1243 }, 1244 { } 1245 }; 1246 1247 /* Setup multiplexing if needed */ 1248 static int i801_add_mux(struct i801_priv *priv) 1249 { 1250 struct device *dev = &priv->adapter.dev; 1251 const struct i801_mux_config *mux_config; 1252 struct i2c_mux_gpio_platform_data gpio_data; 1253 int err; 1254 1255 if (!priv->mux_drvdata) 1256 return 0; 1257 mux_config = priv->mux_drvdata; 1258 1259 /* Prepare the platform data */ 1260 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1261 gpio_data.parent = priv->adapter.nr; 1262 gpio_data.values = mux_config->values; 1263 gpio_data.n_values = mux_config->n_values; 1264 gpio_data.classes = mux_config->classes; 1265 gpio_data.gpio_chip = mux_config->gpio_chip; 1266 gpio_data.gpios = mux_config->gpios; 1267 gpio_data.n_gpios = mux_config->n_gpios; 1268 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1269 1270 /* Register the mux device */ 1271 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1272 PLATFORM_DEVID_AUTO, &gpio_data, 1273 sizeof(struct i2c_mux_gpio_platform_data)); 1274 if (IS_ERR(priv->mux_pdev)) { 1275 err = PTR_ERR(priv->mux_pdev); 1276 priv->mux_pdev = NULL; 1277 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1278 return err; 1279 } 1280 1281 return 0; 1282 } 1283 1284 static void i801_del_mux(struct i801_priv *priv) 1285 { 1286 if (priv->mux_pdev) 1287 platform_device_unregister(priv->mux_pdev); 1288 } 1289 1290 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1291 { 1292 const struct dmi_system_id *id; 1293 const struct i801_mux_config *mux_config; 1294 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1295 int i; 1296 1297 id = dmi_first_match(mux_dmi_table); 1298 if (id) { 1299 /* Remove branch classes from trunk */ 1300 mux_config = id->driver_data; 1301 for (i = 0; i < mux_config->n_values; i++) 1302 class &= ~mux_config->classes[i]; 1303 1304 /* Remember for later */ 1305 priv->mux_drvdata = mux_config; 1306 } 1307 1308 return class; 1309 } 1310 #else 1311 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1312 static inline void i801_del_mux(struct i801_priv *priv) { } 1313 1314 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1315 { 1316 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1317 } 1318 #endif 1319 1320 static const struct itco_wdt_platform_data tco_platform_data = { 1321 .name = "Intel PCH", 1322 .version = 4, 1323 }; 1324 1325 static DEFINE_SPINLOCK(p2sb_spinlock); 1326 1327 static void i801_add_tco(struct i801_priv *priv) 1328 { 1329 struct pci_dev *pci_dev = priv->pci_dev; 1330 struct resource tco_res[3], *res; 1331 struct platform_device *pdev; 1332 unsigned int devfn; 1333 u32 tco_base, tco_ctl; 1334 u32 base_addr, ctrl_val; 1335 u64 base64_addr; 1336 u8 hidden; 1337 1338 if (!(priv->features & FEATURE_TCO)) 1339 return; 1340 1341 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1342 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1343 if (!(tco_ctl & TCOCTL_EN)) 1344 return; 1345 1346 memset(tco_res, 0, sizeof(tco_res)); 1347 1348 res = &tco_res[ICH_RES_IO_TCO]; 1349 res->start = tco_base & ~1; 1350 res->end = res->start + 32 - 1; 1351 res->flags = IORESOURCE_IO; 1352 1353 /* 1354 * Power Management registers. 1355 */ 1356 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); 1357 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); 1358 1359 res = &tco_res[ICH_RES_IO_SMI]; 1360 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; 1361 res->end = res->start + 3; 1362 res->flags = IORESOURCE_IO; 1363 1364 /* 1365 * Enable the ACPI I/O space. 1366 */ 1367 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); 1368 ctrl_val |= ACPICTRL_EN; 1369 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); 1370 1371 /* 1372 * We must access the NO_REBOOT bit over the Primary to Sideband 1373 * bridge (P2SB). The BIOS prevents the P2SB device from being 1374 * enumerated by the PCI subsystem, so we need to unhide/hide it 1375 * to lookup the P2SB BAR. 1376 */ 1377 spin_lock(&p2sb_spinlock); 1378 1379 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1380 1381 /* Unhide the P2SB device, if it is hidden */ 1382 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1383 if (hidden) 1384 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1385 1386 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1387 base64_addr = base_addr & 0xfffffff0; 1388 1389 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1390 base64_addr |= (u64)base_addr << 32; 1391 1392 /* Hide the P2SB device, if it was hidden before */ 1393 if (hidden) 1394 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1395 spin_unlock(&p2sb_spinlock); 1396 1397 res = &tco_res[ICH_RES_MEM_OFF]; 1398 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1399 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1400 else 1401 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1402 1403 res->end = res->start + 3; 1404 res->flags = IORESOURCE_MEM; 1405 1406 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1407 tco_res, 3, &tco_platform_data, 1408 sizeof(tco_platform_data)); 1409 if (IS_ERR(pdev)) { 1410 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1411 return; 1412 } 1413 1414 priv->tco_pdev = pdev; 1415 } 1416 1417 #ifdef CONFIG_ACPI 1418 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1419 acpi_physical_address address) 1420 { 1421 return address >= priv->smba && 1422 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1423 } 1424 1425 static acpi_status 1426 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1427 u64 *value, void *handler_context, void *region_context) 1428 { 1429 struct i801_priv *priv = handler_context; 1430 struct pci_dev *pdev = priv->pci_dev; 1431 acpi_status status; 1432 1433 /* 1434 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1435 * further access from the driver itself. This device is now owned 1436 * by the system firmware. 1437 */ 1438 mutex_lock(&priv->acpi_lock); 1439 1440 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1441 priv->acpi_reserved = true; 1442 1443 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1444 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1445 1446 /* 1447 * BIOS is accessing the host controller so prevent it from 1448 * suspending automatically from now on. 1449 */ 1450 pm_runtime_get_sync(&pdev->dev); 1451 } 1452 1453 if ((function & ACPI_IO_MASK) == ACPI_READ) 1454 status = acpi_os_read_port(address, (u32 *)value, bits); 1455 else 1456 status = acpi_os_write_port(address, (u32)*value, bits); 1457 1458 mutex_unlock(&priv->acpi_lock); 1459 1460 return status; 1461 } 1462 1463 static int i801_acpi_probe(struct i801_priv *priv) 1464 { 1465 struct acpi_device *adev; 1466 acpi_status status; 1467 1468 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1469 if (adev) { 1470 status = acpi_install_address_space_handler(adev->handle, 1471 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1472 NULL, priv); 1473 if (ACPI_SUCCESS(status)) 1474 return 0; 1475 } 1476 1477 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1478 } 1479 1480 static void i801_acpi_remove(struct i801_priv *priv) 1481 { 1482 struct acpi_device *adev; 1483 1484 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1485 if (!adev) 1486 return; 1487 1488 acpi_remove_address_space_handler(adev->handle, 1489 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1490 1491 mutex_lock(&priv->acpi_lock); 1492 if (priv->acpi_reserved) 1493 pm_runtime_put(&priv->pci_dev->dev); 1494 mutex_unlock(&priv->acpi_lock); 1495 } 1496 #else 1497 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1498 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1499 #endif 1500 1501 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1502 { 1503 unsigned char temp; 1504 int err, i; 1505 struct i801_priv *priv; 1506 1507 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1508 if (!priv) 1509 return -ENOMEM; 1510 1511 i2c_set_adapdata(&priv->adapter, priv); 1512 priv->adapter.owner = THIS_MODULE; 1513 priv->adapter.class = i801_get_adapter_class(priv); 1514 priv->adapter.algo = &smbus_algorithm; 1515 priv->adapter.dev.parent = &dev->dev; 1516 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1517 priv->adapter.retries = 3; 1518 mutex_init(&priv->acpi_lock); 1519 1520 priv->pci_dev = dev; 1521 switch (dev->device) { 1522 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1523 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1524 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1525 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1526 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1527 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1528 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1529 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1530 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1531 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1532 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: 1533 priv->features |= FEATURE_I2C_BLOCK_READ; 1534 priv->features |= FEATURE_IRQ; 1535 priv->features |= FEATURE_SMBUS_PEC; 1536 priv->features |= FEATURE_BLOCK_BUFFER; 1537 /* If we have ACPI based watchdog use that instead */ 1538 if (!acpi_has_watchdog()) 1539 priv->features |= FEATURE_TCO; 1540 priv->features |= FEATURE_HOST_NOTIFY; 1541 break; 1542 1543 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1544 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1545 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1546 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1547 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1548 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1549 priv->features |= FEATURE_IDF; 1550 /* fall through */ 1551 default: 1552 priv->features |= FEATURE_I2C_BLOCK_READ; 1553 priv->features |= FEATURE_IRQ; 1554 /* fall through */ 1555 case PCI_DEVICE_ID_INTEL_82801DB_3: 1556 priv->features |= FEATURE_SMBUS_PEC; 1557 priv->features |= FEATURE_BLOCK_BUFFER; 1558 /* fall through */ 1559 case PCI_DEVICE_ID_INTEL_82801CA_3: 1560 priv->features |= FEATURE_HOST_NOTIFY; 1561 /* fall through */ 1562 case PCI_DEVICE_ID_INTEL_82801BA_2: 1563 case PCI_DEVICE_ID_INTEL_82801AB_3: 1564 case PCI_DEVICE_ID_INTEL_82801AA_3: 1565 break; 1566 } 1567 1568 /* Disable features on user request */ 1569 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1570 if (priv->features & disable_features & (1 << i)) 1571 dev_notice(&dev->dev, "%s disabled by user\n", 1572 i801_feature_names[i]); 1573 } 1574 priv->features &= ~disable_features; 1575 1576 err = pcim_enable_device(dev); 1577 if (err) { 1578 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1579 err); 1580 return err; 1581 } 1582 pcim_pin_device(dev); 1583 1584 /* Determine the address of the SMBus area */ 1585 priv->smba = pci_resource_start(dev, SMBBAR); 1586 if (!priv->smba) { 1587 dev_err(&dev->dev, 1588 "SMBus base address uninitialized, upgrade BIOS\n"); 1589 return -ENODEV; 1590 } 1591 1592 if (i801_acpi_probe(priv)) 1593 return -ENODEV; 1594 1595 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1596 dev_driver_string(&dev->dev)); 1597 if (err) { 1598 dev_err(&dev->dev, 1599 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1600 priv->smba, 1601 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1602 i801_acpi_remove(priv); 1603 return err; 1604 } 1605 1606 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1607 priv->original_hstcfg = temp; 1608 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1609 if (!(temp & SMBHSTCFG_HST_EN)) { 1610 dev_info(&dev->dev, "Enabling SMBus device\n"); 1611 temp |= SMBHSTCFG_HST_EN; 1612 } 1613 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1614 1615 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1616 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1617 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1618 priv->features &= ~FEATURE_IRQ; 1619 } 1620 if (temp & SMBHSTCFG_SPD_WD) 1621 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1622 1623 /* Clear special mode bits */ 1624 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1625 outb_p(inb_p(SMBAUXCTL(priv)) & 1626 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1627 1628 /* Remember original Host Notify setting */ 1629 if (priv->features & FEATURE_HOST_NOTIFY) 1630 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1631 1632 /* Default timeout in interrupt mode: 200 ms */ 1633 priv->adapter.timeout = HZ / 5; 1634 1635 if (dev->irq == IRQ_NOTCONNECTED) 1636 priv->features &= ~FEATURE_IRQ; 1637 1638 if (priv->features & FEATURE_IRQ) { 1639 u16 pcictl, pcists; 1640 1641 /* Complain if an interrupt is already pending */ 1642 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1643 if (pcists & SMBPCISTS_INTS) 1644 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1645 1646 /* Check if interrupts have been disabled */ 1647 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1648 if (pcictl & SMBPCICTL_INTDIS) { 1649 dev_info(&dev->dev, "Interrupts are disabled\n"); 1650 priv->features &= ~FEATURE_IRQ; 1651 } 1652 } 1653 1654 if (priv->features & FEATURE_IRQ) { 1655 init_waitqueue_head(&priv->waitq); 1656 1657 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1658 IRQF_SHARED, 1659 dev_driver_string(&dev->dev), priv); 1660 if (err) { 1661 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1662 dev->irq, err); 1663 priv->features &= ~FEATURE_IRQ; 1664 } 1665 } 1666 dev_info(&dev->dev, "SMBus using %s\n", 1667 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1668 1669 i801_add_tco(priv); 1670 1671 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1672 "SMBus I801 adapter at %04lx", priv->smba); 1673 err = i2c_add_adapter(&priv->adapter); 1674 if (err) { 1675 i801_acpi_remove(priv); 1676 return err; 1677 } 1678 1679 i801_enable_host_notify(&priv->adapter); 1680 1681 i801_probe_optional_slaves(priv); 1682 /* We ignore errors - multiplexing is optional */ 1683 i801_add_mux(priv); 1684 1685 pci_set_drvdata(dev, priv); 1686 1687 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1688 pm_runtime_use_autosuspend(&dev->dev); 1689 pm_runtime_put_autosuspend(&dev->dev); 1690 pm_runtime_allow(&dev->dev); 1691 1692 return 0; 1693 } 1694 1695 static void i801_remove(struct pci_dev *dev) 1696 { 1697 struct i801_priv *priv = pci_get_drvdata(dev); 1698 1699 pm_runtime_forbid(&dev->dev); 1700 pm_runtime_get_noresume(&dev->dev); 1701 1702 i801_disable_host_notify(priv); 1703 i801_del_mux(priv); 1704 i2c_del_adapter(&priv->adapter); 1705 i801_acpi_remove(priv); 1706 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1707 1708 platform_device_unregister(priv->tco_pdev); 1709 1710 /* 1711 * do not call pci_disable_device(dev) since it can cause hard hangs on 1712 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1713 */ 1714 } 1715 1716 static void i801_shutdown(struct pci_dev *dev) 1717 { 1718 struct i801_priv *priv = pci_get_drvdata(dev); 1719 1720 /* Restore config registers to avoid hard hang on some systems */ 1721 i801_disable_host_notify(priv); 1722 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1723 } 1724 1725 #ifdef CONFIG_PM_SLEEP 1726 static int i801_suspend(struct device *dev) 1727 { 1728 struct pci_dev *pci_dev = to_pci_dev(dev); 1729 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1730 1731 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); 1732 return 0; 1733 } 1734 1735 static int i801_resume(struct device *dev) 1736 { 1737 struct pci_dev *pci_dev = to_pci_dev(dev); 1738 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1739 1740 i801_enable_host_notify(&priv->adapter); 1741 1742 return 0; 1743 } 1744 #endif 1745 1746 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1747 1748 static struct pci_driver i801_driver = { 1749 .name = "i801_smbus", 1750 .id_table = i801_ids, 1751 .probe = i801_probe, 1752 .remove = i801_remove, 1753 .shutdown = i801_shutdown, 1754 .driver = { 1755 .pm = &i801_pm_ops, 1756 }, 1757 }; 1758 1759 static int __init i2c_i801_init(void) 1760 { 1761 if (dmi_name_in_vendors("FUJITSU")) 1762 input_apanel_init(); 1763 return pci_register_driver(&i801_driver); 1764 } 1765 1766 static void __exit i2c_i801_exit(void) 1767 { 1768 pci_unregister_driver(&i801_driver); 1769 } 1770 1771 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1772 MODULE_DESCRIPTION("I801 SMBus driver"); 1773 MODULE_LICENSE("GPL"); 1774 1775 module_init(i2c_i801_init); 1776 module_exit(i2c_i801_exit); 1777