1 /* 2 i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware 3 monitoring 4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 6 <mdsxyz123@yahoo.com> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 /* 24 SUPPORTED DEVICES PCI ID 25 82801AA 2413 26 82801AB 2423 27 82801BA 2443 28 82801CA/CAM 2483 29 82801DB 24C3 (HW PEC supported, 32 byte buffer not supported) 30 82801EB 24D3 (HW PEC supported, 32 byte buffer not supported) 31 6300ESB 25A4 32 ICH6 266A 33 ICH7 27DA 34 ESB2 269B 35 ICH8 283E 36 ICH9 2930 37 This driver supports several versions of Intel's I/O Controller Hubs (ICH). 38 For SMBus support, they are similar to the PIIX4 and are part 39 of Intel's '810' and other chipsets. 40 See the file Documentation/i2c/busses/i2c-i801 for details. 41 I2C Block Read and Process Call are not supported. 42 */ 43 44 /* Note: we assume there can only be one I801, with one SMBus interface */ 45 46 #include <linux/module.h> 47 #include <linux/pci.h> 48 #include <linux/kernel.h> 49 #include <linux/stddef.h> 50 #include <linux/delay.h> 51 #include <linux/ioport.h> 52 #include <linux/init.h> 53 #include <linux/i2c.h> 54 #include <asm/io.h> 55 56 /* I801 SMBus address offsets */ 57 #define SMBHSTSTS (0 + i801_smba) 58 #define SMBHSTCNT (2 + i801_smba) 59 #define SMBHSTCMD (3 + i801_smba) 60 #define SMBHSTADD (4 + i801_smba) 61 #define SMBHSTDAT0 (5 + i801_smba) 62 #define SMBHSTDAT1 (6 + i801_smba) 63 #define SMBBLKDAT (7 + i801_smba) 64 #define SMBPEC (8 + i801_smba) /* ICH4 only */ 65 #define SMBAUXSTS (12 + i801_smba) /* ICH4 only */ 66 #define SMBAUXCTL (13 + i801_smba) /* ICH4 only */ 67 68 /* PCI Address Constants */ 69 #define SMBBAR 4 70 #define SMBHSTCFG 0x040 71 72 /* Host configuration bits for SMBHSTCFG */ 73 #define SMBHSTCFG_HST_EN 1 74 #define SMBHSTCFG_SMB_SMI_EN 2 75 #define SMBHSTCFG_I2C_EN 4 76 77 /* Other settings */ 78 #define MAX_TIMEOUT 100 79 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */ 80 81 /* I801 command constants */ 82 #define I801_QUICK 0x00 83 #define I801_BYTE 0x04 84 #define I801_BYTE_DATA 0x08 85 #define I801_WORD_DATA 0x0C 86 #define I801_PROC_CALL 0x10 /* later chips only, unimplemented */ 87 #define I801_BLOCK_DATA 0x14 88 #define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */ 89 #define I801_BLOCK_LAST 0x34 90 #define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */ 91 #define I801_START 0x40 92 #define I801_PEC_EN 0x80 /* ICH4 only */ 93 94 95 static int i801_transaction(void); 96 static int i801_block_transaction(union i2c_smbus_data *data, char read_write, 97 int command, int hwpec); 98 99 static unsigned long i801_smba; 100 static unsigned char i801_original_hstcfg; 101 static struct pci_driver i801_driver; 102 static struct pci_dev *I801_dev; 103 static int isich4; 104 105 static int i801_transaction(void) 106 { 107 int temp; 108 int result = 0; 109 int timeout = 0; 110 111 dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " 112 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 113 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 114 inb_p(SMBHSTDAT1)); 115 116 /* Make sure the SMBus host is ready to start transmitting */ 117 /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */ 118 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) { 119 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n", 120 temp); 121 outb_p(temp, SMBHSTSTS); 122 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) { 123 dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp); 124 return -1; 125 } else { 126 dev_dbg(&I801_dev->dev, "Successful!\n"); 127 } 128 } 129 130 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT); 131 132 /* We will always wait for a fraction of a second! */ 133 do { 134 msleep(1); 135 temp = inb_p(SMBHSTSTS); 136 } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT)); 137 138 /* If the SMBus is still busy, we give up */ 139 if (timeout >= MAX_TIMEOUT) { 140 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n"); 141 result = -1; 142 } 143 144 if (temp & 0x10) { 145 result = -1; 146 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n"); 147 } 148 149 if (temp & 0x08) { 150 result = -1; 151 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked " 152 "until next hard reset. (sorry!)\n"); 153 /* Clock stops and slave is stuck in mid-transmission */ 154 } 155 156 if (temp & 0x04) { 157 result = -1; 158 dev_dbg(&I801_dev->dev, "Error: no response!\n"); 159 } 160 161 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00) 162 outb_p(inb(SMBHSTSTS), SMBHSTSTS); 163 164 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) { 165 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction " 166 "(%02x)\n", temp); 167 } 168 dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, " 169 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 170 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 171 inb_p(SMBHSTDAT1)); 172 return result; 173 } 174 175 /* All-inclusive block transaction function */ 176 static int i801_block_transaction(union i2c_smbus_data *data, char read_write, 177 int command, int hwpec) 178 { 179 int i, len; 180 int smbcmd; 181 int temp; 182 int result = 0; 183 int timeout; 184 unsigned char hostc, errmask; 185 186 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 187 if (read_write == I2C_SMBUS_WRITE) { 188 /* set I2C_EN bit in configuration register */ 189 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc); 190 pci_write_config_byte(I801_dev, SMBHSTCFG, 191 hostc | SMBHSTCFG_I2C_EN); 192 } else { 193 dev_err(&I801_dev->dev, 194 "I2C_SMBUS_I2C_BLOCK_READ not DB!\n"); 195 return -1; 196 } 197 } 198 199 if (read_write == I2C_SMBUS_WRITE) { 200 len = data->block[0]; 201 if (len < 1) 202 len = 1; 203 if (len > 32) 204 len = 32; 205 outb_p(len, SMBHSTDAT0); 206 outb_p(data->block[1], SMBBLKDAT); 207 } else { 208 len = 32; /* max for reads */ 209 } 210 211 if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 212 /* set 32 byte buffer */ 213 } 214 215 for (i = 1; i <= len; i++) { 216 if (i == len && read_write == I2C_SMBUS_READ) 217 smbcmd = I801_BLOCK_LAST; 218 else 219 smbcmd = I801_BLOCK_DATA; 220 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT); 221 222 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, " 223 "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i, 224 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD), 225 inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT)); 226 227 /* Make sure the SMBus host is ready to start transmitting */ 228 temp = inb_p(SMBHSTSTS); 229 if (i == 1) { 230 /* Erronenous conditions before transaction: 231 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */ 232 errmask=0x9f; 233 } else { 234 /* Erronenous conditions during transaction: 235 * Failed, Bus_Err, Dev_Err, Intr */ 236 errmask=0x1e; 237 } 238 if (temp & errmask) { 239 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). " 240 "Resetting...\n", temp); 241 outb_p(temp, SMBHSTSTS); 242 if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) { 243 dev_err(&I801_dev->dev, 244 "Reset failed! (%02x)\n", temp); 245 result = -1; 246 goto END; 247 } 248 if (i != 1) { 249 /* if die in middle of block transaction, fail */ 250 result = -1; 251 goto END; 252 } 253 } 254 255 if (i == 1) 256 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT); 257 258 /* We will always wait for a fraction of a second! */ 259 timeout = 0; 260 do { 261 msleep(1); 262 temp = inb_p(SMBHSTSTS); 263 } 264 while ((!(temp & 0x80)) 265 && (timeout++ < MAX_TIMEOUT)); 266 267 /* If the SMBus is still busy, we give up */ 268 if (timeout >= MAX_TIMEOUT) { 269 result = -1; 270 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n"); 271 } 272 273 if (temp & 0x10) { 274 result = -1; 275 dev_dbg(&I801_dev->dev, 276 "Error: Failed bus transaction\n"); 277 } else if (temp & 0x08) { 278 result = -1; 279 dev_err(&I801_dev->dev, "Bus collision!\n"); 280 } else if (temp & 0x04) { 281 result = -1; 282 dev_dbg(&I801_dev->dev, "Error: no response!\n"); 283 } 284 285 if (i == 1 && read_write == I2C_SMBUS_READ) { 286 len = inb_p(SMBHSTDAT0); 287 if (len < 1) 288 len = 1; 289 if (len > 32) 290 len = 32; 291 data->block[0] = len; 292 } 293 294 /* Retrieve/store value in SMBBLKDAT */ 295 if (read_write == I2C_SMBUS_READ) 296 data->block[i] = inb_p(SMBBLKDAT); 297 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 298 outb_p(data->block[i+1], SMBBLKDAT); 299 if ((temp & 0x9e) != 0x00) 300 outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */ 301 302 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) { 303 dev_dbg(&I801_dev->dev, 304 "Bad status (%02x) at end of transaction\n", 305 temp); 306 } 307 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, " 308 "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i, 309 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD), 310 inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT)); 311 312 if (result < 0) 313 goto END; 314 } 315 316 if (hwpec) { 317 /* wait for INTR bit as advised by Intel */ 318 timeout = 0; 319 do { 320 msleep(1); 321 temp = inb_p(SMBHSTSTS); 322 } while ((!(temp & 0x02)) 323 && (timeout++ < MAX_TIMEOUT)); 324 325 if (timeout >= MAX_TIMEOUT) { 326 dev_dbg(&I801_dev->dev, "PEC Timeout!\n"); 327 } 328 outb_p(temp, SMBHSTSTS); 329 } 330 result = 0; 331 END: 332 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 333 /* restore saved configuration register value */ 334 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc); 335 } 336 return result; 337 } 338 339 /* Return -1 on error. */ 340 static s32 i801_access(struct i2c_adapter * adap, u16 addr, 341 unsigned short flags, char read_write, u8 command, 342 int size, union i2c_smbus_data * data) 343 { 344 int hwpec; 345 int block = 0; 346 int ret, xact = 0; 347 348 hwpec = isich4 && (flags & I2C_CLIENT_PEC) 349 && size != I2C_SMBUS_QUICK 350 && size != I2C_SMBUS_I2C_BLOCK_DATA; 351 352 switch (size) { 353 case I2C_SMBUS_QUICK: 354 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 355 SMBHSTADD); 356 xact = I801_QUICK; 357 break; 358 case I2C_SMBUS_BYTE: 359 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 360 SMBHSTADD); 361 if (read_write == I2C_SMBUS_WRITE) 362 outb_p(command, SMBHSTCMD); 363 xact = I801_BYTE; 364 break; 365 case I2C_SMBUS_BYTE_DATA: 366 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 367 SMBHSTADD); 368 outb_p(command, SMBHSTCMD); 369 if (read_write == I2C_SMBUS_WRITE) 370 outb_p(data->byte, SMBHSTDAT0); 371 xact = I801_BYTE_DATA; 372 break; 373 case I2C_SMBUS_WORD_DATA: 374 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 375 SMBHSTADD); 376 outb_p(command, SMBHSTCMD); 377 if (read_write == I2C_SMBUS_WRITE) { 378 outb_p(data->word & 0xff, SMBHSTDAT0); 379 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); 380 } 381 xact = I801_WORD_DATA; 382 break; 383 case I2C_SMBUS_BLOCK_DATA: 384 case I2C_SMBUS_I2C_BLOCK_DATA: 385 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 386 SMBHSTADD); 387 outb_p(command, SMBHSTCMD); 388 block = 1; 389 break; 390 case I2C_SMBUS_PROC_CALL: 391 default: 392 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size); 393 return -1; 394 } 395 396 outb_p(hwpec, SMBAUXCTL); /* enable/disable hardware PEC */ 397 398 if(block) 399 ret = i801_block_transaction(data, read_write, size, hwpec); 400 else { 401 outb_p(xact | ENABLE_INT9, SMBHSTCNT); 402 ret = i801_transaction(); 403 } 404 405 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 406 time, so we forcibly disable it after every transaction. */ 407 if (hwpec) 408 outb_p(0, SMBAUXCTL); 409 410 if(block) 411 return ret; 412 if(ret) 413 return -1; 414 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 415 return 0; 416 417 switch (xact & 0x7f) { 418 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 419 case I801_BYTE_DATA: 420 data->byte = inb_p(SMBHSTDAT0); 421 break; 422 case I801_WORD_DATA: 423 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); 424 break; 425 } 426 return 0; 427 } 428 429 430 static u32 i801_func(struct i2c_adapter *adapter) 431 { 432 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 433 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 434 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 435 | (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0); 436 } 437 438 static const struct i2c_algorithm smbus_algorithm = { 439 .smbus_xfer = i801_access, 440 .functionality = i801_func, 441 }; 442 443 static struct i2c_adapter i801_adapter = { 444 .owner = THIS_MODULE, 445 .id = I2C_HW_SMBUS_I801, 446 .class = I2C_CLASS_HWMON, 447 .algo = &smbus_algorithm, 448 }; 449 450 static struct pci_device_id i801_ids[] = { 451 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 452 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 453 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 454 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 455 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 456 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 458 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 459 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 460 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 461 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 462 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 463 { 0, } 464 }; 465 466 MODULE_DEVICE_TABLE (pci, i801_ids); 467 468 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 469 { 470 unsigned char temp; 471 int err; 472 473 I801_dev = dev; 474 switch (dev->device) { 475 case PCI_DEVICE_ID_INTEL_82801DB_3: 476 case PCI_DEVICE_ID_INTEL_82801EB_3: 477 case PCI_DEVICE_ID_INTEL_ESB_4: 478 case PCI_DEVICE_ID_INTEL_ICH6_16: 479 case PCI_DEVICE_ID_INTEL_ICH7_17: 480 case PCI_DEVICE_ID_INTEL_ESB2_17: 481 case PCI_DEVICE_ID_INTEL_ICH8_5: 482 case PCI_DEVICE_ID_INTEL_ICH9_6: 483 isich4 = 1; 484 break; 485 default: 486 isich4 = 0; 487 } 488 489 err = pci_enable_device(dev); 490 if (err) { 491 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 492 err); 493 goto exit; 494 } 495 496 /* Determine the address of the SMBus area */ 497 i801_smba = pci_resource_start(dev, SMBBAR); 498 if (!i801_smba) { 499 dev_err(&dev->dev, "SMBus base address uninitialized, " 500 "upgrade BIOS\n"); 501 err = -ENODEV; 502 goto exit; 503 } 504 505 err = pci_request_region(dev, SMBBAR, i801_driver.name); 506 if (err) { 507 dev_err(&dev->dev, "Failed to request SMBus region " 508 "0x%lx-0x%Lx\n", i801_smba, 509 (unsigned long long)pci_resource_end(dev, SMBBAR)); 510 goto exit; 511 } 512 513 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp); 514 i801_original_hstcfg = temp; 515 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 516 if (!(temp & SMBHSTCFG_HST_EN)) { 517 dev_info(&dev->dev, "Enabling SMBus device\n"); 518 temp |= SMBHSTCFG_HST_EN; 519 } 520 pci_write_config_byte(I801_dev, SMBHSTCFG, temp); 521 522 if (temp & SMBHSTCFG_SMB_SMI_EN) 523 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 524 else 525 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); 526 527 /* set up the sysfs linkage to our parent device */ 528 i801_adapter.dev.parent = &dev->dev; 529 530 snprintf(i801_adapter.name, I2C_NAME_SIZE, 531 "SMBus I801 adapter at %04lx", i801_smba); 532 err = i2c_add_adapter(&i801_adapter); 533 if (err) { 534 dev_err(&dev->dev, "Failed to add SMBus adapter\n"); 535 goto exit_release; 536 } 537 return 0; 538 539 exit_release: 540 pci_release_region(dev, SMBBAR); 541 exit: 542 return err; 543 } 544 545 static void __devexit i801_remove(struct pci_dev *dev) 546 { 547 i2c_del_adapter(&i801_adapter); 548 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg); 549 pci_release_region(dev, SMBBAR); 550 /* 551 * do not call pci_disable_device(dev) since it can cause hard hangs on 552 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 553 */ 554 } 555 556 #ifdef CONFIG_PM 557 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) 558 { 559 pci_save_state(dev); 560 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg); 561 pci_set_power_state(dev, pci_choose_state(dev, mesg)); 562 return 0; 563 } 564 565 static int i801_resume(struct pci_dev *dev) 566 { 567 pci_set_power_state(dev, PCI_D0); 568 pci_restore_state(dev); 569 return pci_enable_device(dev); 570 } 571 #else 572 #define i801_suspend NULL 573 #define i801_resume NULL 574 #endif 575 576 static struct pci_driver i801_driver = { 577 .name = "i801_smbus", 578 .id_table = i801_ids, 579 .probe = i801_probe, 580 .remove = __devexit_p(i801_remove), 581 .suspend = i801_suspend, 582 .resume = i801_resume, 583 }; 584 585 static int __init i2c_i801_init(void) 586 { 587 return pci_register_driver(&i801_driver); 588 } 589 590 static void __exit i2c_i801_exit(void) 591 { 592 pci_unregister_driver(&i801_driver); 593 } 594 595 MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, " 596 "Philip Edelbrock <phil@netroedge.com>, " 597 "and Mark D. Studebaker <mdsxyz123@yahoo.com>"); 598 MODULE_DESCRIPTION("I801 SMBus driver"); 599 MODULE_LICENSE("GPL"); 600 601 module_init(i2c_i801_init); 602 module_exit(i2c_i801_exit); 603