1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes 68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 78 * 79 * Features supported by this driver: 80 * Software PEC no 81 * Hardware PEC yes 82 * Block buffer yes 83 * Block process call transaction yes 84 * I2C block read transaction yes (doesn't use the block buffer) 85 * Slave mode no 86 * SMBus Host Notify yes 87 * Interrupt processing yes 88 * 89 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 90 */ 91 92 #define DRV_NAME "i801_smbus" 93 94 #include <linux/interrupt.h> 95 #include <linux/module.h> 96 #include <linux/pci.h> 97 #include <linux/kernel.h> 98 #include <linux/stddef.h> 99 #include <linux/delay.h> 100 #include <linux/ioport.h> 101 #include <linux/init.h> 102 #include <linux/i2c.h> 103 #include <linux/i2c-smbus.h> 104 #include <linux/acpi.h> 105 #include <linux/io.h> 106 #include <linux/dmi.h> 107 #include <linux/slab.h> 108 #include <linux/string.h> 109 #include <linux/completion.h> 110 #include <linux/err.h> 111 #include <linux/platform_device.h> 112 #include <linux/platform_data/itco_wdt.h> 113 #include <linux/pm_runtime.h> 114 #include <linux/mutex.h> 115 116 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 117 #include <linux/gpio/machine.h> 118 #include <linux/platform_data/i2c-mux-gpio.h> 119 #endif 120 121 /* I801 SMBus address offsets */ 122 #define SMBHSTSTS(p) (0 + (p)->smba) 123 #define SMBHSTCNT(p) (2 + (p)->smba) 124 #define SMBHSTCMD(p) (3 + (p)->smba) 125 #define SMBHSTADD(p) (4 + (p)->smba) 126 #define SMBHSTDAT0(p) (5 + (p)->smba) 127 #define SMBHSTDAT1(p) (6 + (p)->smba) 128 #define SMBBLKDAT(p) (7 + (p)->smba) 129 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 130 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 131 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 132 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 133 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 134 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 135 136 /* PCI Address Constants */ 137 #define SMBBAR 4 138 #define SMBHSTCFG 0x040 139 #define TCOBASE 0x050 140 #define TCOCTL 0x054 141 142 #define SBREG_BAR 0x10 143 #define SBREG_SMBCTRL 0xc6000c 144 #define SBREG_SMBCTRL_DNV 0xcf000c 145 146 /* Host configuration bits for SMBHSTCFG */ 147 #define SMBHSTCFG_HST_EN BIT(0) 148 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 149 #define SMBHSTCFG_I2C_EN BIT(2) 150 #define SMBHSTCFG_SPD_WD BIT(4) 151 152 /* TCO configuration bits for TCOCTL */ 153 #define TCOCTL_EN BIT(8) 154 155 /* Auxiliary status register bits, ICH4+ only */ 156 #define SMBAUXSTS_CRCE BIT(0) 157 #define SMBAUXSTS_STCO BIT(1) 158 159 /* Auxiliary control register bits, ICH4+ only */ 160 #define SMBAUXCTL_CRC BIT(0) 161 #define SMBAUXCTL_E32B BIT(1) 162 163 /* I801 command constants */ 164 #define I801_QUICK 0x00 165 #define I801_BYTE 0x04 166 #define I801_BYTE_DATA 0x08 167 #define I801_WORD_DATA 0x0C 168 #define I801_PROC_CALL 0x10 /* unimplemented */ 169 #define I801_BLOCK_DATA 0x14 170 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 171 #define I801_BLOCK_PROC_CALL 0x1C 172 173 /* I801 Host Control register bits */ 174 #define SMBHSTCNT_INTREN BIT(0) 175 #define SMBHSTCNT_KILL BIT(1) 176 #define SMBHSTCNT_LAST_BYTE BIT(5) 177 #define SMBHSTCNT_START BIT(6) 178 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 179 180 /* I801 Hosts Status register bits */ 181 #define SMBHSTSTS_BYTE_DONE BIT(7) 182 #define SMBHSTSTS_INUSE_STS BIT(6) 183 #define SMBHSTSTS_SMBALERT_STS BIT(5) 184 #define SMBHSTSTS_FAILED BIT(4) 185 #define SMBHSTSTS_BUS_ERR BIT(3) 186 #define SMBHSTSTS_DEV_ERR BIT(2) 187 #define SMBHSTSTS_INTR BIT(1) 188 #define SMBHSTSTS_HOST_BUSY BIT(0) 189 190 /* Host Notify Status register bits */ 191 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 192 193 /* Host Notify Command register bits */ 194 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2) 195 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 196 197 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 198 SMBHSTSTS_DEV_ERR) 199 200 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 201 STATUS_ERROR_FLAGS) 202 203 /* Older devices have their ID defined in <linux/pci_ids.h> */ 204 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 205 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 206 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 207 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 208 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 209 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 210 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 212 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 216 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 217 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 218 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 219 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 220 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 221 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 222 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 223 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3 224 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 225 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 226 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 227 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 228 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 229 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 230 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 231 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 232 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 233 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 235 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 237 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 238 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 239 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 240 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 241 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 242 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 243 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 244 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 245 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 246 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 247 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 248 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 249 250 struct i801_mux_config { 251 char *gpio_chip; 252 unsigned values[3]; 253 int n_values; 254 unsigned classes[3]; 255 unsigned gpios[2]; /* Relative to gpio_chip->base */ 256 int n_gpios; 257 }; 258 259 struct i801_priv { 260 struct i2c_adapter adapter; 261 unsigned long smba; 262 unsigned char original_hstcfg; 263 unsigned char original_hstcnt; 264 unsigned char original_slvcmd; 265 struct pci_dev *pci_dev; 266 unsigned int features; 267 268 /* isr processing */ 269 struct completion done; 270 u8 status; 271 272 /* Command state used by isr for byte-by-byte block transactions */ 273 u8 cmd; 274 bool is_read; 275 int count; 276 int len; 277 u8 *data; 278 279 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 280 const struct i801_mux_config *mux_drvdata; 281 struct platform_device *mux_pdev; 282 struct gpiod_lookup_table *lookup; 283 #endif 284 struct platform_device *tco_pdev; 285 286 /* 287 * If set to true the host controller registers are reserved for 288 * ACPI AML use. Protected by acpi_lock. 289 */ 290 bool acpi_reserved; 291 struct mutex acpi_lock; 292 }; 293 294 #define FEATURE_SMBUS_PEC BIT(0) 295 #define FEATURE_BLOCK_BUFFER BIT(1) 296 #define FEATURE_BLOCK_PROC BIT(2) 297 #define FEATURE_I2C_BLOCK_READ BIT(3) 298 #define FEATURE_IRQ BIT(4) 299 #define FEATURE_HOST_NOTIFY BIT(5) 300 /* Not really a feature, but it's convenient to handle it as such */ 301 #define FEATURE_IDF BIT(15) 302 #define FEATURE_TCO_SPT BIT(16) 303 #define FEATURE_TCO_CNL BIT(17) 304 305 static const char *i801_feature_names[] = { 306 "SMBus PEC", 307 "Block buffer", 308 "Block process call", 309 "I2C block read", 310 "Interrupt", 311 "SMBus Host Notify", 312 }; 313 314 static unsigned int disable_features; 315 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 316 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 317 "\t\t 0x01 disable SMBus PEC\n" 318 "\t\t 0x02 disable the block buffer\n" 319 "\t\t 0x08 disable the I2C block read functionality\n" 320 "\t\t 0x10 don't use interrupts\n" 321 "\t\t 0x20 disable SMBus Host Notify "); 322 323 /* Make sure the SMBus host is ready to start transmitting. 324 Return 0 if it is, -EBUSY if it is not. */ 325 static int i801_check_pre(struct i801_priv *priv) 326 { 327 int status; 328 329 status = inb_p(SMBHSTSTS(priv)); 330 if (status & SMBHSTSTS_HOST_BUSY) { 331 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n"); 332 return -EBUSY; 333 } 334 335 status &= STATUS_FLAGS; 336 if (status) { 337 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status); 338 outb_p(status, SMBHSTSTS(priv)); 339 } 340 341 /* 342 * Clear CRC status if needed. 343 * During normal operation, i801_check_post() takes care 344 * of it after every operation. We do it here only in case 345 * the hardware was already in this state when the driver 346 * started. 347 */ 348 if (priv->features & FEATURE_SMBUS_PEC) { 349 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 350 if (status) { 351 pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status); 352 outb_p(status, SMBAUXSTS(priv)); 353 } 354 } 355 356 return 0; 357 } 358 359 static int i801_check_post(struct i801_priv *priv, int status) 360 { 361 int result = 0; 362 363 /* 364 * If the SMBus is still busy, we give up 365 * Note: This timeout condition only happens when using polling 366 * transactions. For interrupt operation, NAK/timeout is indicated by 367 * DEV_ERR. 368 */ 369 if (unlikely(status < 0)) { 370 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 371 /* try to stop the current command */ 372 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 373 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 374 usleep_range(1000, 2000); 375 outb_p(0, SMBHSTCNT(priv)); 376 377 /* Check if it worked */ 378 status = inb_p(SMBHSTSTS(priv)); 379 if ((status & SMBHSTSTS_HOST_BUSY) || 380 !(status & SMBHSTSTS_FAILED)) 381 dev_err(&priv->pci_dev->dev, 382 "Failed terminating the transaction\n"); 383 return -ETIMEDOUT; 384 } 385 386 if (status & SMBHSTSTS_FAILED) { 387 result = -EIO; 388 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 389 } 390 if (status & SMBHSTSTS_DEV_ERR) { 391 /* 392 * This may be a PEC error, check and clear it. 393 * 394 * AUXSTS is handled differently from HSTSTS. 395 * For HSTSTS, i801_isr() or i801_wait_intr() 396 * has already cleared the error bits in hardware, 397 * and we are passed a copy of the original value 398 * in "status". 399 * For AUXSTS, the hardware register is left 400 * for us to handle here. 401 * This is asymmetric, slightly iffy, but safe, 402 * since all this code is serialized and the CRCE 403 * bit is harmless as long as it's cleared before 404 * the next operation. 405 */ 406 if ((priv->features & FEATURE_SMBUS_PEC) && 407 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 408 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 409 result = -EBADMSG; 410 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 411 } else { 412 result = -ENXIO; 413 dev_dbg(&priv->pci_dev->dev, "No response\n"); 414 } 415 } 416 if (status & SMBHSTSTS_BUS_ERR) { 417 result = -EAGAIN; 418 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 419 } 420 421 return result; 422 } 423 424 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 425 static int i801_wait_intr(struct i801_priv *priv) 426 { 427 unsigned long timeout = jiffies + priv->adapter.timeout; 428 int status, busy; 429 430 do { 431 usleep_range(250, 500); 432 status = inb_p(SMBHSTSTS(priv)); 433 busy = status & SMBHSTSTS_HOST_BUSY; 434 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 435 if (!busy && status) 436 return status; 437 } while (time_is_after_eq_jiffies(timeout)); 438 439 return -ETIMEDOUT; 440 } 441 442 /* Wait for either BYTE_DONE or an error flag being set */ 443 static int i801_wait_byte_done(struct i801_priv *priv) 444 { 445 unsigned long timeout = jiffies + priv->adapter.timeout; 446 int status; 447 448 do { 449 usleep_range(250, 500); 450 status = inb_p(SMBHSTSTS(priv)); 451 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 452 return status & STATUS_ERROR_FLAGS; 453 } while (time_is_after_eq_jiffies(timeout)); 454 455 return -ETIMEDOUT; 456 } 457 458 static int i801_transaction(struct i801_priv *priv, int xact) 459 { 460 int status; 461 unsigned long result; 462 const struct i2c_adapter *adap = &priv->adapter; 463 464 status = i801_check_pre(priv); 465 if (status < 0) 466 return status; 467 468 if (priv->features & FEATURE_IRQ) { 469 reinit_completion(&priv->done); 470 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 471 SMBHSTCNT(priv)); 472 result = wait_for_completion_timeout(&priv->done, adap->timeout); 473 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT); 474 } 475 476 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 477 * SMBSCMD are passed in xact */ 478 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 479 480 status = i801_wait_intr(priv); 481 return i801_check_post(priv, status); 482 } 483 484 static int i801_block_transaction_by_block(struct i801_priv *priv, 485 union i2c_smbus_data *data, 486 char read_write, int command) 487 { 488 int i, len, status, xact; 489 490 switch (command) { 491 case I2C_SMBUS_BLOCK_PROC_CALL: 492 xact = I801_BLOCK_PROC_CALL; 493 break; 494 case I2C_SMBUS_BLOCK_DATA: 495 xact = I801_BLOCK_DATA; 496 break; 497 default: 498 return -EOPNOTSUPP; 499 } 500 501 /* Set block buffer mode */ 502 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 503 504 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 505 506 if (read_write == I2C_SMBUS_WRITE) { 507 len = data->block[0]; 508 outb_p(len, SMBHSTDAT0(priv)); 509 for (i = 0; i < len; i++) 510 outb_p(data->block[i+1], SMBBLKDAT(priv)); 511 } 512 513 status = i801_transaction(priv, xact); 514 if (status) 515 return status; 516 517 if (read_write == I2C_SMBUS_READ || 518 command == I2C_SMBUS_BLOCK_PROC_CALL) { 519 len = inb_p(SMBHSTDAT0(priv)); 520 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 521 return -EPROTO; 522 523 data->block[0] = len; 524 for (i = 0; i < len; i++) 525 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 526 } 527 return 0; 528 } 529 530 static void i801_isr_byte_done(struct i801_priv *priv) 531 { 532 if (priv->is_read) { 533 /* For SMBus block reads, length is received with first byte */ 534 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 535 (priv->count == 0)) { 536 priv->len = inb_p(SMBHSTDAT0(priv)); 537 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 538 dev_err(&priv->pci_dev->dev, 539 "Illegal SMBus block read size %d\n", 540 priv->len); 541 /* FIXME: Recover */ 542 priv->len = I2C_SMBUS_BLOCK_MAX; 543 } 544 priv->data[-1] = priv->len; 545 } 546 547 /* Read next byte */ 548 if (priv->count < priv->len) 549 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 550 else 551 dev_dbg(&priv->pci_dev->dev, 552 "Discarding extra byte on block read\n"); 553 554 /* Set LAST_BYTE for last byte of read transaction */ 555 if (priv->count == priv->len - 1) 556 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 557 SMBHSTCNT(priv)); 558 } else if (priv->count < priv->len - 1) { 559 /* Write next byte, except for IRQ after last byte */ 560 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 561 } 562 563 /* Clear BYTE_DONE to continue with next byte */ 564 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 565 } 566 567 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 568 { 569 unsigned short addr; 570 571 addr = inb_p(SMBNTFDADD(priv)) >> 1; 572 573 /* 574 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 575 * always returns 0. Our current implementation doesn't provide 576 * data, so we just ignore it. 577 */ 578 i2c_handle_smbus_host_notify(&priv->adapter, addr); 579 580 /* clear Host Notify bit and return */ 581 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 582 return IRQ_HANDLED; 583 } 584 585 /* 586 * There are three kinds of interrupts: 587 * 588 * 1) i801 signals transaction completion with one of these interrupts: 589 * INTR - Success 590 * DEV_ERR - Invalid command, NAK or communication timeout 591 * BUS_ERR - SMI# transaction collision 592 * FAILED - transaction was canceled due to a KILL request 593 * When any of these occur, update ->status and signal completion. 594 * ->status must be cleared before kicking off the next transaction. 595 * 596 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 597 * occurs for each byte of a byte-by-byte to prepare the next byte. 598 * 599 * 3) Host Notify interrupts 600 */ 601 static irqreturn_t i801_isr(int irq, void *dev_id) 602 { 603 struct i801_priv *priv = dev_id; 604 u16 pcists; 605 u8 status; 606 607 /* Confirm this is our interrupt */ 608 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 609 if (!(pcists & PCI_STATUS_INTERRUPT)) 610 return IRQ_NONE; 611 612 if (priv->features & FEATURE_HOST_NOTIFY) { 613 status = inb_p(SMBSLVSTS(priv)); 614 if (status & SMBSLVSTS_HST_NTFY_STS) 615 return i801_host_notify_isr(priv); 616 } 617 618 status = inb_p(SMBHSTSTS(priv)); 619 if (status & SMBHSTSTS_BYTE_DONE) 620 i801_isr_byte_done(priv); 621 622 /* 623 * Clear remaining IRQ sources: Completion of last command, errors 624 * and the SMB_ALERT signal. SMB_ALERT status is set after signal 625 * assertion independently of the interrupt generation being blocked 626 * or not so clear it always when the status is set. 627 */ 628 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS | SMBHSTSTS_SMBALERT_STS; 629 if (status) 630 outb_p(status, SMBHSTSTS(priv)); 631 status &= ~SMBHSTSTS_SMBALERT_STS; /* SMB_ALERT not reported */ 632 /* 633 * Report transaction result. 634 * ->status must be cleared before the next transaction is started. 635 */ 636 if (status) { 637 priv->status = status; 638 complete(&priv->done); 639 } 640 641 return IRQ_HANDLED; 642 } 643 644 /* 645 * For "byte-by-byte" block transactions: 646 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 647 * I2C read uses cmd=I801_I2C_BLOCK_DATA 648 */ 649 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 650 union i2c_smbus_data *data, 651 char read_write, int command) 652 { 653 int i, len; 654 int smbcmd; 655 int status; 656 unsigned long result; 657 const struct i2c_adapter *adap = &priv->adapter; 658 659 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 660 return -EOPNOTSUPP; 661 662 status = i801_check_pre(priv); 663 if (status < 0) 664 return status; 665 666 len = data->block[0]; 667 668 if (read_write == I2C_SMBUS_WRITE) { 669 outb_p(len, SMBHSTDAT0(priv)); 670 outb_p(data->block[1], SMBBLKDAT(priv)); 671 } 672 673 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 674 read_write == I2C_SMBUS_READ) 675 smbcmd = I801_I2C_BLOCK_DATA; 676 else 677 smbcmd = I801_BLOCK_DATA; 678 679 if (priv->features & FEATURE_IRQ) { 680 priv->is_read = (read_write == I2C_SMBUS_READ); 681 if (len == 1 && priv->is_read) 682 smbcmd |= SMBHSTCNT_LAST_BYTE; 683 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 684 priv->len = len; 685 priv->count = 0; 686 priv->data = &data->block[1]; 687 688 reinit_completion(&priv->done); 689 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 690 result = wait_for_completion_timeout(&priv->done, adap->timeout); 691 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT); 692 } 693 694 for (i = 1; i <= len; i++) { 695 if (i == len && read_write == I2C_SMBUS_READ) 696 smbcmd |= SMBHSTCNT_LAST_BYTE; 697 outb_p(smbcmd, SMBHSTCNT(priv)); 698 699 if (i == 1) 700 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 701 SMBHSTCNT(priv)); 702 703 status = i801_wait_byte_done(priv); 704 if (status) 705 goto exit; 706 707 if (i == 1 && read_write == I2C_SMBUS_READ 708 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 709 len = inb_p(SMBHSTDAT0(priv)); 710 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 711 dev_err(&priv->pci_dev->dev, 712 "Illegal SMBus block read size %d\n", 713 len); 714 /* Recover */ 715 while (inb_p(SMBHSTSTS(priv)) & 716 SMBHSTSTS_HOST_BUSY) 717 outb_p(SMBHSTSTS_BYTE_DONE, 718 SMBHSTSTS(priv)); 719 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 720 return -EPROTO; 721 } 722 data->block[0] = len; 723 } 724 725 /* Retrieve/store value in SMBBLKDAT */ 726 if (read_write == I2C_SMBUS_READ) 727 data->block[i] = inb_p(SMBBLKDAT(priv)); 728 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 729 outb_p(data->block[i+1], SMBBLKDAT(priv)); 730 731 /* signals SMBBLKDAT ready */ 732 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 733 } 734 735 status = i801_wait_intr(priv); 736 exit: 737 return i801_check_post(priv, status); 738 } 739 740 /* Block transaction function */ 741 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 742 char read_write, int command) 743 { 744 int result = 0; 745 unsigned char hostc; 746 747 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA) 748 data->block[0] = I2C_SMBUS_BLOCK_MAX; 749 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 750 return -EPROTO; 751 752 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 753 if (read_write == I2C_SMBUS_WRITE) { 754 /* set I2C_EN bit in configuration register */ 755 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 756 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 757 hostc | SMBHSTCFG_I2C_EN); 758 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 759 dev_err(&priv->pci_dev->dev, 760 "I2C block read is unsupported!\n"); 761 return -EOPNOTSUPP; 762 } 763 } 764 765 /* Experience has shown that the block buffer can only be used for 766 SMBus (not I2C) block transactions, even though the datasheet 767 doesn't mention this limitation. */ 768 if ((priv->features & FEATURE_BLOCK_BUFFER) && 769 command != I2C_SMBUS_I2C_BLOCK_DATA) 770 result = i801_block_transaction_by_block(priv, data, 771 read_write, 772 command); 773 else 774 result = i801_block_transaction_byte_by_byte(priv, data, 775 read_write, 776 command); 777 778 if (command == I2C_SMBUS_I2C_BLOCK_DATA 779 && read_write == I2C_SMBUS_WRITE) { 780 /* restore saved configuration register value */ 781 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 782 } 783 return result; 784 } 785 786 /* Return negative errno on error. */ 787 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 788 unsigned short flags, char read_write, u8 command, 789 int size, union i2c_smbus_data *data) 790 { 791 int hwpec; 792 int block = 0; 793 int ret = 0, xact = 0; 794 struct i801_priv *priv = i2c_get_adapdata(adap); 795 796 mutex_lock(&priv->acpi_lock); 797 if (priv->acpi_reserved) { 798 mutex_unlock(&priv->acpi_lock); 799 return -EBUSY; 800 } 801 802 pm_runtime_get_sync(&priv->pci_dev->dev); 803 804 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 805 && size != I2C_SMBUS_QUICK 806 && size != I2C_SMBUS_I2C_BLOCK_DATA; 807 808 switch (size) { 809 case I2C_SMBUS_QUICK: 810 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 811 SMBHSTADD(priv)); 812 xact = I801_QUICK; 813 break; 814 case I2C_SMBUS_BYTE: 815 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 816 SMBHSTADD(priv)); 817 if (read_write == I2C_SMBUS_WRITE) 818 outb_p(command, SMBHSTCMD(priv)); 819 xact = I801_BYTE; 820 break; 821 case I2C_SMBUS_BYTE_DATA: 822 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 823 SMBHSTADD(priv)); 824 outb_p(command, SMBHSTCMD(priv)); 825 if (read_write == I2C_SMBUS_WRITE) 826 outb_p(data->byte, SMBHSTDAT0(priv)); 827 xact = I801_BYTE_DATA; 828 break; 829 case I2C_SMBUS_WORD_DATA: 830 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 831 SMBHSTADD(priv)); 832 outb_p(command, SMBHSTCMD(priv)); 833 if (read_write == I2C_SMBUS_WRITE) { 834 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 835 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 836 } 837 xact = I801_WORD_DATA; 838 break; 839 case I2C_SMBUS_BLOCK_DATA: 840 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 841 SMBHSTADD(priv)); 842 outb_p(command, SMBHSTCMD(priv)); 843 block = 1; 844 break; 845 case I2C_SMBUS_I2C_BLOCK_DATA: 846 /* 847 * NB: page 240 of ICH5 datasheet shows that the R/#W 848 * bit should be cleared here, even when reading. 849 * However if SPD Write Disable is set (Lynx Point and later), 850 * the read will fail if we don't set the R/#W bit. 851 */ 852 outb_p(((addr & 0x7f) << 1) | 853 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 854 (read_write & 0x01) : 0), 855 SMBHSTADD(priv)); 856 if (read_write == I2C_SMBUS_READ) { 857 /* NB: page 240 of ICH5 datasheet also shows 858 * that DATA1 is the cmd field when reading */ 859 outb_p(command, SMBHSTDAT1(priv)); 860 } else 861 outb_p(command, SMBHSTCMD(priv)); 862 block = 1; 863 break; 864 case I2C_SMBUS_BLOCK_PROC_CALL: 865 /* 866 * Bit 0 of the slave address register always indicate a write 867 * command. 868 */ 869 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 870 outb_p(command, SMBHSTCMD(priv)); 871 block = 1; 872 break; 873 default: 874 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 875 size); 876 ret = -EOPNOTSUPP; 877 goto out; 878 } 879 880 if (hwpec) /* enable/disable hardware PEC */ 881 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 882 else 883 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 884 SMBAUXCTL(priv)); 885 886 if (block) 887 ret = i801_block_transaction(priv, data, read_write, size); 888 else 889 ret = i801_transaction(priv, xact); 890 891 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 892 time, so we forcibly disable it after every transaction. Turn off 893 E32B for the same reason. */ 894 if (hwpec || block) 895 outb_p(inb_p(SMBAUXCTL(priv)) & 896 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 897 898 if (block) 899 goto out; 900 if (ret) 901 goto out; 902 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 903 goto out; 904 905 switch (xact & 0x7f) { 906 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 907 case I801_BYTE_DATA: 908 data->byte = inb_p(SMBHSTDAT0(priv)); 909 break; 910 case I801_WORD_DATA: 911 data->word = inb_p(SMBHSTDAT0(priv)) + 912 (inb_p(SMBHSTDAT1(priv)) << 8); 913 break; 914 } 915 916 out: 917 /* 918 * Unlock the SMBus device for use by BIOS/ACPI, 919 * and clear status flags if not done already. 920 */ 921 outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv)); 922 923 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 924 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 925 mutex_unlock(&priv->acpi_lock); 926 return ret; 927 } 928 929 930 static u32 i801_func(struct i2c_adapter *adapter) 931 { 932 struct i801_priv *priv = i2c_get_adapdata(adapter); 933 934 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 935 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 936 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 937 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 938 ((priv->features & FEATURE_BLOCK_PROC) ? 939 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 940 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 941 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 942 ((priv->features & FEATURE_HOST_NOTIFY) ? 943 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 944 } 945 946 static void i801_enable_host_notify(struct i2c_adapter *adapter) 947 { 948 struct i801_priv *priv = i2c_get_adapdata(adapter); 949 950 if (!(priv->features & FEATURE_HOST_NOTIFY)) 951 return; 952 953 /* 954 * Enable host notify interrupt and block the generation of interrupt 955 * from the SMB_ALERT signal because the driver does not support 956 * SMBus Alert. 957 */ 958 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE | 959 priv->original_slvcmd, SMBSLVCMD(priv)); 960 961 /* clear Host Notify bit to allow a new notification */ 962 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 963 } 964 965 static void i801_disable_host_notify(struct i801_priv *priv) 966 { 967 if (!(priv->features & FEATURE_HOST_NOTIFY)) 968 return; 969 970 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 971 } 972 973 static const struct i2c_algorithm smbus_algorithm = { 974 .smbus_xfer = i801_access, 975 .functionality = i801_func, 976 }; 977 978 #define FEATURES_ICH5 (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ | \ 979 FEATURE_IRQ | FEATURE_SMBUS_PEC | \ 980 FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY) 981 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \ 982 FEATURE_HOST_NOTIFY) 983 984 static const struct pci_device_id i801_ids[] = { 985 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) }, 986 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) }, 987 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) }, 988 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) }, 989 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) }, 990 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) }, 991 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) }, 992 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) }, 993 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) }, 994 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) }, 995 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) }, 996 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) }, 997 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) }, 998 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) }, 999 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) }, 1000 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) }, 1001 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) }, 1002 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) }, 1003 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) }, 1004 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) }, 1005 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) }, 1006 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) }, 1007 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) }, 1008 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) }, 1009 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) }, 1010 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) }, 1011 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) }, 1012 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) }, 1013 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) }, 1014 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) }, 1015 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) }, 1016 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) }, 1017 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) }, 1018 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) }, 1019 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) }, 1020 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) }, 1021 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1022 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1023 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1024 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1025 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1026 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) }, 1027 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1028 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1029 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1030 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1031 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1032 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1033 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1034 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1035 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1036 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1037 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1038 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1039 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1040 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1041 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1042 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1043 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1044 { 0, } 1045 }; 1046 1047 MODULE_DEVICE_TABLE(pci, i801_ids); 1048 1049 #if defined CONFIG_X86 && defined CONFIG_DMI 1050 static unsigned char apanel_addr; 1051 1052 /* Scan the system ROM for the signature "FJKEYINF" */ 1053 static __init const void __iomem *bios_signature(const void __iomem *bios) 1054 { 1055 ssize_t offset; 1056 const unsigned char signature[] = "FJKEYINF"; 1057 1058 for (offset = 0; offset < 0x10000; offset += 0x10) { 1059 if (check_signature(bios + offset, signature, 1060 sizeof(signature)-1)) 1061 return bios + offset; 1062 } 1063 return NULL; 1064 } 1065 1066 static void __init input_apanel_init(void) 1067 { 1068 void __iomem *bios; 1069 const void __iomem *p; 1070 1071 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1072 p = bios_signature(bios); 1073 if (p) { 1074 /* just use the first address */ 1075 apanel_addr = readb(p + 8 + 3) >> 1; 1076 } 1077 iounmap(bios); 1078 } 1079 1080 struct dmi_onboard_device_info { 1081 const char *name; 1082 u8 type; 1083 unsigned short i2c_addr; 1084 const char *i2c_type; 1085 }; 1086 1087 static const struct dmi_onboard_device_info dmi_devices[] = { 1088 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1089 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1090 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1091 }; 1092 1093 static void dmi_check_onboard_device(u8 type, const char *name, 1094 struct i2c_adapter *adap) 1095 { 1096 int i; 1097 struct i2c_board_info info; 1098 1099 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1100 /* & ~0x80, ignore enabled/disabled bit */ 1101 if ((type & ~0x80) != dmi_devices[i].type) 1102 continue; 1103 if (strcasecmp(name, dmi_devices[i].name)) 1104 continue; 1105 1106 memset(&info, 0, sizeof(struct i2c_board_info)); 1107 info.addr = dmi_devices[i].i2c_addr; 1108 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1109 i2c_new_client_device(adap, &info); 1110 break; 1111 } 1112 } 1113 1114 /* We use our own function to check for onboard devices instead of 1115 dmi_find_device() as some buggy BIOS's have the devices we are interested 1116 in marked as disabled */ 1117 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1118 { 1119 int i, count; 1120 1121 if (dm->type != 10) 1122 return; 1123 1124 count = (dm->length - sizeof(struct dmi_header)) / 2; 1125 for (i = 0; i < count; i++) { 1126 const u8 *d = (char *)(dm + 1) + (i * 2); 1127 const char *name = ((char *) dm) + dm->length; 1128 u8 type = d[0]; 1129 u8 s = d[1]; 1130 1131 if (!s) 1132 continue; 1133 s--; 1134 while (s > 0 && name[0]) { 1135 name += strlen(name) + 1; 1136 s--; 1137 } 1138 if (name[0] == 0) /* Bogus string reference */ 1139 continue; 1140 1141 dmi_check_onboard_device(type, name, adap); 1142 } 1143 } 1144 1145 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1146 static const char *const acpi_smo8800_ids[] = { 1147 "SMO8800", 1148 "SMO8801", 1149 "SMO8810", 1150 "SMO8811", 1151 "SMO8820", 1152 "SMO8821", 1153 "SMO8830", 1154 "SMO8831", 1155 }; 1156 1157 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1158 u32 nesting_level, 1159 void *context, 1160 void **return_value) 1161 { 1162 struct acpi_device_info *info; 1163 acpi_status status; 1164 char *hid; 1165 int i; 1166 1167 status = acpi_get_object_info(obj_handle, &info); 1168 if (ACPI_FAILURE(status)) 1169 return AE_OK; 1170 1171 if (!(info->valid & ACPI_VALID_HID)) 1172 goto smo88xx_not_found; 1173 1174 hid = info->hardware_id.string; 1175 if (!hid) 1176 goto smo88xx_not_found; 1177 1178 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1179 if (i < 0) 1180 goto smo88xx_not_found; 1181 1182 kfree(info); 1183 1184 *return_value = NULL; 1185 return AE_CTRL_TERMINATE; 1186 1187 smo88xx_not_found: 1188 kfree(info); 1189 return AE_OK; 1190 } 1191 1192 static bool is_dell_system_with_lis3lv02d(void) 1193 { 1194 void *err = ERR_PTR(-ENOENT); 1195 1196 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc.")) 1197 return false; 1198 1199 /* 1200 * Check that ACPI device SMO88xx is present and is functioning. 1201 * Function acpi_get_devices() already filters all ACPI devices 1202 * which are not present or are not functioning. 1203 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1204 * accelerometer but unfortunately ACPI does not provide any other 1205 * information (like I2C address). 1206 */ 1207 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err); 1208 1209 return !IS_ERR(err); 1210 } 1211 1212 /* 1213 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1214 * so it is needed to define mapping table based on DMI product names. 1215 */ 1216 static const struct { 1217 const char *dmi_product_name; 1218 unsigned short i2c_addr; 1219 } dell_lis3lv02d_devices[] = { 1220 /* 1221 * Dell platform team told us that these Latitude devices have 1222 * ST microelectronics accelerometer at I2C address 0x29. 1223 */ 1224 { "Latitude E5250", 0x29 }, 1225 { "Latitude E5450", 0x29 }, 1226 { "Latitude E5550", 0x29 }, 1227 { "Latitude E6440", 0x29 }, 1228 { "Latitude E6440 ATG", 0x29 }, 1229 { "Latitude E6540", 0x29 }, 1230 /* 1231 * Additional individual entries were added after verification. 1232 */ 1233 { "Latitude 5480", 0x29 }, 1234 { "Vostro V131", 0x1d }, 1235 }; 1236 1237 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1238 { 1239 struct i2c_board_info info; 1240 const char *dmi_product_name; 1241 int i; 1242 1243 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1244 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1245 if (strcmp(dmi_product_name, 1246 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1247 break; 1248 } 1249 1250 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1251 dev_warn(&priv->pci_dev->dev, 1252 "Accelerometer lis3lv02d is present on SMBus but its" 1253 " address is unknown, skipping registration\n"); 1254 return; 1255 } 1256 1257 memset(&info, 0, sizeof(struct i2c_board_info)); 1258 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1259 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1260 i2c_new_client_device(&priv->adapter, &info); 1261 } 1262 1263 /* Register optional slaves */ 1264 static void i801_probe_optional_slaves(struct i801_priv *priv) 1265 { 1266 /* Only register slaves on main SMBus channel */ 1267 if (priv->features & FEATURE_IDF) 1268 return; 1269 1270 if (apanel_addr) { 1271 struct i2c_board_info info = { 1272 .addr = apanel_addr, 1273 .type = "fujitsu_apanel", 1274 }; 1275 1276 i2c_new_client_device(&priv->adapter, &info); 1277 } 1278 1279 if (dmi_name_in_vendors("FUJITSU")) 1280 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1281 1282 if (is_dell_system_with_lis3lv02d()) 1283 register_dell_lis3lv02d_i2c_device(priv); 1284 1285 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1286 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1287 if (!priv->mux_drvdata) 1288 #endif 1289 i2c_register_spd(&priv->adapter); 1290 } 1291 #else 1292 static void __init input_apanel_init(void) {} 1293 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1294 #endif /* CONFIG_X86 && CONFIG_DMI */ 1295 1296 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1297 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1298 .gpio_chip = "gpio_ich", 1299 .values = { 0x02, 0x03 }, 1300 .n_values = 2, 1301 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1302 .gpios = { 52, 53 }, 1303 .n_gpios = 2, 1304 }; 1305 1306 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1307 .gpio_chip = "gpio_ich", 1308 .values = { 0x02, 0x03, 0x01 }, 1309 .n_values = 3, 1310 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1311 .gpios = { 52, 53 }, 1312 .n_gpios = 2, 1313 }; 1314 1315 static const struct dmi_system_id mux_dmi_table[] = { 1316 { 1317 .matches = { 1318 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1319 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1320 }, 1321 .driver_data = &i801_mux_config_asus_z8_d12, 1322 }, 1323 { 1324 .matches = { 1325 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1326 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1327 }, 1328 .driver_data = &i801_mux_config_asus_z8_d12, 1329 }, 1330 { 1331 .matches = { 1332 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1333 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1334 }, 1335 .driver_data = &i801_mux_config_asus_z8_d12, 1336 }, 1337 { 1338 .matches = { 1339 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1340 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1341 }, 1342 .driver_data = &i801_mux_config_asus_z8_d12, 1343 }, 1344 { 1345 .matches = { 1346 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1347 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1348 }, 1349 .driver_data = &i801_mux_config_asus_z8_d12, 1350 }, 1351 { 1352 .matches = { 1353 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1354 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1355 }, 1356 .driver_data = &i801_mux_config_asus_z8_d12, 1357 }, 1358 { 1359 .matches = { 1360 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1361 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1362 }, 1363 .driver_data = &i801_mux_config_asus_z8_d18, 1364 }, 1365 { 1366 .matches = { 1367 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1368 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1369 }, 1370 .driver_data = &i801_mux_config_asus_z8_d18, 1371 }, 1372 { 1373 .matches = { 1374 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1375 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1376 }, 1377 .driver_data = &i801_mux_config_asus_z8_d12, 1378 }, 1379 { } 1380 }; 1381 1382 /* Setup multiplexing if needed */ 1383 static void i801_add_mux(struct i801_priv *priv) 1384 { 1385 struct device *dev = &priv->adapter.dev; 1386 const struct i801_mux_config *mux_config; 1387 struct i2c_mux_gpio_platform_data gpio_data; 1388 struct gpiod_lookup_table *lookup; 1389 int i; 1390 1391 if (!priv->mux_drvdata) 1392 return; 1393 mux_config = priv->mux_drvdata; 1394 1395 /* Prepare the platform data */ 1396 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1397 gpio_data.parent = priv->adapter.nr; 1398 gpio_data.values = mux_config->values; 1399 gpio_data.n_values = mux_config->n_values; 1400 gpio_data.classes = mux_config->classes; 1401 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1402 1403 /* Register GPIO descriptor lookup table */ 1404 lookup = devm_kzalloc(dev, 1405 struct_size(lookup, table, mux_config->n_gpios + 1), 1406 GFP_KERNEL); 1407 if (!lookup) 1408 return; 1409 lookup->dev_id = "i2c-mux-gpio"; 1410 for (i = 0; i < mux_config->n_gpios; i++) 1411 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip, 1412 mux_config->gpios[i], "mux", 0); 1413 gpiod_add_lookup_table(lookup); 1414 priv->lookup = lookup; 1415 1416 /* 1417 * Register the mux device, we use PLATFORM_DEVID_NONE here 1418 * because since we are referring to the GPIO chip by name we are 1419 * anyways in deep trouble if there is more than one of these 1420 * devices, and there should likely only be one platform controller 1421 * hub. 1422 */ 1423 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1424 PLATFORM_DEVID_NONE, &gpio_data, 1425 sizeof(struct i2c_mux_gpio_platform_data)); 1426 if (IS_ERR(priv->mux_pdev)) { 1427 gpiod_remove_lookup_table(lookup); 1428 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1429 } 1430 } 1431 1432 static void i801_del_mux(struct i801_priv *priv) 1433 { 1434 platform_device_unregister(priv->mux_pdev); 1435 gpiod_remove_lookup_table(priv->lookup); 1436 } 1437 1438 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1439 { 1440 const struct dmi_system_id *id; 1441 const struct i801_mux_config *mux_config; 1442 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1443 int i; 1444 1445 id = dmi_first_match(mux_dmi_table); 1446 if (id) { 1447 /* Remove branch classes from trunk */ 1448 mux_config = id->driver_data; 1449 for (i = 0; i < mux_config->n_values; i++) 1450 class &= ~mux_config->classes[i]; 1451 1452 /* Remember for later */ 1453 priv->mux_drvdata = mux_config; 1454 } 1455 1456 return class; 1457 } 1458 #else 1459 static inline void i801_add_mux(struct i801_priv *priv) { } 1460 static inline void i801_del_mux(struct i801_priv *priv) { } 1461 1462 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1463 { 1464 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1465 } 1466 #endif 1467 1468 static struct platform_device * 1469 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1470 struct resource *tco_res) 1471 { 1472 static const struct itco_wdt_platform_data pldata = { 1473 .name = "Intel PCH", 1474 .version = 4, 1475 }; 1476 struct resource *res; 1477 unsigned int devfn; 1478 u64 base64_addr; 1479 u32 base_addr; 1480 u8 hidden; 1481 1482 /* 1483 * We must access the NO_REBOOT bit over the Primary to Sideband 1484 * bridge (P2SB). The BIOS prevents the P2SB device from being 1485 * enumerated by the PCI subsystem, so we need to unhide/hide it 1486 * to lookup the P2SB BAR. 1487 */ 1488 pci_lock_rescan_remove(); 1489 1490 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1491 1492 /* Unhide the P2SB device, if it is hidden */ 1493 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1494 if (hidden) 1495 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1496 1497 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1498 base64_addr = base_addr & 0xfffffff0; 1499 1500 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1501 base64_addr |= (u64)base_addr << 32; 1502 1503 /* Hide the P2SB device, if it was hidden before */ 1504 if (hidden) 1505 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1506 pci_unlock_rescan_remove(); 1507 1508 res = &tco_res[1]; 1509 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1510 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1511 else 1512 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1513 1514 res->end = res->start + 3; 1515 res->flags = IORESOURCE_MEM; 1516 1517 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1518 tco_res, 2, &pldata, sizeof(pldata)); 1519 } 1520 1521 static struct platform_device * 1522 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1523 struct resource *tco_res) 1524 { 1525 static const struct itco_wdt_platform_data pldata = { 1526 .name = "Intel PCH", 1527 .version = 6, 1528 }; 1529 1530 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1531 tco_res, 1, &pldata, sizeof(pldata)); 1532 } 1533 1534 static void i801_add_tco(struct i801_priv *priv) 1535 { 1536 struct pci_dev *pci_dev = priv->pci_dev; 1537 struct resource tco_res[2], *res; 1538 u32 tco_base, tco_ctl; 1539 1540 /* If we have ACPI based watchdog use that instead */ 1541 if (acpi_has_watchdog()) 1542 return; 1543 1544 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1545 return; 1546 1547 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1548 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1549 if (!(tco_ctl & TCOCTL_EN)) 1550 return; 1551 1552 memset(tco_res, 0, sizeof(tco_res)); 1553 /* 1554 * Always populate the main iTCO IO resource here. The second entry 1555 * for NO_REBOOT MMIO is filled by the SPT specific function. 1556 */ 1557 res = &tco_res[0]; 1558 res->start = tco_base & ~1; 1559 res->end = res->start + 32 - 1; 1560 res->flags = IORESOURCE_IO; 1561 1562 if (priv->features & FEATURE_TCO_CNL) 1563 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1564 else 1565 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1566 1567 if (IS_ERR(priv->tco_pdev)) 1568 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1569 } 1570 1571 #ifdef CONFIG_ACPI 1572 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1573 acpi_physical_address address) 1574 { 1575 return address >= priv->smba && 1576 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1577 } 1578 1579 static acpi_status 1580 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1581 u64 *value, void *handler_context, void *region_context) 1582 { 1583 struct i801_priv *priv = handler_context; 1584 struct pci_dev *pdev = priv->pci_dev; 1585 acpi_status status; 1586 1587 /* 1588 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1589 * further access from the driver itself. This device is now owned 1590 * by the system firmware. 1591 */ 1592 mutex_lock(&priv->acpi_lock); 1593 1594 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1595 priv->acpi_reserved = true; 1596 1597 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1598 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1599 1600 /* 1601 * BIOS is accessing the host controller so prevent it from 1602 * suspending automatically from now on. 1603 */ 1604 pm_runtime_get_sync(&pdev->dev); 1605 } 1606 1607 if ((function & ACPI_IO_MASK) == ACPI_READ) 1608 status = acpi_os_read_port(address, (u32 *)value, bits); 1609 else 1610 status = acpi_os_write_port(address, (u32)*value, bits); 1611 1612 mutex_unlock(&priv->acpi_lock); 1613 1614 return status; 1615 } 1616 1617 static int i801_acpi_probe(struct i801_priv *priv) 1618 { 1619 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1620 acpi_status status; 1621 1622 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, 1623 i801_acpi_io_handler, NULL, priv); 1624 if (ACPI_SUCCESS(status)) 1625 return 0; 1626 1627 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1628 } 1629 1630 static void i801_acpi_remove(struct i801_priv *priv) 1631 { 1632 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1633 1634 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1635 } 1636 #else 1637 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1638 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1639 #endif 1640 1641 static void i801_setup_hstcfg(struct i801_priv *priv) 1642 { 1643 unsigned char hstcfg = priv->original_hstcfg; 1644 1645 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1646 hstcfg |= SMBHSTCFG_HST_EN; 1647 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1648 } 1649 1650 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1651 { 1652 int err, i; 1653 struct i801_priv *priv; 1654 1655 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1656 if (!priv) 1657 return -ENOMEM; 1658 1659 i2c_set_adapdata(&priv->adapter, priv); 1660 priv->adapter.owner = THIS_MODULE; 1661 priv->adapter.class = i801_get_adapter_class(priv); 1662 priv->adapter.algo = &smbus_algorithm; 1663 priv->adapter.dev.parent = &dev->dev; 1664 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1665 priv->adapter.retries = 3; 1666 mutex_init(&priv->acpi_lock); 1667 1668 priv->pci_dev = dev; 1669 priv->features = id->driver_data; 1670 1671 /* Disable features on user request */ 1672 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1673 if (priv->features & disable_features & (1 << i)) 1674 dev_notice(&dev->dev, "%s disabled by user\n", 1675 i801_feature_names[i]); 1676 } 1677 priv->features &= ~disable_features; 1678 1679 err = pcim_enable_device(dev); 1680 if (err) { 1681 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1682 err); 1683 return err; 1684 } 1685 pcim_pin_device(dev); 1686 1687 /* Determine the address of the SMBus area */ 1688 priv->smba = pci_resource_start(dev, SMBBAR); 1689 if (!priv->smba) { 1690 dev_err(&dev->dev, 1691 "SMBus base address uninitialized, upgrade BIOS\n"); 1692 return -ENODEV; 1693 } 1694 1695 if (i801_acpi_probe(priv)) 1696 return -ENODEV; 1697 1698 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME); 1699 if (err) { 1700 dev_err(&dev->dev, 1701 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1702 priv->smba, 1703 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1704 i801_acpi_remove(priv); 1705 return err; 1706 } 1707 1708 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1709 i801_setup_hstcfg(priv); 1710 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1711 dev_info(&dev->dev, "Enabling SMBus device\n"); 1712 1713 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1714 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1715 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1716 priv->features &= ~FEATURE_IRQ; 1717 } 1718 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1719 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1720 1721 /* Clear special mode bits */ 1722 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1723 outb_p(inb_p(SMBAUXCTL(priv)) & 1724 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1725 1726 /* Remember original Interrupt and Host Notify settings */ 1727 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL; 1728 if (priv->features & FEATURE_HOST_NOTIFY) 1729 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1730 1731 /* Default timeout in interrupt mode: 200 ms */ 1732 priv->adapter.timeout = HZ / 5; 1733 1734 if (dev->irq == IRQ_NOTCONNECTED) 1735 priv->features &= ~FEATURE_IRQ; 1736 1737 if (priv->features & FEATURE_IRQ) { 1738 u16 pcists; 1739 1740 /* Complain if an interrupt is already pending */ 1741 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1742 if (pcists & PCI_STATUS_INTERRUPT) 1743 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1744 } 1745 1746 if (priv->features & FEATURE_IRQ) { 1747 init_completion(&priv->done); 1748 1749 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1750 IRQF_SHARED, DRV_NAME, priv); 1751 if (err) { 1752 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1753 dev->irq, err); 1754 priv->features &= ~FEATURE_IRQ; 1755 } 1756 } 1757 dev_info(&dev->dev, "SMBus using %s\n", 1758 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1759 1760 i801_add_tco(priv); 1761 1762 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1763 "SMBus I801 adapter at %04lx", priv->smba); 1764 err = i2c_add_adapter(&priv->adapter); 1765 if (err) { 1766 i801_acpi_remove(priv); 1767 return err; 1768 } 1769 1770 i801_enable_host_notify(&priv->adapter); 1771 1772 i801_probe_optional_slaves(priv); 1773 /* We ignore errors - multiplexing is optional */ 1774 i801_add_mux(priv); 1775 1776 pci_set_drvdata(dev, priv); 1777 1778 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1779 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1780 pm_runtime_use_autosuspend(&dev->dev); 1781 pm_runtime_put_autosuspend(&dev->dev); 1782 pm_runtime_allow(&dev->dev); 1783 1784 return 0; 1785 } 1786 1787 static void i801_remove(struct pci_dev *dev) 1788 { 1789 struct i801_priv *priv = pci_get_drvdata(dev); 1790 1791 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1792 i801_disable_host_notify(priv); 1793 i801_del_mux(priv); 1794 i2c_del_adapter(&priv->adapter); 1795 i801_acpi_remove(priv); 1796 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1797 1798 platform_device_unregister(priv->tco_pdev); 1799 1800 /* if acpi_reserved is set then usage_count is incremented already */ 1801 if (!priv->acpi_reserved) 1802 pm_runtime_get_noresume(&dev->dev); 1803 1804 /* 1805 * do not call pci_disable_device(dev) since it can cause hard hangs on 1806 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1807 */ 1808 } 1809 1810 static void i801_shutdown(struct pci_dev *dev) 1811 { 1812 struct i801_priv *priv = pci_get_drvdata(dev); 1813 1814 /* Restore config registers to avoid hard hang on some systems */ 1815 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1816 i801_disable_host_notify(priv); 1817 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1818 } 1819 1820 #ifdef CONFIG_PM_SLEEP 1821 static int i801_suspend(struct device *dev) 1822 { 1823 struct i801_priv *priv = dev_get_drvdata(dev); 1824 1825 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1826 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1827 return 0; 1828 } 1829 1830 static int i801_resume(struct device *dev) 1831 { 1832 struct i801_priv *priv = dev_get_drvdata(dev); 1833 1834 i801_setup_hstcfg(priv); 1835 i801_enable_host_notify(&priv->adapter); 1836 1837 return 0; 1838 } 1839 #endif 1840 1841 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1842 1843 static struct pci_driver i801_driver = { 1844 .name = DRV_NAME, 1845 .id_table = i801_ids, 1846 .probe = i801_probe, 1847 .remove = i801_remove, 1848 .shutdown = i801_shutdown, 1849 .driver = { 1850 .pm = &i801_pm_ops, 1851 }, 1852 }; 1853 1854 static int __init i2c_i801_init(void) 1855 { 1856 if (dmi_name_in_vendors("FUJITSU")) 1857 input_apanel_init(); 1858 return pci_register_driver(&i801_driver); 1859 } 1860 1861 static void __exit i2c_i801_exit(void) 1862 { 1863 pci_unregister_driver(&i801_driver); 1864 } 1865 1866 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1867 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1868 MODULE_DESCRIPTION("I801 SMBus driver"); 1869 MODULE_LICENSE("GPL"); 1870 1871 module_init(i2c_i801_init); 1872 module_exit(i2c_i801_exit); 1873