1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 68 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 69 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 70 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 71 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 72 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 73 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 74 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 75 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 76 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 77 * 78 * Features supported by this driver: 79 * Software PEC no 80 * Hardware PEC yes 81 * Block buffer yes 82 * Block process call transaction yes 83 * I2C block read transaction yes (doesn't use the block buffer) 84 * Slave mode no 85 * SMBus Host Notify yes 86 * Interrupt processing yes 87 * 88 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 89 */ 90 91 #include <linux/interrupt.h> 92 #include <linux/module.h> 93 #include <linux/pci.h> 94 #include <linux/kernel.h> 95 #include <linux/stddef.h> 96 #include <linux/delay.h> 97 #include <linux/ioport.h> 98 #include <linux/init.h> 99 #include <linux/i2c.h> 100 #include <linux/i2c-smbus.h> 101 #include <linux/acpi.h> 102 #include <linux/io.h> 103 #include <linux/dmi.h> 104 #include <linux/slab.h> 105 #include <linux/string.h> 106 #include <linux/wait.h> 107 #include <linux/err.h> 108 #include <linux/platform_device.h> 109 #include <linux/platform_data/itco_wdt.h> 110 #include <linux/pm_runtime.h> 111 112 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 113 #include <linux/gpio/machine.h> 114 #include <linux/platform_data/i2c-mux-gpio.h> 115 #endif 116 117 /* I801 SMBus address offsets */ 118 #define SMBHSTSTS(p) (0 + (p)->smba) 119 #define SMBHSTCNT(p) (2 + (p)->smba) 120 #define SMBHSTCMD(p) (3 + (p)->smba) 121 #define SMBHSTADD(p) (4 + (p)->smba) 122 #define SMBHSTDAT0(p) (5 + (p)->smba) 123 #define SMBHSTDAT1(p) (6 + (p)->smba) 124 #define SMBBLKDAT(p) (7 + (p)->smba) 125 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 126 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 127 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 128 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 129 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 130 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 131 132 /* PCI Address Constants */ 133 #define SMBBAR 4 134 #define SMBPCICTL 0x004 135 #define SMBPCISTS 0x006 136 #define SMBHSTCFG 0x040 137 #define TCOBASE 0x050 138 #define TCOCTL 0x054 139 140 #define SBREG_BAR 0x10 141 #define SBREG_SMBCTRL 0xc6000c 142 #define SBREG_SMBCTRL_DNV 0xcf000c 143 144 /* Host status bits for SMBPCISTS */ 145 #define SMBPCISTS_INTS BIT(3) 146 147 /* Control bits for SMBPCICTL */ 148 #define SMBPCICTL_INTDIS BIT(10) 149 150 /* Host configuration bits for SMBHSTCFG */ 151 #define SMBHSTCFG_HST_EN BIT(0) 152 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 153 #define SMBHSTCFG_I2C_EN BIT(2) 154 #define SMBHSTCFG_SPD_WD BIT(4) 155 156 /* TCO configuration bits for TCOCTL */ 157 #define TCOCTL_EN BIT(8) 158 159 /* Auxiliary status register bits, ICH4+ only */ 160 #define SMBAUXSTS_CRCE BIT(0) 161 #define SMBAUXSTS_STCO BIT(1) 162 163 /* Auxiliary control register bits, ICH4+ only */ 164 #define SMBAUXCTL_CRC BIT(0) 165 #define SMBAUXCTL_E32B BIT(1) 166 167 /* Other settings */ 168 #define MAX_RETRIES 400 169 170 /* I801 command constants */ 171 #define I801_QUICK 0x00 172 #define I801_BYTE 0x04 173 #define I801_BYTE_DATA 0x08 174 #define I801_WORD_DATA 0x0C 175 #define I801_PROC_CALL 0x10 /* unimplemented */ 176 #define I801_BLOCK_DATA 0x14 177 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 178 #define I801_BLOCK_PROC_CALL 0x1C 179 180 /* I801 Host Control register bits */ 181 #define SMBHSTCNT_INTREN BIT(0) 182 #define SMBHSTCNT_KILL BIT(1) 183 #define SMBHSTCNT_LAST_BYTE BIT(5) 184 #define SMBHSTCNT_START BIT(6) 185 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 186 187 /* I801 Hosts Status register bits */ 188 #define SMBHSTSTS_BYTE_DONE BIT(7) 189 #define SMBHSTSTS_INUSE_STS BIT(6) 190 #define SMBHSTSTS_SMBALERT_STS BIT(5) 191 #define SMBHSTSTS_FAILED BIT(4) 192 #define SMBHSTSTS_BUS_ERR BIT(3) 193 #define SMBHSTSTS_DEV_ERR BIT(2) 194 #define SMBHSTSTS_INTR BIT(1) 195 #define SMBHSTSTS_HOST_BUSY BIT(0) 196 197 /* Host Notify Status register bits */ 198 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 199 200 /* Host Notify Command register bits */ 201 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 202 203 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 204 SMBHSTSTS_DEV_ERR) 205 206 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 207 STATUS_ERROR_FLAGS) 208 209 /* Older devices have their ID defined in <linux/pci_ids.h> */ 210 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 211 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 212 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 213 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 214 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 215 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 216 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 218 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 220 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 221 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 222 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 223 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 224 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 225 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 226 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 227 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 228 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 229 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 230 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 231 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 232 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 233 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 234 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 235 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 236 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 237 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 238 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 239 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 240 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 241 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 242 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 243 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 244 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 245 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 246 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 247 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 248 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 249 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 250 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 251 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 252 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 253 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 254 255 struct i801_mux_config { 256 char *gpio_chip; 257 unsigned values[3]; 258 int n_values; 259 unsigned classes[3]; 260 unsigned gpios[2]; /* Relative to gpio_chip->base */ 261 int n_gpios; 262 }; 263 264 struct i801_priv { 265 struct i2c_adapter adapter; 266 unsigned long smba; 267 unsigned char original_hstcfg; 268 unsigned char original_slvcmd; 269 struct pci_dev *pci_dev; 270 unsigned int features; 271 272 /* isr processing */ 273 wait_queue_head_t waitq; 274 u8 status; 275 276 /* Command state used by isr for byte-by-byte block transactions */ 277 u8 cmd; 278 bool is_read; 279 int count; 280 int len; 281 u8 *data; 282 283 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 284 const struct i801_mux_config *mux_drvdata; 285 struct platform_device *mux_pdev; 286 struct gpiod_lookup_table *lookup; 287 #endif 288 struct platform_device *tco_pdev; 289 290 /* 291 * If set to true the host controller registers are reserved for 292 * ACPI AML use. Protected by acpi_lock. 293 */ 294 bool acpi_reserved; 295 struct mutex acpi_lock; 296 }; 297 298 #define FEATURE_SMBUS_PEC BIT(0) 299 #define FEATURE_BLOCK_BUFFER BIT(1) 300 #define FEATURE_BLOCK_PROC BIT(2) 301 #define FEATURE_I2C_BLOCK_READ BIT(3) 302 #define FEATURE_IRQ BIT(4) 303 #define FEATURE_HOST_NOTIFY BIT(5) 304 /* Not really a feature, but it's convenient to handle it as such */ 305 #define FEATURE_IDF BIT(15) 306 #define FEATURE_TCO_SPT BIT(16) 307 #define FEATURE_TCO_CNL BIT(17) 308 309 static const char *i801_feature_names[] = { 310 "SMBus PEC", 311 "Block buffer", 312 "Block process call", 313 "I2C block read", 314 "Interrupt", 315 "SMBus Host Notify", 316 }; 317 318 static unsigned int disable_features; 319 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 320 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 321 "\t\t 0x01 disable SMBus PEC\n" 322 "\t\t 0x02 disable the block buffer\n" 323 "\t\t 0x08 disable the I2C block read functionality\n" 324 "\t\t 0x10 don't use interrupts\n" 325 "\t\t 0x20 disable SMBus Host Notify "); 326 327 /* Make sure the SMBus host is ready to start transmitting. 328 Return 0 if it is, -EBUSY if it is not. */ 329 static int i801_check_pre(struct i801_priv *priv) 330 { 331 int status; 332 333 status = inb_p(SMBHSTSTS(priv)); 334 if (status & SMBHSTSTS_HOST_BUSY) { 335 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 336 return -EBUSY; 337 } 338 339 status &= STATUS_FLAGS; 340 if (status) { 341 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 342 status); 343 outb_p(status, SMBHSTSTS(priv)); 344 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 345 if (status) { 346 dev_err(&priv->pci_dev->dev, 347 "Failed clearing status flags (%02x)\n", 348 status); 349 return -EBUSY; 350 } 351 } 352 353 /* 354 * Clear CRC status if needed. 355 * During normal operation, i801_check_post() takes care 356 * of it after every operation. We do it here only in case 357 * the hardware was already in this state when the driver 358 * started. 359 */ 360 if (priv->features & FEATURE_SMBUS_PEC) { 361 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 362 if (status) { 363 dev_dbg(&priv->pci_dev->dev, 364 "Clearing aux status flags (%02x)\n", status); 365 outb_p(status, SMBAUXSTS(priv)); 366 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 367 if (status) { 368 dev_err(&priv->pci_dev->dev, 369 "Failed clearing aux status flags (%02x)\n", 370 status); 371 return -EBUSY; 372 } 373 } 374 } 375 376 return 0; 377 } 378 379 /* 380 * Convert the status register to an error code, and clear it. 381 * Note that status only contains the bits we want to clear, not the 382 * actual register value. 383 */ 384 static int i801_check_post(struct i801_priv *priv, int status) 385 { 386 int result = 0; 387 388 /* 389 * If the SMBus is still busy, we give up 390 * Note: This timeout condition only happens when using polling 391 * transactions. For interrupt operation, NAK/timeout is indicated by 392 * DEV_ERR. 393 */ 394 if (unlikely(status < 0)) { 395 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 396 /* try to stop the current command */ 397 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 398 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 399 usleep_range(1000, 2000); 400 outb_p(0, SMBHSTCNT(priv)); 401 402 /* Check if it worked */ 403 status = inb_p(SMBHSTSTS(priv)); 404 if ((status & SMBHSTSTS_HOST_BUSY) || 405 !(status & SMBHSTSTS_FAILED)) 406 dev_err(&priv->pci_dev->dev, 407 "Failed terminating the transaction\n"); 408 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 409 return -ETIMEDOUT; 410 } 411 412 if (status & SMBHSTSTS_FAILED) { 413 result = -EIO; 414 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 415 } 416 if (status & SMBHSTSTS_DEV_ERR) { 417 /* 418 * This may be a PEC error, check and clear it. 419 * 420 * AUXSTS is handled differently from HSTSTS. 421 * For HSTSTS, i801_isr() or i801_wait_intr() 422 * has already cleared the error bits in hardware, 423 * and we are passed a copy of the original value 424 * in "status". 425 * For AUXSTS, the hardware register is left 426 * for us to handle here. 427 * This is asymmetric, slightly iffy, but safe, 428 * since all this code is serialized and the CRCE 429 * bit is harmless as long as it's cleared before 430 * the next operation. 431 */ 432 if ((priv->features & FEATURE_SMBUS_PEC) && 433 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 434 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 435 result = -EBADMSG; 436 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 437 } else { 438 result = -ENXIO; 439 dev_dbg(&priv->pci_dev->dev, "No response\n"); 440 } 441 } 442 if (status & SMBHSTSTS_BUS_ERR) { 443 result = -EAGAIN; 444 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 445 } 446 447 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 448 outb_p(status, SMBHSTSTS(priv)); 449 450 return result; 451 } 452 453 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 454 static int i801_wait_intr(struct i801_priv *priv) 455 { 456 int timeout = 0; 457 int status; 458 459 /* We will always wait for a fraction of a second! */ 460 do { 461 usleep_range(250, 500); 462 status = inb_p(SMBHSTSTS(priv)); 463 } while (((status & SMBHSTSTS_HOST_BUSY) || 464 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 465 (timeout++ < MAX_RETRIES)); 466 467 if (timeout > MAX_RETRIES) { 468 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 469 return -ETIMEDOUT; 470 } 471 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 472 } 473 474 /* Wait for either BYTE_DONE or an error flag being set */ 475 static int i801_wait_byte_done(struct i801_priv *priv) 476 { 477 int timeout = 0; 478 int status; 479 480 /* We will always wait for a fraction of a second! */ 481 do { 482 usleep_range(250, 500); 483 status = inb_p(SMBHSTSTS(priv)); 484 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 485 (timeout++ < MAX_RETRIES)); 486 487 if (timeout > MAX_RETRIES) { 488 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 489 return -ETIMEDOUT; 490 } 491 return status & STATUS_ERROR_FLAGS; 492 } 493 494 static int i801_transaction(struct i801_priv *priv, int xact) 495 { 496 int status; 497 int result; 498 const struct i2c_adapter *adap = &priv->adapter; 499 500 result = i801_check_pre(priv); 501 if (result < 0) 502 return result; 503 504 if (priv->features & FEATURE_IRQ) { 505 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 506 SMBHSTCNT(priv)); 507 result = wait_event_timeout(priv->waitq, 508 (status = priv->status), 509 adap->timeout); 510 if (!result) { 511 status = -ETIMEDOUT; 512 dev_warn(&priv->pci_dev->dev, 513 "Timeout waiting for interrupt!\n"); 514 } 515 priv->status = 0; 516 return i801_check_post(priv, status); 517 } 518 519 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 520 * SMBSCMD are passed in xact */ 521 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 522 523 status = i801_wait_intr(priv); 524 return i801_check_post(priv, status); 525 } 526 527 static int i801_block_transaction_by_block(struct i801_priv *priv, 528 union i2c_smbus_data *data, 529 char read_write, int command, 530 int hwpec) 531 { 532 int i, len; 533 int status; 534 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0; 535 536 switch (command) { 537 case I2C_SMBUS_BLOCK_PROC_CALL: 538 xact |= I801_BLOCK_PROC_CALL; 539 break; 540 case I2C_SMBUS_BLOCK_DATA: 541 xact |= I801_BLOCK_DATA; 542 break; 543 default: 544 return -EOPNOTSUPP; 545 } 546 547 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 548 549 /* Use 32-byte buffer to process this transaction */ 550 if (read_write == I2C_SMBUS_WRITE) { 551 len = data->block[0]; 552 outb_p(len, SMBHSTDAT0(priv)); 553 for (i = 0; i < len; i++) 554 outb_p(data->block[i+1], SMBBLKDAT(priv)); 555 } 556 557 status = i801_transaction(priv, xact); 558 if (status) 559 return status; 560 561 if (read_write == I2C_SMBUS_READ || 562 command == I2C_SMBUS_BLOCK_PROC_CALL) { 563 len = inb_p(SMBHSTDAT0(priv)); 564 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 565 return -EPROTO; 566 567 data->block[0] = len; 568 for (i = 0; i < len; i++) 569 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 570 } 571 return 0; 572 } 573 574 static void i801_isr_byte_done(struct i801_priv *priv) 575 { 576 if (priv->is_read) { 577 /* For SMBus block reads, length is received with first byte */ 578 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 579 (priv->count == 0)) { 580 priv->len = inb_p(SMBHSTDAT0(priv)); 581 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 582 dev_err(&priv->pci_dev->dev, 583 "Illegal SMBus block read size %d\n", 584 priv->len); 585 /* FIXME: Recover */ 586 priv->len = I2C_SMBUS_BLOCK_MAX; 587 } else { 588 dev_dbg(&priv->pci_dev->dev, 589 "SMBus block read size is %d\n", 590 priv->len); 591 } 592 priv->data[-1] = priv->len; 593 } 594 595 /* Read next byte */ 596 if (priv->count < priv->len) 597 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 598 else 599 dev_dbg(&priv->pci_dev->dev, 600 "Discarding extra byte on block read\n"); 601 602 /* Set LAST_BYTE for last byte of read transaction */ 603 if (priv->count == priv->len - 1) 604 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 605 SMBHSTCNT(priv)); 606 } else if (priv->count < priv->len - 1) { 607 /* Write next byte, except for IRQ after last byte */ 608 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 609 } 610 611 /* Clear BYTE_DONE to continue with next byte */ 612 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 613 } 614 615 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 616 { 617 unsigned short addr; 618 619 addr = inb_p(SMBNTFDADD(priv)) >> 1; 620 621 /* 622 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 623 * always returns 0. Our current implementation doesn't provide 624 * data, so we just ignore it. 625 */ 626 i2c_handle_smbus_host_notify(&priv->adapter, addr); 627 628 /* clear Host Notify bit and return */ 629 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 630 return IRQ_HANDLED; 631 } 632 633 /* 634 * There are three kinds of interrupts: 635 * 636 * 1) i801 signals transaction completion with one of these interrupts: 637 * INTR - Success 638 * DEV_ERR - Invalid command, NAK or communication timeout 639 * BUS_ERR - SMI# transaction collision 640 * FAILED - transaction was canceled due to a KILL request 641 * When any of these occur, update ->status and wake up the waitq. 642 * ->status must be cleared before kicking off the next transaction. 643 * 644 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 645 * occurs for each byte of a byte-by-byte to prepare the next byte. 646 * 647 * 3) Host Notify interrupts 648 */ 649 static irqreturn_t i801_isr(int irq, void *dev_id) 650 { 651 struct i801_priv *priv = dev_id; 652 u16 pcists; 653 u8 status; 654 655 /* Confirm this is our interrupt */ 656 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 657 if (!(pcists & SMBPCISTS_INTS)) 658 return IRQ_NONE; 659 660 if (priv->features & FEATURE_HOST_NOTIFY) { 661 status = inb_p(SMBSLVSTS(priv)); 662 if (status & SMBSLVSTS_HST_NTFY_STS) 663 return i801_host_notify_isr(priv); 664 } 665 666 status = inb_p(SMBHSTSTS(priv)); 667 if (status & SMBHSTSTS_BYTE_DONE) 668 i801_isr_byte_done(priv); 669 670 /* 671 * Clear irq sources and report transaction result. 672 * ->status must be cleared before the next transaction is started. 673 */ 674 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 675 if (status) { 676 outb_p(status, SMBHSTSTS(priv)); 677 priv->status = status; 678 wake_up(&priv->waitq); 679 } 680 681 return IRQ_HANDLED; 682 } 683 684 /* 685 * For "byte-by-byte" block transactions: 686 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 687 * I2C read uses cmd=I801_I2C_BLOCK_DATA 688 */ 689 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 690 union i2c_smbus_data *data, 691 char read_write, int command, 692 int hwpec) 693 { 694 int i, len; 695 int smbcmd; 696 int status; 697 int result; 698 const struct i2c_adapter *adap = &priv->adapter; 699 700 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 701 return -EOPNOTSUPP; 702 703 result = i801_check_pre(priv); 704 if (result < 0) 705 return result; 706 707 len = data->block[0]; 708 709 if (read_write == I2C_SMBUS_WRITE) { 710 outb_p(len, SMBHSTDAT0(priv)); 711 outb_p(data->block[1], SMBBLKDAT(priv)); 712 } 713 714 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 715 read_write == I2C_SMBUS_READ) 716 smbcmd = I801_I2C_BLOCK_DATA; 717 else 718 smbcmd = I801_BLOCK_DATA; 719 720 if (priv->features & FEATURE_IRQ) { 721 priv->is_read = (read_write == I2C_SMBUS_READ); 722 if (len == 1 && priv->is_read) 723 smbcmd |= SMBHSTCNT_LAST_BYTE; 724 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 725 priv->len = len; 726 priv->count = 0; 727 priv->data = &data->block[1]; 728 729 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 730 result = wait_event_timeout(priv->waitq, 731 (status = priv->status), 732 adap->timeout); 733 if (!result) { 734 status = -ETIMEDOUT; 735 dev_warn(&priv->pci_dev->dev, 736 "Timeout waiting for interrupt!\n"); 737 } 738 priv->status = 0; 739 return i801_check_post(priv, status); 740 } 741 742 for (i = 1; i <= len; i++) { 743 if (i == len && read_write == I2C_SMBUS_READ) 744 smbcmd |= SMBHSTCNT_LAST_BYTE; 745 outb_p(smbcmd, SMBHSTCNT(priv)); 746 747 if (i == 1) 748 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 749 SMBHSTCNT(priv)); 750 751 status = i801_wait_byte_done(priv); 752 if (status) 753 goto exit; 754 755 if (i == 1 && read_write == I2C_SMBUS_READ 756 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 757 len = inb_p(SMBHSTDAT0(priv)); 758 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 759 dev_err(&priv->pci_dev->dev, 760 "Illegal SMBus block read size %d\n", 761 len); 762 /* Recover */ 763 while (inb_p(SMBHSTSTS(priv)) & 764 SMBHSTSTS_HOST_BUSY) 765 outb_p(SMBHSTSTS_BYTE_DONE, 766 SMBHSTSTS(priv)); 767 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 768 return -EPROTO; 769 } 770 data->block[0] = len; 771 } 772 773 /* Retrieve/store value in SMBBLKDAT */ 774 if (read_write == I2C_SMBUS_READ) 775 data->block[i] = inb_p(SMBBLKDAT(priv)); 776 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 777 outb_p(data->block[i+1], SMBBLKDAT(priv)); 778 779 /* signals SMBBLKDAT ready */ 780 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 781 } 782 783 status = i801_wait_intr(priv); 784 exit: 785 return i801_check_post(priv, status); 786 } 787 788 static int i801_set_block_buffer_mode(struct i801_priv *priv) 789 { 790 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 791 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 792 return -EIO; 793 return 0; 794 } 795 796 /* Block transaction function */ 797 static int i801_block_transaction(struct i801_priv *priv, 798 union i2c_smbus_data *data, char read_write, 799 int command, int hwpec) 800 { 801 int result = 0; 802 unsigned char hostc; 803 804 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 805 if (read_write == I2C_SMBUS_WRITE) { 806 /* set I2C_EN bit in configuration register */ 807 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 808 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 809 hostc | SMBHSTCFG_I2C_EN); 810 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 811 dev_err(&priv->pci_dev->dev, 812 "I2C block read is unsupported!\n"); 813 return -EOPNOTSUPP; 814 } 815 } 816 817 if (read_write == I2C_SMBUS_WRITE 818 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 819 if (data->block[0] < 1) 820 data->block[0] = 1; 821 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 822 data->block[0] = I2C_SMBUS_BLOCK_MAX; 823 } else { 824 data->block[0] = 32; /* max for SMBus block reads */ 825 } 826 827 /* Experience has shown that the block buffer can only be used for 828 SMBus (not I2C) block transactions, even though the datasheet 829 doesn't mention this limitation. */ 830 if ((priv->features & FEATURE_BLOCK_BUFFER) 831 && command != I2C_SMBUS_I2C_BLOCK_DATA 832 && i801_set_block_buffer_mode(priv) == 0) 833 result = i801_block_transaction_by_block(priv, data, 834 read_write, 835 command, hwpec); 836 else 837 result = i801_block_transaction_byte_by_byte(priv, data, 838 read_write, 839 command, hwpec); 840 841 if (command == I2C_SMBUS_I2C_BLOCK_DATA 842 && read_write == I2C_SMBUS_WRITE) { 843 /* restore saved configuration register value */ 844 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 845 } 846 return result; 847 } 848 849 /* Return negative errno on error. */ 850 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 851 unsigned short flags, char read_write, u8 command, 852 int size, union i2c_smbus_data *data) 853 { 854 int hwpec; 855 int block = 0; 856 int ret = 0, xact = 0; 857 struct i801_priv *priv = i2c_get_adapdata(adap); 858 859 mutex_lock(&priv->acpi_lock); 860 if (priv->acpi_reserved) { 861 mutex_unlock(&priv->acpi_lock); 862 return -EBUSY; 863 } 864 865 pm_runtime_get_sync(&priv->pci_dev->dev); 866 867 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 868 && size != I2C_SMBUS_QUICK 869 && size != I2C_SMBUS_I2C_BLOCK_DATA; 870 871 switch (size) { 872 case I2C_SMBUS_QUICK: 873 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 874 SMBHSTADD(priv)); 875 xact = I801_QUICK; 876 break; 877 case I2C_SMBUS_BYTE: 878 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 879 SMBHSTADD(priv)); 880 if (read_write == I2C_SMBUS_WRITE) 881 outb_p(command, SMBHSTCMD(priv)); 882 xact = I801_BYTE; 883 break; 884 case I2C_SMBUS_BYTE_DATA: 885 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 886 SMBHSTADD(priv)); 887 outb_p(command, SMBHSTCMD(priv)); 888 if (read_write == I2C_SMBUS_WRITE) 889 outb_p(data->byte, SMBHSTDAT0(priv)); 890 xact = I801_BYTE_DATA; 891 break; 892 case I2C_SMBUS_WORD_DATA: 893 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 894 SMBHSTADD(priv)); 895 outb_p(command, SMBHSTCMD(priv)); 896 if (read_write == I2C_SMBUS_WRITE) { 897 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 898 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 899 } 900 xact = I801_WORD_DATA; 901 break; 902 case I2C_SMBUS_BLOCK_DATA: 903 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 904 SMBHSTADD(priv)); 905 outb_p(command, SMBHSTCMD(priv)); 906 block = 1; 907 break; 908 case I2C_SMBUS_I2C_BLOCK_DATA: 909 /* 910 * NB: page 240 of ICH5 datasheet shows that the R/#W 911 * bit should be cleared here, even when reading. 912 * However if SPD Write Disable is set (Lynx Point and later), 913 * the read will fail if we don't set the R/#W bit. 914 */ 915 outb_p(((addr & 0x7f) << 1) | 916 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 917 (read_write & 0x01) : 0), 918 SMBHSTADD(priv)); 919 if (read_write == I2C_SMBUS_READ) { 920 /* NB: page 240 of ICH5 datasheet also shows 921 * that DATA1 is the cmd field when reading */ 922 outb_p(command, SMBHSTDAT1(priv)); 923 } else 924 outb_p(command, SMBHSTCMD(priv)); 925 block = 1; 926 break; 927 case I2C_SMBUS_BLOCK_PROC_CALL: 928 /* 929 * Bit 0 of the slave address register always indicate a write 930 * command. 931 */ 932 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 933 outb_p(command, SMBHSTCMD(priv)); 934 block = 1; 935 break; 936 default: 937 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 938 size); 939 ret = -EOPNOTSUPP; 940 goto out; 941 } 942 943 if (hwpec) /* enable/disable hardware PEC */ 944 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 945 else 946 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 947 SMBAUXCTL(priv)); 948 949 if (block) 950 ret = i801_block_transaction(priv, data, read_write, size, 951 hwpec); 952 else 953 ret = i801_transaction(priv, xact); 954 955 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 956 time, so we forcibly disable it after every transaction. Turn off 957 E32B for the same reason. */ 958 if (hwpec || block) 959 outb_p(inb_p(SMBAUXCTL(priv)) & 960 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 961 962 if (block) 963 goto out; 964 if (ret) 965 goto out; 966 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 967 goto out; 968 969 switch (xact & 0x7f) { 970 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 971 case I801_BYTE_DATA: 972 data->byte = inb_p(SMBHSTDAT0(priv)); 973 break; 974 case I801_WORD_DATA: 975 data->word = inb_p(SMBHSTDAT0(priv)) + 976 (inb_p(SMBHSTDAT1(priv)) << 8); 977 break; 978 } 979 980 out: 981 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 982 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 983 mutex_unlock(&priv->acpi_lock); 984 return ret; 985 } 986 987 988 static u32 i801_func(struct i2c_adapter *adapter) 989 { 990 struct i801_priv *priv = i2c_get_adapdata(adapter); 991 992 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 993 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 994 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 995 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 996 ((priv->features & FEATURE_BLOCK_PROC) ? 997 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 998 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 999 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 1000 ((priv->features & FEATURE_HOST_NOTIFY) ? 1001 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 1002 } 1003 1004 static void i801_enable_host_notify(struct i2c_adapter *adapter) 1005 { 1006 struct i801_priv *priv = i2c_get_adapdata(adapter); 1007 1008 if (!(priv->features & FEATURE_HOST_NOTIFY)) 1009 return; 1010 1011 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 1012 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 1013 SMBSLVCMD(priv)); 1014 1015 /* clear Host Notify bit to allow a new notification */ 1016 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 1017 } 1018 1019 static void i801_disable_host_notify(struct i801_priv *priv) 1020 { 1021 if (!(priv->features & FEATURE_HOST_NOTIFY)) 1022 return; 1023 1024 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 1025 } 1026 1027 static const struct i2c_algorithm smbus_algorithm = { 1028 .smbus_xfer = i801_access, 1029 .functionality = i801_func, 1030 }; 1031 1032 static const struct pci_device_id i801_ids[] = { 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) }, 1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1075 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1076 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1077 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1078 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1079 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1080 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1081 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, 1082 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) }, 1083 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) }, 1084 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) }, 1085 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) }, 1086 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) }, 1087 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) }, 1088 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) }, 1089 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS) }, 1090 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS) }, 1091 { 0, } 1092 }; 1093 1094 MODULE_DEVICE_TABLE(pci, i801_ids); 1095 1096 #if defined CONFIG_X86 && defined CONFIG_DMI 1097 static unsigned char apanel_addr; 1098 1099 /* Scan the system ROM for the signature "FJKEYINF" */ 1100 static __init const void __iomem *bios_signature(const void __iomem *bios) 1101 { 1102 ssize_t offset; 1103 const unsigned char signature[] = "FJKEYINF"; 1104 1105 for (offset = 0; offset < 0x10000; offset += 0x10) { 1106 if (check_signature(bios + offset, signature, 1107 sizeof(signature)-1)) 1108 return bios + offset; 1109 } 1110 return NULL; 1111 } 1112 1113 static void __init input_apanel_init(void) 1114 { 1115 void __iomem *bios; 1116 const void __iomem *p; 1117 1118 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1119 p = bios_signature(bios); 1120 if (p) { 1121 /* just use the first address */ 1122 apanel_addr = readb(p + 8 + 3) >> 1; 1123 } 1124 iounmap(bios); 1125 } 1126 1127 struct dmi_onboard_device_info { 1128 const char *name; 1129 u8 type; 1130 unsigned short i2c_addr; 1131 const char *i2c_type; 1132 }; 1133 1134 static const struct dmi_onboard_device_info dmi_devices[] = { 1135 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1136 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1137 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1138 }; 1139 1140 static void dmi_check_onboard_device(u8 type, const char *name, 1141 struct i2c_adapter *adap) 1142 { 1143 int i; 1144 struct i2c_board_info info; 1145 1146 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1147 /* & ~0x80, ignore enabled/disabled bit */ 1148 if ((type & ~0x80) != dmi_devices[i].type) 1149 continue; 1150 if (strcasecmp(name, dmi_devices[i].name)) 1151 continue; 1152 1153 memset(&info, 0, sizeof(struct i2c_board_info)); 1154 info.addr = dmi_devices[i].i2c_addr; 1155 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1156 i2c_new_client_device(adap, &info); 1157 break; 1158 } 1159 } 1160 1161 /* We use our own function to check for onboard devices instead of 1162 dmi_find_device() as some buggy BIOS's have the devices we are interested 1163 in marked as disabled */ 1164 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1165 { 1166 int i, count; 1167 1168 if (dm->type != 10) 1169 return; 1170 1171 count = (dm->length - sizeof(struct dmi_header)) / 2; 1172 for (i = 0; i < count; i++) { 1173 const u8 *d = (char *)(dm + 1) + (i * 2); 1174 const char *name = ((char *) dm) + dm->length; 1175 u8 type = d[0]; 1176 u8 s = d[1]; 1177 1178 if (!s) 1179 continue; 1180 s--; 1181 while (s > 0 && name[0]) { 1182 name += strlen(name) + 1; 1183 s--; 1184 } 1185 if (name[0] == 0) /* Bogus string reference */ 1186 continue; 1187 1188 dmi_check_onboard_device(type, name, adap); 1189 } 1190 } 1191 1192 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1193 static const char *const acpi_smo8800_ids[] = { 1194 "SMO8800", 1195 "SMO8801", 1196 "SMO8810", 1197 "SMO8811", 1198 "SMO8820", 1199 "SMO8821", 1200 "SMO8830", 1201 "SMO8831", 1202 }; 1203 1204 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1205 u32 nesting_level, 1206 void *context, 1207 void **return_value) 1208 { 1209 struct acpi_device_info *info; 1210 acpi_status status; 1211 char *hid; 1212 int i; 1213 1214 status = acpi_get_object_info(obj_handle, &info); 1215 if (ACPI_FAILURE(status)) 1216 return AE_OK; 1217 1218 if (!(info->valid & ACPI_VALID_HID)) 1219 goto smo88xx_not_found; 1220 1221 hid = info->hardware_id.string; 1222 if (!hid) 1223 goto smo88xx_not_found; 1224 1225 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1226 if (i < 0) 1227 goto smo88xx_not_found; 1228 1229 kfree(info); 1230 1231 *((bool *)return_value) = true; 1232 return AE_CTRL_TERMINATE; 1233 1234 smo88xx_not_found: 1235 kfree(info); 1236 return AE_OK; 1237 } 1238 1239 static bool is_dell_system_with_lis3lv02d(void) 1240 { 1241 bool found; 1242 const char *vendor; 1243 1244 vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1245 if (!vendor || strcmp(vendor, "Dell Inc.")) 1246 return false; 1247 1248 /* 1249 * Check that ACPI device SMO88xx is present and is functioning. 1250 * Function acpi_get_devices() already filters all ACPI devices 1251 * which are not present or are not functioning. 1252 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1253 * accelerometer but unfortunately ACPI does not provide any other 1254 * information (like I2C address). 1255 */ 1256 found = false; 1257 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, 1258 (void **)&found); 1259 1260 return found; 1261 } 1262 1263 /* 1264 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1265 * so it is needed to define mapping table based on DMI product names. 1266 */ 1267 static const struct { 1268 const char *dmi_product_name; 1269 unsigned short i2c_addr; 1270 } dell_lis3lv02d_devices[] = { 1271 /* 1272 * Dell platform team told us that these Latitude devices have 1273 * ST microelectronics accelerometer at I2C address 0x29. 1274 */ 1275 { "Latitude E5250", 0x29 }, 1276 { "Latitude E5450", 0x29 }, 1277 { "Latitude E5550", 0x29 }, 1278 { "Latitude E6440", 0x29 }, 1279 { "Latitude E6440 ATG", 0x29 }, 1280 { "Latitude E6540", 0x29 }, 1281 /* 1282 * Additional individual entries were added after verification. 1283 */ 1284 { "Latitude 5480", 0x29 }, 1285 { "Vostro V131", 0x1d }, 1286 }; 1287 1288 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1289 { 1290 struct i2c_board_info info; 1291 const char *dmi_product_name; 1292 int i; 1293 1294 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1295 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1296 if (strcmp(dmi_product_name, 1297 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1298 break; 1299 } 1300 1301 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1302 dev_warn(&priv->pci_dev->dev, 1303 "Accelerometer lis3lv02d is present on SMBus but its" 1304 " address is unknown, skipping registration\n"); 1305 return; 1306 } 1307 1308 memset(&info, 0, sizeof(struct i2c_board_info)); 1309 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1310 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1311 i2c_new_client_device(&priv->adapter, &info); 1312 } 1313 1314 /* Register optional slaves */ 1315 static void i801_probe_optional_slaves(struct i801_priv *priv) 1316 { 1317 /* Only register slaves on main SMBus channel */ 1318 if (priv->features & FEATURE_IDF) 1319 return; 1320 1321 if (apanel_addr) { 1322 struct i2c_board_info info; 1323 1324 memset(&info, 0, sizeof(struct i2c_board_info)); 1325 info.addr = apanel_addr; 1326 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1327 i2c_new_client_device(&priv->adapter, &info); 1328 } 1329 1330 if (dmi_name_in_vendors("FUJITSU")) 1331 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1332 1333 if (is_dell_system_with_lis3lv02d()) 1334 register_dell_lis3lv02d_i2c_device(priv); 1335 1336 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1337 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1338 if (!priv->mux_drvdata) 1339 #endif 1340 i2c_register_spd(&priv->adapter); 1341 } 1342 #else 1343 static void __init input_apanel_init(void) {} 1344 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1345 #endif /* CONFIG_X86 && CONFIG_DMI */ 1346 1347 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1348 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1349 .gpio_chip = "gpio_ich", 1350 .values = { 0x02, 0x03 }, 1351 .n_values = 2, 1352 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1353 .gpios = { 52, 53 }, 1354 .n_gpios = 2, 1355 }; 1356 1357 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1358 .gpio_chip = "gpio_ich", 1359 .values = { 0x02, 0x03, 0x01 }, 1360 .n_values = 3, 1361 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1362 .gpios = { 52, 53 }, 1363 .n_gpios = 2, 1364 }; 1365 1366 static const struct dmi_system_id mux_dmi_table[] = { 1367 { 1368 .matches = { 1369 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1370 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1371 }, 1372 .driver_data = &i801_mux_config_asus_z8_d12, 1373 }, 1374 { 1375 .matches = { 1376 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1377 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1378 }, 1379 .driver_data = &i801_mux_config_asus_z8_d12, 1380 }, 1381 { 1382 .matches = { 1383 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1384 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1385 }, 1386 .driver_data = &i801_mux_config_asus_z8_d12, 1387 }, 1388 { 1389 .matches = { 1390 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1391 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1392 }, 1393 .driver_data = &i801_mux_config_asus_z8_d12, 1394 }, 1395 { 1396 .matches = { 1397 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1398 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1399 }, 1400 .driver_data = &i801_mux_config_asus_z8_d12, 1401 }, 1402 { 1403 .matches = { 1404 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1405 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1406 }, 1407 .driver_data = &i801_mux_config_asus_z8_d12, 1408 }, 1409 { 1410 .matches = { 1411 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1412 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1413 }, 1414 .driver_data = &i801_mux_config_asus_z8_d18, 1415 }, 1416 { 1417 .matches = { 1418 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1419 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1420 }, 1421 .driver_data = &i801_mux_config_asus_z8_d18, 1422 }, 1423 { 1424 .matches = { 1425 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1426 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1427 }, 1428 .driver_data = &i801_mux_config_asus_z8_d12, 1429 }, 1430 { } 1431 }; 1432 1433 /* Setup multiplexing if needed */ 1434 static int i801_add_mux(struct i801_priv *priv) 1435 { 1436 struct device *dev = &priv->adapter.dev; 1437 const struct i801_mux_config *mux_config; 1438 struct i2c_mux_gpio_platform_data gpio_data; 1439 struct gpiod_lookup_table *lookup; 1440 int i; 1441 1442 if (!priv->mux_drvdata) 1443 return 0; 1444 mux_config = priv->mux_drvdata; 1445 1446 /* Prepare the platform data */ 1447 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1448 gpio_data.parent = priv->adapter.nr; 1449 gpio_data.values = mux_config->values; 1450 gpio_data.n_values = mux_config->n_values; 1451 gpio_data.classes = mux_config->classes; 1452 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1453 1454 /* Register GPIO descriptor lookup table */ 1455 lookup = devm_kzalloc(dev, 1456 struct_size(lookup, table, mux_config->n_gpios + 1), 1457 GFP_KERNEL); 1458 if (!lookup) 1459 return -ENOMEM; 1460 lookup->dev_id = "i2c-mux-gpio"; 1461 for (i = 0; i < mux_config->n_gpios; i++) { 1462 lookup->table[i] = (struct gpiod_lookup) 1463 GPIO_LOOKUP(mux_config->gpio_chip, 1464 mux_config->gpios[i], "mux", 0); 1465 } 1466 gpiod_add_lookup_table(lookup); 1467 priv->lookup = lookup; 1468 1469 /* 1470 * Register the mux device, we use PLATFORM_DEVID_NONE here 1471 * because since we are referring to the GPIO chip by name we are 1472 * anyways in deep trouble if there is more than one of these 1473 * devices, and there should likely only be one platform controller 1474 * hub. 1475 */ 1476 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1477 PLATFORM_DEVID_NONE, &gpio_data, 1478 sizeof(struct i2c_mux_gpio_platform_data)); 1479 if (IS_ERR(priv->mux_pdev)) { 1480 gpiod_remove_lookup_table(lookup); 1481 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1482 } 1483 1484 return PTR_ERR_OR_ZERO(priv->mux_pdev); 1485 } 1486 1487 static void i801_del_mux(struct i801_priv *priv) 1488 { 1489 platform_device_unregister(priv->mux_pdev); 1490 gpiod_remove_lookup_table(priv->lookup); 1491 } 1492 1493 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1494 { 1495 const struct dmi_system_id *id; 1496 const struct i801_mux_config *mux_config; 1497 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1498 int i; 1499 1500 id = dmi_first_match(mux_dmi_table); 1501 if (id) { 1502 /* Remove branch classes from trunk */ 1503 mux_config = id->driver_data; 1504 for (i = 0; i < mux_config->n_values; i++) 1505 class &= ~mux_config->classes[i]; 1506 1507 /* Remember for later */ 1508 priv->mux_drvdata = mux_config; 1509 } 1510 1511 return class; 1512 } 1513 #else 1514 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1515 static inline void i801_del_mux(struct i801_priv *priv) { } 1516 1517 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1518 { 1519 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1520 } 1521 #endif 1522 1523 static const struct itco_wdt_platform_data spt_tco_platform_data = { 1524 .name = "Intel PCH", 1525 .version = 4, 1526 }; 1527 1528 static DEFINE_SPINLOCK(p2sb_spinlock); 1529 1530 static struct platform_device * 1531 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1532 struct resource *tco_res) 1533 { 1534 struct resource *res; 1535 unsigned int devfn; 1536 u64 base64_addr; 1537 u32 base_addr; 1538 u8 hidden; 1539 1540 /* 1541 * We must access the NO_REBOOT bit over the Primary to Sideband 1542 * bridge (P2SB). The BIOS prevents the P2SB device from being 1543 * enumerated by the PCI subsystem, so we need to unhide/hide it 1544 * to lookup the P2SB BAR. 1545 */ 1546 spin_lock(&p2sb_spinlock); 1547 1548 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1549 1550 /* Unhide the P2SB device, if it is hidden */ 1551 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1552 if (hidden) 1553 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1554 1555 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1556 base64_addr = base_addr & 0xfffffff0; 1557 1558 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1559 base64_addr |= (u64)base_addr << 32; 1560 1561 /* Hide the P2SB device, if it was hidden before */ 1562 if (hidden) 1563 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1564 spin_unlock(&p2sb_spinlock); 1565 1566 res = &tco_res[1]; 1567 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1568 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1569 else 1570 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1571 1572 res->end = res->start + 3; 1573 res->flags = IORESOURCE_MEM; 1574 1575 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1576 tco_res, 2, &spt_tco_platform_data, 1577 sizeof(spt_tco_platform_data)); 1578 } 1579 1580 static const struct itco_wdt_platform_data cnl_tco_platform_data = { 1581 .name = "Intel PCH", 1582 .version = 6, 1583 }; 1584 1585 static struct platform_device * 1586 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1587 struct resource *tco_res) 1588 { 1589 return platform_device_register_resndata(&pci_dev->dev, 1590 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data, 1591 sizeof(cnl_tco_platform_data)); 1592 } 1593 1594 static void i801_add_tco(struct i801_priv *priv) 1595 { 1596 struct pci_dev *pci_dev = priv->pci_dev; 1597 struct resource tco_res[2], *res; 1598 u32 tco_base, tco_ctl; 1599 1600 /* If we have ACPI based watchdog use that instead */ 1601 if (acpi_has_watchdog()) 1602 return; 1603 1604 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1605 return; 1606 1607 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1608 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1609 if (!(tco_ctl & TCOCTL_EN)) 1610 return; 1611 1612 memset(tco_res, 0, sizeof(tco_res)); 1613 /* 1614 * Always populate the main iTCO IO resource here. The second entry 1615 * for NO_REBOOT MMIO is filled by the SPT specific function. 1616 */ 1617 res = &tco_res[0]; 1618 res->start = tco_base & ~1; 1619 res->end = res->start + 32 - 1; 1620 res->flags = IORESOURCE_IO; 1621 1622 if (priv->features & FEATURE_TCO_CNL) 1623 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1624 else 1625 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1626 1627 if (IS_ERR(priv->tco_pdev)) 1628 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1629 } 1630 1631 #ifdef CONFIG_ACPI 1632 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1633 acpi_physical_address address) 1634 { 1635 return address >= priv->smba && 1636 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1637 } 1638 1639 static acpi_status 1640 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1641 u64 *value, void *handler_context, void *region_context) 1642 { 1643 struct i801_priv *priv = handler_context; 1644 struct pci_dev *pdev = priv->pci_dev; 1645 acpi_status status; 1646 1647 /* 1648 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1649 * further access from the driver itself. This device is now owned 1650 * by the system firmware. 1651 */ 1652 mutex_lock(&priv->acpi_lock); 1653 1654 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1655 priv->acpi_reserved = true; 1656 1657 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1658 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1659 1660 /* 1661 * BIOS is accessing the host controller so prevent it from 1662 * suspending automatically from now on. 1663 */ 1664 pm_runtime_get_sync(&pdev->dev); 1665 } 1666 1667 if ((function & ACPI_IO_MASK) == ACPI_READ) 1668 status = acpi_os_read_port(address, (u32 *)value, bits); 1669 else 1670 status = acpi_os_write_port(address, (u32)*value, bits); 1671 1672 mutex_unlock(&priv->acpi_lock); 1673 1674 return status; 1675 } 1676 1677 static int i801_acpi_probe(struct i801_priv *priv) 1678 { 1679 struct acpi_device *adev; 1680 acpi_status status; 1681 1682 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1683 if (adev) { 1684 status = acpi_install_address_space_handler(adev->handle, 1685 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1686 NULL, priv); 1687 if (ACPI_SUCCESS(status)) 1688 return 0; 1689 } 1690 1691 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1692 } 1693 1694 static void i801_acpi_remove(struct i801_priv *priv) 1695 { 1696 struct acpi_device *adev; 1697 1698 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1699 if (!adev) 1700 return; 1701 1702 acpi_remove_address_space_handler(adev->handle, 1703 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1704 1705 mutex_lock(&priv->acpi_lock); 1706 if (priv->acpi_reserved) 1707 pm_runtime_put(&priv->pci_dev->dev); 1708 mutex_unlock(&priv->acpi_lock); 1709 } 1710 #else 1711 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1712 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1713 #endif 1714 1715 static unsigned char i801_setup_hstcfg(struct i801_priv *priv) 1716 { 1717 unsigned char hstcfg = priv->original_hstcfg; 1718 1719 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1720 hstcfg |= SMBHSTCFG_HST_EN; 1721 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1722 return hstcfg; 1723 } 1724 1725 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1726 { 1727 unsigned char temp; 1728 int err, i; 1729 struct i801_priv *priv; 1730 1731 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1732 if (!priv) 1733 return -ENOMEM; 1734 1735 i2c_set_adapdata(&priv->adapter, priv); 1736 priv->adapter.owner = THIS_MODULE; 1737 priv->adapter.class = i801_get_adapter_class(priv); 1738 priv->adapter.algo = &smbus_algorithm; 1739 priv->adapter.dev.parent = &dev->dev; 1740 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1741 priv->adapter.retries = 3; 1742 mutex_init(&priv->acpi_lock); 1743 1744 priv->pci_dev = dev; 1745 switch (dev->device) { 1746 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1747 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1748 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1749 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1750 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1751 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1752 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS: 1753 priv->features |= FEATURE_BLOCK_PROC; 1754 priv->features |= FEATURE_I2C_BLOCK_READ; 1755 priv->features |= FEATURE_IRQ; 1756 priv->features |= FEATURE_SMBUS_PEC; 1757 priv->features |= FEATURE_BLOCK_BUFFER; 1758 priv->features |= FEATURE_TCO_SPT; 1759 priv->features |= FEATURE_HOST_NOTIFY; 1760 break; 1761 1762 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1763 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1764 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1765 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1766 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: 1767 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS: 1768 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS: 1769 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS: 1770 case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS: 1771 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS: 1772 case PCI_DEVICE_ID_INTEL_EBG_SMBUS: 1773 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS: 1774 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS: 1775 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS: 1776 priv->features |= FEATURE_BLOCK_PROC; 1777 priv->features |= FEATURE_I2C_BLOCK_READ; 1778 priv->features |= FEATURE_IRQ; 1779 priv->features |= FEATURE_SMBUS_PEC; 1780 priv->features |= FEATURE_BLOCK_BUFFER; 1781 priv->features |= FEATURE_TCO_CNL; 1782 priv->features |= FEATURE_HOST_NOTIFY; 1783 break; 1784 1785 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1786 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1787 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1788 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1789 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1790 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1791 priv->features |= FEATURE_IDF; 1792 fallthrough; 1793 default: 1794 priv->features |= FEATURE_BLOCK_PROC; 1795 priv->features |= FEATURE_I2C_BLOCK_READ; 1796 priv->features |= FEATURE_IRQ; 1797 fallthrough; 1798 case PCI_DEVICE_ID_INTEL_82801DB_3: 1799 priv->features |= FEATURE_SMBUS_PEC; 1800 priv->features |= FEATURE_BLOCK_BUFFER; 1801 fallthrough; 1802 case PCI_DEVICE_ID_INTEL_82801CA_3: 1803 priv->features |= FEATURE_HOST_NOTIFY; 1804 fallthrough; 1805 case PCI_DEVICE_ID_INTEL_82801BA_2: 1806 case PCI_DEVICE_ID_INTEL_82801AB_3: 1807 case PCI_DEVICE_ID_INTEL_82801AA_3: 1808 break; 1809 } 1810 1811 /* Disable features on user request */ 1812 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1813 if (priv->features & disable_features & (1 << i)) 1814 dev_notice(&dev->dev, "%s disabled by user\n", 1815 i801_feature_names[i]); 1816 } 1817 priv->features &= ~disable_features; 1818 1819 err = pcim_enable_device(dev); 1820 if (err) { 1821 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1822 err); 1823 return err; 1824 } 1825 pcim_pin_device(dev); 1826 1827 /* Determine the address of the SMBus area */ 1828 priv->smba = pci_resource_start(dev, SMBBAR); 1829 if (!priv->smba) { 1830 dev_err(&dev->dev, 1831 "SMBus base address uninitialized, upgrade BIOS\n"); 1832 return -ENODEV; 1833 } 1834 1835 if (i801_acpi_probe(priv)) 1836 return -ENODEV; 1837 1838 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1839 dev_driver_string(&dev->dev)); 1840 if (err) { 1841 dev_err(&dev->dev, 1842 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1843 priv->smba, 1844 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1845 i801_acpi_remove(priv); 1846 return err; 1847 } 1848 1849 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1850 temp = i801_setup_hstcfg(priv); 1851 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1852 dev_info(&dev->dev, "Enabling SMBus device\n"); 1853 1854 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1855 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1856 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1857 priv->features &= ~FEATURE_IRQ; 1858 } 1859 if (temp & SMBHSTCFG_SPD_WD) 1860 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1861 1862 /* Clear special mode bits */ 1863 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1864 outb_p(inb_p(SMBAUXCTL(priv)) & 1865 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1866 1867 /* Remember original Host Notify setting */ 1868 if (priv->features & FEATURE_HOST_NOTIFY) 1869 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1870 1871 /* Default timeout in interrupt mode: 200 ms */ 1872 priv->adapter.timeout = HZ / 5; 1873 1874 if (dev->irq == IRQ_NOTCONNECTED) 1875 priv->features &= ~FEATURE_IRQ; 1876 1877 if (priv->features & FEATURE_IRQ) { 1878 u16 pcictl, pcists; 1879 1880 /* Complain if an interrupt is already pending */ 1881 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1882 if (pcists & SMBPCISTS_INTS) 1883 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1884 1885 /* Check if interrupts have been disabled */ 1886 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1887 if (pcictl & SMBPCICTL_INTDIS) { 1888 dev_info(&dev->dev, "Interrupts are disabled\n"); 1889 priv->features &= ~FEATURE_IRQ; 1890 } 1891 } 1892 1893 if (priv->features & FEATURE_IRQ) { 1894 init_waitqueue_head(&priv->waitq); 1895 1896 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1897 IRQF_SHARED, 1898 dev_driver_string(&dev->dev), priv); 1899 if (err) { 1900 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1901 dev->irq, err); 1902 priv->features &= ~FEATURE_IRQ; 1903 } 1904 } 1905 dev_info(&dev->dev, "SMBus using %s\n", 1906 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1907 1908 i801_add_tco(priv); 1909 1910 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1911 "SMBus I801 adapter at %04lx", priv->smba); 1912 err = i2c_add_adapter(&priv->adapter); 1913 if (err) { 1914 i801_acpi_remove(priv); 1915 return err; 1916 } 1917 1918 i801_enable_host_notify(&priv->adapter); 1919 1920 i801_probe_optional_slaves(priv); 1921 /* We ignore errors - multiplexing is optional */ 1922 i801_add_mux(priv); 1923 1924 pci_set_drvdata(dev, priv); 1925 1926 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1927 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1928 pm_runtime_use_autosuspend(&dev->dev); 1929 pm_runtime_put_autosuspend(&dev->dev); 1930 pm_runtime_allow(&dev->dev); 1931 1932 return 0; 1933 } 1934 1935 static void i801_remove(struct pci_dev *dev) 1936 { 1937 struct i801_priv *priv = pci_get_drvdata(dev); 1938 1939 pm_runtime_forbid(&dev->dev); 1940 pm_runtime_get_noresume(&dev->dev); 1941 1942 i801_disable_host_notify(priv); 1943 i801_del_mux(priv); 1944 i2c_del_adapter(&priv->adapter); 1945 i801_acpi_remove(priv); 1946 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1947 1948 platform_device_unregister(priv->tco_pdev); 1949 1950 /* 1951 * do not call pci_disable_device(dev) since it can cause hard hangs on 1952 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1953 */ 1954 } 1955 1956 static void i801_shutdown(struct pci_dev *dev) 1957 { 1958 struct i801_priv *priv = pci_get_drvdata(dev); 1959 1960 /* Restore config registers to avoid hard hang on some systems */ 1961 i801_disable_host_notify(priv); 1962 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1963 } 1964 1965 #ifdef CONFIG_PM_SLEEP 1966 static int i801_suspend(struct device *dev) 1967 { 1968 struct i801_priv *priv = dev_get_drvdata(dev); 1969 1970 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1971 return 0; 1972 } 1973 1974 static int i801_resume(struct device *dev) 1975 { 1976 struct i801_priv *priv = dev_get_drvdata(dev); 1977 1978 i801_setup_hstcfg(priv); 1979 i801_enable_host_notify(&priv->adapter); 1980 1981 return 0; 1982 } 1983 #endif 1984 1985 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1986 1987 static struct pci_driver i801_driver = { 1988 .name = "i801_smbus", 1989 .id_table = i801_ids, 1990 .probe = i801_probe, 1991 .remove = i801_remove, 1992 .shutdown = i801_shutdown, 1993 .driver = { 1994 .pm = &i801_pm_ops, 1995 }, 1996 }; 1997 1998 static int __init i2c_i801_init(void) 1999 { 2000 if (dmi_name_in_vendors("FUJITSU")) 2001 input_apanel_init(); 2002 return pci_register_driver(&i801_driver); 2003 } 2004 2005 static void __exit i2c_i801_exit(void) 2006 { 2007 pci_unregister_driver(&i801_driver); 2008 } 2009 2010 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 2011 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 2012 MODULE_DESCRIPTION("I801 SMBus driver"); 2013 MODULE_LICENSE("GPL"); 2014 2015 module_init(i2c_i801_init); 2016 module_exit(i2c_i801_exit); 2017