1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes 68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes 79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes 80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes 81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes 82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes 83 * 84 * Features supported by this driver: 85 * Software PEC no 86 * Hardware PEC yes 87 * Block buffer yes 88 * Block process call transaction yes 89 * I2C block read transaction yes (doesn't use the block buffer) 90 * Slave mode no 91 * SMBus Host Notify yes 92 * Interrupt processing yes 93 * 94 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 95 */ 96 97 #define DRV_NAME "i801_smbus" 98 99 #include <linux/interrupt.h> 100 #include <linux/module.h> 101 #include <linux/pci.h> 102 #include <linux/kernel.h> 103 #include <linux/stddef.h> 104 #include <linux/delay.h> 105 #include <linux/ioport.h> 106 #include <linux/init.h> 107 #include <linux/i2c.h> 108 #include <linux/i2c-smbus.h> 109 #include <linux/acpi.h> 110 #include <linux/io.h> 111 #include <linux/dmi.h> 112 #include <linux/slab.h> 113 #include <linux/string.h> 114 #include <linux/completion.h> 115 #include <linux/err.h> 116 #include <linux/platform_device.h> 117 #include <linux/platform_data/itco_wdt.h> 118 #include <linux/platform_data/x86/p2sb.h> 119 #include <linux/pm_runtime.h> 120 #include <linux/mutex.h> 121 122 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 123 #include <linux/gpio/machine.h> 124 #include <linux/platform_data/i2c-mux-gpio.h> 125 #endif 126 127 /* I801 SMBus address offsets */ 128 #define SMBHSTSTS(p) (0 + (p)->smba) 129 #define SMBHSTCNT(p) (2 + (p)->smba) 130 #define SMBHSTCMD(p) (3 + (p)->smba) 131 #define SMBHSTADD(p) (4 + (p)->smba) 132 #define SMBHSTDAT0(p) (5 + (p)->smba) 133 #define SMBHSTDAT1(p) (6 + (p)->smba) 134 #define SMBBLKDAT(p) (7 + (p)->smba) 135 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 136 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 137 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 138 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 139 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 140 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 141 142 /* PCI Address Constants */ 143 #define SMBBAR 4 144 #define SMBHSTCFG 0x040 145 #define TCOBASE 0x050 146 #define TCOCTL 0x054 147 148 #define SBREG_SMBCTRL 0xc6000c 149 #define SBREG_SMBCTRL_DNV 0xcf000c 150 151 /* Host configuration bits for SMBHSTCFG */ 152 #define SMBHSTCFG_HST_EN BIT(0) 153 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 154 #define SMBHSTCFG_I2C_EN BIT(2) 155 #define SMBHSTCFG_SPD_WD BIT(4) 156 157 /* TCO configuration bits for TCOCTL */ 158 #define TCOCTL_EN BIT(8) 159 160 /* Auxiliary status register bits, ICH4+ only */ 161 #define SMBAUXSTS_CRCE BIT(0) 162 #define SMBAUXSTS_STCO BIT(1) 163 164 /* Auxiliary control register bits, ICH4+ only */ 165 #define SMBAUXCTL_CRC BIT(0) 166 #define SMBAUXCTL_E32B BIT(1) 167 168 /* I801 command constants */ 169 #define I801_QUICK 0x00 170 #define I801_BYTE 0x04 171 #define I801_BYTE_DATA 0x08 172 #define I801_WORD_DATA 0x0C 173 #define I801_PROC_CALL 0x10 174 #define I801_BLOCK_DATA 0x14 175 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 176 #define I801_BLOCK_PROC_CALL 0x1C 177 178 /* I801 Host Control register bits */ 179 #define SMBHSTCNT_INTREN BIT(0) 180 #define SMBHSTCNT_KILL BIT(1) 181 #define SMBHSTCNT_LAST_BYTE BIT(5) 182 #define SMBHSTCNT_START BIT(6) 183 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 184 185 /* I801 Hosts Status register bits */ 186 #define SMBHSTSTS_BYTE_DONE BIT(7) 187 #define SMBHSTSTS_INUSE_STS BIT(6) 188 #define SMBHSTSTS_SMBALERT_STS BIT(5) 189 #define SMBHSTSTS_FAILED BIT(4) 190 #define SMBHSTSTS_BUS_ERR BIT(3) 191 #define SMBHSTSTS_DEV_ERR BIT(2) 192 #define SMBHSTSTS_INTR BIT(1) 193 #define SMBHSTSTS_HOST_BUSY BIT(0) 194 195 /* Host Notify Status register bits */ 196 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 197 198 /* Host Notify Command register bits */ 199 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2) 200 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 201 202 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 203 SMBHSTSTS_DEV_ERR) 204 205 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 206 STATUS_ERROR_FLAGS) 207 208 #define SMBUS_LEN_SENTINEL (I2C_SMBUS_BLOCK_MAX + 1) 209 210 /* Older devices have their ID defined in <linux/pci_ids.h> */ 211 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 212 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 213 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 214 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 215 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 216 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 217 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 219 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 220 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 221 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 222 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 223 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 224 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 225 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 226 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 227 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 228 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 229 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 230 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3 231 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 232 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 233 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 234 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 235 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 236 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 237 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796 238 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 239 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23 240 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 241 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22 242 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23 243 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 244 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 245 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 246 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 247 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 248 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 249 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 250 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 251 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 252 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 253 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 254 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 255 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 256 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 257 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 258 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 259 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 260 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22 261 262 struct i801_mux_config { 263 char *gpio_chip; 264 unsigned values[3]; 265 int n_values; 266 unsigned classes[3]; 267 unsigned gpios[2]; /* Relative to gpio_chip->base */ 268 int n_gpios; 269 }; 270 271 struct i801_priv { 272 struct i2c_adapter adapter; 273 unsigned long smba; 274 unsigned char original_hstcfg; 275 unsigned char original_hstcnt; 276 unsigned char original_slvcmd; 277 struct pci_dev *pci_dev; 278 unsigned int features; 279 280 /* isr processing */ 281 struct completion done; 282 u8 status; 283 284 /* Command state used by isr for byte-by-byte block transactions */ 285 u8 cmd; 286 bool is_read; 287 int count; 288 int len; 289 u8 *data; 290 291 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 292 struct platform_device *mux_pdev; 293 struct gpiod_lookup_table *lookup; 294 #endif 295 struct platform_device *tco_pdev; 296 297 /* 298 * If set to true the host controller registers are reserved for 299 * ACPI AML use. 300 */ 301 bool acpi_reserved; 302 }; 303 304 #define FEATURE_SMBUS_PEC BIT(0) 305 #define FEATURE_BLOCK_BUFFER BIT(1) 306 #define FEATURE_BLOCK_PROC BIT(2) 307 #define FEATURE_I2C_BLOCK_READ BIT(3) 308 #define FEATURE_IRQ BIT(4) 309 #define FEATURE_HOST_NOTIFY BIT(5) 310 /* Not really a feature, but it's convenient to handle it as such */ 311 #define FEATURE_IDF BIT(15) 312 #define FEATURE_TCO_SPT BIT(16) 313 #define FEATURE_TCO_CNL BIT(17) 314 315 static const char *i801_feature_names[] = { 316 "SMBus PEC", 317 "Block buffer", 318 "Block process call", 319 "I2C block read", 320 "Interrupt", 321 "SMBus Host Notify", 322 }; 323 324 static unsigned int disable_features; 325 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 326 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 327 "\t\t 0x01 disable SMBus PEC\n" 328 "\t\t 0x02 disable the block buffer\n" 329 "\t\t 0x08 disable the I2C block read functionality\n" 330 "\t\t 0x10 don't use interrupts\n" 331 "\t\t 0x20 disable SMBus Host Notify "); 332 333 static int i801_get_block_len(struct i801_priv *priv) 334 { 335 u8 len = inb_p(SMBHSTDAT0(priv)); 336 337 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 338 pci_err(priv->pci_dev, "Illegal SMBus block read size %u\n", len); 339 return -EPROTO; 340 } 341 342 return len; 343 } 344 345 static int i801_check_and_clear_pec_error(struct i801_priv *priv) 346 { 347 u8 status; 348 349 if (!(priv->features & FEATURE_SMBUS_PEC)) 350 return 0; 351 352 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 353 if (status) { 354 outb_p(status, SMBAUXSTS(priv)); 355 return -EBADMSG; 356 } 357 358 return 0; 359 } 360 361 /* Make sure the SMBus host is ready to start transmitting. 362 Return 0 if it is, -EBUSY if it is not. */ 363 static int i801_check_pre(struct i801_priv *priv) 364 { 365 int status, result; 366 367 status = inb_p(SMBHSTSTS(priv)); 368 if (status & SMBHSTSTS_HOST_BUSY) { 369 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n"); 370 return -EBUSY; 371 } 372 373 status &= STATUS_FLAGS; 374 if (status) { 375 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status); 376 outb_p(status, SMBHSTSTS(priv)); 377 } 378 379 /* 380 * Clear CRC status if needed. 381 * During normal operation, i801_check_post() takes care 382 * of it after every operation. We do it here only in case 383 * the hardware was already in this state when the driver 384 * started. 385 */ 386 result = i801_check_and_clear_pec_error(priv); 387 if (result) 388 pci_dbg(priv->pci_dev, "Clearing aux status flag CRCE\n"); 389 390 return 0; 391 } 392 393 static int i801_check_post(struct i801_priv *priv, int status) 394 { 395 int result = 0; 396 397 /* 398 * If the SMBus is still busy, we give up 399 */ 400 if (unlikely(status < 0)) { 401 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 402 /* try to stop the current command */ 403 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 404 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 405 usleep_range(1000, 2000); 406 outb_p(0, SMBHSTCNT(priv)); 407 408 /* Check if it worked */ 409 status = inb_p(SMBHSTSTS(priv)); 410 if ((status & SMBHSTSTS_HOST_BUSY) || 411 !(status & SMBHSTSTS_FAILED)) 412 dev_err(&priv->pci_dev->dev, 413 "Failed terminating the transaction\n"); 414 return -ETIMEDOUT; 415 } 416 417 if (status & SMBHSTSTS_FAILED) { 418 result = -EIO; 419 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 420 } 421 if (status & SMBHSTSTS_DEV_ERR) { 422 /* 423 * This may be a PEC error, check and clear it. 424 * 425 * AUXSTS is handled differently from HSTSTS. 426 * For HSTSTS, i801_isr() or i801_wait_intr() 427 * has already cleared the error bits in hardware, 428 * and we are passed a copy of the original value 429 * in "status". 430 * For AUXSTS, the hardware register is left 431 * for us to handle here. 432 * This is asymmetric, slightly iffy, but safe, 433 * since all this code is serialized and the CRCE 434 * bit is harmless as long as it's cleared before 435 * the next operation. 436 */ 437 result = i801_check_and_clear_pec_error(priv); 438 if (result) { 439 pci_dbg(priv->pci_dev, "PEC error\n"); 440 } else { 441 result = -ENXIO; 442 pci_dbg(priv->pci_dev, "No response\n"); 443 } 444 } 445 if (status & SMBHSTSTS_BUS_ERR) { 446 result = -EAGAIN; 447 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 448 } 449 450 return result; 451 } 452 453 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 454 static int i801_wait_intr(struct i801_priv *priv) 455 { 456 unsigned long timeout = jiffies + priv->adapter.timeout; 457 int status, busy; 458 459 do { 460 usleep_range(250, 500); 461 status = inb_p(SMBHSTSTS(priv)); 462 busy = status & SMBHSTSTS_HOST_BUSY; 463 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 464 if (!busy && status) 465 return status & STATUS_ERROR_FLAGS; 466 } while (time_is_after_eq_jiffies(timeout)); 467 468 return -ETIMEDOUT; 469 } 470 471 /* Wait for either BYTE_DONE or an error flag being set */ 472 static int i801_wait_byte_done(struct i801_priv *priv) 473 { 474 unsigned long timeout = jiffies + priv->adapter.timeout; 475 int status; 476 477 do { 478 usleep_range(250, 500); 479 status = inb_p(SMBHSTSTS(priv)); 480 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 481 return status & STATUS_ERROR_FLAGS; 482 } while (time_is_after_eq_jiffies(timeout)); 483 484 return -ETIMEDOUT; 485 } 486 487 static int i801_transaction(struct i801_priv *priv, int xact) 488 { 489 unsigned long result; 490 const struct i2c_adapter *adap = &priv->adapter; 491 492 if (priv->features & FEATURE_IRQ) { 493 reinit_completion(&priv->done); 494 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 495 SMBHSTCNT(priv)); 496 result = wait_for_completion_timeout(&priv->done, adap->timeout); 497 return result ? priv->status : -ETIMEDOUT; 498 } 499 500 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 501 502 return i801_wait_intr(priv); 503 } 504 505 static int i801_block_transaction_by_block(struct i801_priv *priv, 506 union i2c_smbus_data *data, 507 char read_write, int command) 508 { 509 int i, len, status, xact; 510 511 switch (command) { 512 case I2C_SMBUS_BLOCK_PROC_CALL: 513 xact = I801_BLOCK_PROC_CALL; 514 break; 515 case I2C_SMBUS_BLOCK_DATA: 516 xact = I801_BLOCK_DATA; 517 break; 518 default: 519 return -EOPNOTSUPP; 520 } 521 522 /* Set block buffer mode */ 523 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 524 525 if (read_write == I2C_SMBUS_WRITE) { 526 len = data->block[0]; 527 outb_p(len, SMBHSTDAT0(priv)); 528 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 529 for (i = 0; i < len; i++) 530 outb_p(data->block[i+1], SMBBLKDAT(priv)); 531 } 532 533 status = i801_transaction(priv, xact); 534 if (status) 535 goto out; 536 537 if (read_write == I2C_SMBUS_READ || 538 command == I2C_SMBUS_BLOCK_PROC_CALL) { 539 status = i801_get_block_len(priv); 540 if (status < 0) 541 goto out; 542 543 len = status; 544 data->block[0] = len; 545 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 546 for (i = 0; i < len; i++) 547 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 548 } 549 out: 550 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv)); 551 return status; 552 } 553 554 static void i801_isr_byte_done(struct i801_priv *priv) 555 { 556 if (priv->is_read) { 557 /* 558 * At transfer start i801_smbus_block_transaction() marks 559 * the block length as invalid. Check for this sentinel value 560 * and read the block length from SMBHSTDAT0. 561 */ 562 if (priv->len == SMBUS_LEN_SENTINEL) { 563 priv->len = i801_get_block_len(priv); 564 if (priv->len < 0) 565 /* FIXME: Recover */ 566 priv->len = I2C_SMBUS_BLOCK_MAX; 567 568 priv->data[-1] = priv->len; 569 } 570 571 /* Read next byte */ 572 if (priv->count < priv->len) 573 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 574 else 575 dev_dbg(&priv->pci_dev->dev, 576 "Discarding extra byte on block read\n"); 577 578 /* Set LAST_BYTE for last byte of read transaction */ 579 if (priv->count == priv->len - 1) 580 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 581 SMBHSTCNT(priv)); 582 } else if (priv->count < priv->len - 1) { 583 /* Write next byte, except for IRQ after last byte */ 584 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 585 } 586 } 587 588 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 589 { 590 unsigned short addr; 591 592 addr = inb_p(SMBNTFDADD(priv)) >> 1; 593 594 /* 595 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 596 * always returns 0. Our current implementation doesn't provide 597 * data, so we just ignore it. 598 */ 599 i2c_handle_smbus_host_notify(&priv->adapter, addr); 600 601 /* clear Host Notify bit and return */ 602 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 603 return IRQ_HANDLED; 604 } 605 606 /* 607 * There are three kinds of interrupts: 608 * 609 * 1) i801 signals transaction completion with one of these interrupts: 610 * INTR - Success 611 * DEV_ERR - Invalid command, NAK or communication timeout 612 * BUS_ERR - SMI# transaction collision 613 * FAILED - transaction was canceled due to a KILL request 614 * When any of these occur, update ->status and signal completion. 615 * 616 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 617 * occurs for each byte of a byte-by-byte to prepare the next byte. 618 * 619 * 3) Host Notify interrupts 620 */ 621 static irqreturn_t i801_isr(int irq, void *dev_id) 622 { 623 struct i801_priv *priv = dev_id; 624 u16 pcists; 625 u8 status; 626 627 /* Confirm this is our interrupt */ 628 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 629 if (!(pcists & PCI_STATUS_INTERRUPT)) 630 return IRQ_NONE; 631 632 if (priv->features & FEATURE_HOST_NOTIFY) { 633 status = inb_p(SMBSLVSTS(priv)); 634 if (status & SMBSLVSTS_HST_NTFY_STS) 635 return i801_host_notify_isr(priv); 636 } 637 638 status = inb_p(SMBHSTSTS(priv)); 639 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE) 640 i801_isr_byte_done(priv); 641 642 /* 643 * Clear IRQ sources: SMB_ALERT status is set after signal assertion 644 * independently of the interrupt generation being blocked or not 645 * so clear it always when the status is set. 646 */ 647 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS; 648 outb_p(status, SMBHSTSTS(priv)); 649 650 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 651 if (status) { 652 priv->status = status & STATUS_ERROR_FLAGS; 653 complete(&priv->done); 654 } 655 656 return IRQ_HANDLED; 657 } 658 659 /* 660 * For "byte-by-byte" block transactions: 661 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 662 * I2C read uses cmd=I801_I2C_BLOCK_DATA 663 */ 664 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 665 union i2c_smbus_data *data, 666 char read_write, int command) 667 { 668 int i, len; 669 int smbcmd; 670 int status; 671 unsigned long result; 672 const struct i2c_adapter *adap = &priv->adapter; 673 674 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 675 return -EOPNOTSUPP; 676 677 len = data->block[0]; 678 679 if (read_write == I2C_SMBUS_WRITE) { 680 outb_p(len, SMBHSTDAT0(priv)); 681 outb_p(data->block[1], SMBBLKDAT(priv)); 682 } 683 684 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 685 read_write == I2C_SMBUS_READ) 686 smbcmd = I801_I2C_BLOCK_DATA; 687 else 688 smbcmd = I801_BLOCK_DATA; 689 690 if (priv->features & FEATURE_IRQ) { 691 priv->is_read = (read_write == I2C_SMBUS_READ); 692 if (len == 1 && priv->is_read) 693 smbcmd |= SMBHSTCNT_LAST_BYTE; 694 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 695 priv->len = len; 696 priv->count = 0; 697 priv->data = &data->block[1]; 698 699 reinit_completion(&priv->done); 700 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 701 result = wait_for_completion_timeout(&priv->done, adap->timeout); 702 return result ? priv->status : -ETIMEDOUT; 703 } 704 705 if (len == 1 && read_write == I2C_SMBUS_READ) 706 smbcmd |= SMBHSTCNT_LAST_BYTE; 707 outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 708 709 for (i = 1; i <= len; i++) { 710 status = i801_wait_byte_done(priv); 711 if (status) 712 return status; 713 714 /* 715 * At transfer start i801_smbus_block_transaction() marks 716 * the block length as invalid. Check for this sentinel value 717 * and read the block length from SMBHSTDAT0. 718 */ 719 if (len == SMBUS_LEN_SENTINEL) { 720 len = i801_get_block_len(priv); 721 if (len < 0) { 722 /* Recover */ 723 while (inb_p(SMBHSTSTS(priv)) & 724 SMBHSTSTS_HOST_BUSY) 725 outb_p(SMBHSTSTS_BYTE_DONE, 726 SMBHSTSTS(priv)); 727 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 728 return -EPROTO; 729 } 730 data->block[0] = len; 731 } 732 733 if (read_write == I2C_SMBUS_READ) { 734 data->block[i] = inb_p(SMBBLKDAT(priv)); 735 if (i == len - 1) 736 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv)); 737 } 738 739 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 740 outb_p(data->block[i+1], SMBBLKDAT(priv)); 741 742 /* signals SMBBLKDAT ready */ 743 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 744 } 745 746 return i801_wait_intr(priv); 747 } 748 749 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write) 750 { 751 outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv)); 752 } 753 754 /* Single value transaction function */ 755 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 756 u8 addr, u8 hstcmd, char read_write, int command) 757 { 758 int xact, ret; 759 760 switch (command) { 761 case I2C_SMBUS_QUICK: 762 i801_set_hstadd(priv, addr, read_write); 763 xact = I801_QUICK; 764 break; 765 case I2C_SMBUS_BYTE: 766 i801_set_hstadd(priv, addr, read_write); 767 if (read_write == I2C_SMBUS_WRITE) 768 outb_p(hstcmd, SMBHSTCMD(priv)); 769 xact = I801_BYTE; 770 break; 771 case I2C_SMBUS_BYTE_DATA: 772 i801_set_hstadd(priv, addr, read_write); 773 if (read_write == I2C_SMBUS_WRITE) 774 outb_p(data->byte, SMBHSTDAT0(priv)); 775 outb_p(hstcmd, SMBHSTCMD(priv)); 776 xact = I801_BYTE_DATA; 777 break; 778 case I2C_SMBUS_WORD_DATA: 779 i801_set_hstadd(priv, addr, read_write); 780 if (read_write == I2C_SMBUS_WRITE) { 781 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 782 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 783 } 784 outb_p(hstcmd, SMBHSTCMD(priv)); 785 xact = I801_WORD_DATA; 786 break; 787 case I2C_SMBUS_PROC_CALL: 788 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 789 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 790 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 791 outb_p(hstcmd, SMBHSTCMD(priv)); 792 read_write = I2C_SMBUS_READ; 793 xact = I801_PROC_CALL; 794 break; 795 default: 796 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command); 797 return -EOPNOTSUPP; 798 } 799 800 ret = i801_transaction(priv, xact); 801 if (ret || read_write == I2C_SMBUS_WRITE) 802 return ret; 803 804 switch (command) { 805 case I2C_SMBUS_BYTE: 806 case I2C_SMBUS_BYTE_DATA: 807 data->byte = inb_p(SMBHSTDAT0(priv)); 808 break; 809 case I2C_SMBUS_WORD_DATA: 810 case I2C_SMBUS_PROC_CALL: 811 data->word = inb_p(SMBHSTDAT0(priv)) + 812 (inb_p(SMBHSTDAT1(priv)) << 8); 813 break; 814 } 815 816 return 0; 817 } 818 819 static int i801_smbus_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 820 u8 addr, u8 hstcmd, char read_write, int command) 821 { 822 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA) 823 /* Mark block length as invalid */ 824 data->block[0] = SMBUS_LEN_SENTINEL; 825 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 826 return -EPROTO; 827 828 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 829 /* Needs to be flagged as write transaction */ 830 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 831 else 832 i801_set_hstadd(priv, addr, read_write); 833 outb_p(hstcmd, SMBHSTCMD(priv)); 834 835 if (priv->features & FEATURE_BLOCK_BUFFER) 836 return i801_block_transaction_by_block(priv, data, read_write, command); 837 else 838 return i801_block_transaction_byte_by_byte(priv, data, read_write, command); 839 } 840 841 static int i801_i2c_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 842 u8 addr, u8 hstcmd, char read_write, int command) 843 { 844 int result; 845 u8 hostc; 846 847 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 848 return -EPROTO; 849 /* 850 * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here, 851 * even when reading. However if SPD Write Disable is set (Lynx Point and later), 852 * the read will fail if we don't set the R/#W bit. 853 */ 854 i801_set_hstadd(priv, addr, 855 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE); 856 857 /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */ 858 if (read_write == I2C_SMBUS_READ) 859 outb_p(hstcmd, SMBHSTDAT1(priv)); 860 else 861 outb_p(hstcmd, SMBHSTCMD(priv)); 862 863 if (read_write == I2C_SMBUS_WRITE) { 864 /* set I2C_EN bit in configuration register */ 865 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 866 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN); 867 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 868 pci_err(priv->pci_dev, "I2C block read is unsupported!\n"); 869 return -EOPNOTSUPP; 870 } 871 872 /* Block buffer isn't supported for I2C block transactions */ 873 result = i801_block_transaction_byte_by_byte(priv, data, read_write, command); 874 875 /* restore saved configuration register value */ 876 if (read_write == I2C_SMBUS_WRITE) 877 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 878 879 return result; 880 } 881 882 /* Return negative errno on error. */ 883 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 884 unsigned short flags, char read_write, u8 command, 885 int size, union i2c_smbus_data *data) 886 { 887 int hwpec, ret; 888 struct i801_priv *priv = i2c_get_adapdata(adap); 889 890 if (priv->acpi_reserved) 891 return -EBUSY; 892 893 pm_runtime_get_sync(&priv->pci_dev->dev); 894 895 ret = i801_check_pre(priv); 896 if (ret) 897 goto out; 898 899 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 900 && size != I2C_SMBUS_QUICK 901 && size != I2C_SMBUS_I2C_BLOCK_DATA; 902 903 if (hwpec) /* enable/disable hardware PEC */ 904 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 905 else 906 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 907 SMBAUXCTL(priv)); 908 909 if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL) 910 ret = i801_smbus_block_transaction(priv, data, addr, command, read_write, size); 911 else if (size == I2C_SMBUS_I2C_BLOCK_DATA) 912 ret = i801_i2c_block_transaction(priv, data, addr, command, read_write, size); 913 else 914 ret = i801_simple_transaction(priv, data, addr, command, read_write, size); 915 916 ret = i801_check_post(priv, ret); 917 918 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 919 * time, so we forcibly disable it after every transaction. 920 */ 921 if (hwpec) 922 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv)); 923 out: 924 /* 925 * Unlock the SMBus device for use by BIOS/ACPI, 926 * and clear status flags if not done already. 927 */ 928 outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv)); 929 930 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 931 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 932 return ret; 933 } 934 935 936 static u32 i801_func(struct i2c_adapter *adapter) 937 { 938 struct i801_priv *priv = i2c_get_adapdata(adapter); 939 940 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 941 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 942 I2C_FUNC_SMBUS_PROC_CALL | 943 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 944 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 945 ((priv->features & FEATURE_BLOCK_PROC) ? 946 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 947 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 948 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 949 ((priv->features & FEATURE_HOST_NOTIFY) ? 950 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 951 } 952 953 static void i801_enable_host_notify(struct i2c_adapter *adapter) 954 { 955 struct i801_priv *priv = i2c_get_adapdata(adapter); 956 957 if (!(priv->features & FEATURE_HOST_NOTIFY)) 958 return; 959 960 /* 961 * Enable host notify interrupt and block the generation of interrupt 962 * from the SMB_ALERT signal because the driver does not support 963 * SMBus Alert. 964 */ 965 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE | 966 priv->original_slvcmd, SMBSLVCMD(priv)); 967 968 /* clear Host Notify bit to allow a new notification */ 969 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 970 } 971 972 static void i801_disable_host_notify(struct i801_priv *priv) 973 { 974 if (!(priv->features & FEATURE_HOST_NOTIFY)) 975 return; 976 977 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 978 } 979 980 static const struct i2c_algorithm smbus_algorithm = { 981 .smbus_xfer = i801_access, 982 .functionality = i801_func, 983 }; 984 985 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \ 986 FEATURE_HOST_NOTIFY) 987 #define FEATURES_ICH5 (FEATURES_ICH4 | FEATURE_BLOCK_PROC | \ 988 FEATURE_I2C_BLOCK_READ | FEATURE_IRQ) 989 990 static const struct pci_device_id i801_ids[] = { 991 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) }, 992 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) }, 993 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) }, 994 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) }, 995 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) }, 996 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) }, 997 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) }, 998 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) }, 999 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) }, 1000 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) }, 1001 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) }, 1002 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) }, 1003 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) }, 1004 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) }, 1005 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) }, 1006 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) }, 1007 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) }, 1008 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) }, 1009 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) }, 1010 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) }, 1011 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) }, 1012 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) }, 1013 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) }, 1014 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) }, 1015 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) }, 1016 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) }, 1017 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) }, 1018 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) }, 1019 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) }, 1020 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) }, 1021 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) }, 1022 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) }, 1023 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) }, 1024 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) }, 1025 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) }, 1026 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) }, 1027 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1028 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1029 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1030 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1031 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1032 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) }, 1033 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1034 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1035 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1036 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1037 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1038 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1039 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1040 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1041 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1042 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1043 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1044 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1045 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1046 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1047 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1048 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1049 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1050 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1051 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1052 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1053 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1054 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1055 { 0, } 1056 }; 1057 1058 MODULE_DEVICE_TABLE(pci, i801_ids); 1059 1060 #if defined CONFIG_X86 && defined CONFIG_DMI 1061 static unsigned char apanel_addr; 1062 1063 /* Scan the system ROM for the signature "FJKEYINF" */ 1064 static __init const void __iomem *bios_signature(const void __iomem *bios) 1065 { 1066 ssize_t offset; 1067 const unsigned char signature[] = "FJKEYINF"; 1068 1069 for (offset = 0; offset < 0x10000; offset += 0x10) { 1070 if (check_signature(bios + offset, signature, 1071 sizeof(signature)-1)) 1072 return bios + offset; 1073 } 1074 return NULL; 1075 } 1076 1077 static void __init input_apanel_init(void) 1078 { 1079 void __iomem *bios; 1080 const void __iomem *p; 1081 1082 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1083 p = bios_signature(bios); 1084 if (p) { 1085 /* just use the first address */ 1086 apanel_addr = readb(p + 8 + 3) >> 1; 1087 } 1088 iounmap(bios); 1089 } 1090 1091 struct dmi_onboard_device_info { 1092 const char *name; 1093 u8 type; 1094 unsigned short i2c_addr; 1095 const char *i2c_type; 1096 }; 1097 1098 static const struct dmi_onboard_device_info dmi_devices[] = { 1099 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1100 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1101 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1102 }; 1103 1104 static void dmi_check_onboard_device(u8 type, const char *name, 1105 struct i2c_adapter *adap) 1106 { 1107 int i; 1108 struct i2c_board_info info; 1109 1110 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1111 /* & ~0x80, ignore enabled/disabled bit */ 1112 if ((type & ~0x80) != dmi_devices[i].type) 1113 continue; 1114 if (strcasecmp(name, dmi_devices[i].name)) 1115 continue; 1116 1117 memset(&info, 0, sizeof(struct i2c_board_info)); 1118 info.addr = dmi_devices[i].i2c_addr; 1119 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1120 i2c_new_client_device(adap, &info); 1121 break; 1122 } 1123 } 1124 1125 /* We use our own function to check for onboard devices instead of 1126 dmi_find_device() as some buggy BIOS's have the devices we are interested 1127 in marked as disabled */ 1128 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1129 { 1130 int i, count; 1131 1132 if (dm->type != DMI_ENTRY_ONBOARD_DEVICE) 1133 return; 1134 1135 count = (dm->length - sizeof(struct dmi_header)) / 2; 1136 for (i = 0; i < count; i++) { 1137 const u8 *d = (char *)(dm + 1) + (i * 2); 1138 const char *name = ((char *) dm) + dm->length; 1139 u8 type = d[0]; 1140 u8 s = d[1]; 1141 1142 if (!s) 1143 continue; 1144 s--; 1145 while (s > 0 && name[0]) { 1146 name += strlen(name) + 1; 1147 s--; 1148 } 1149 if (name[0] == 0) /* Bogus string reference */ 1150 continue; 1151 1152 dmi_check_onboard_device(type, name, adap); 1153 } 1154 } 1155 1156 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1157 static const char *const acpi_smo8800_ids[] = { 1158 "SMO8800", 1159 "SMO8801", 1160 "SMO8810", 1161 "SMO8811", 1162 "SMO8820", 1163 "SMO8821", 1164 "SMO8830", 1165 "SMO8831", 1166 }; 1167 1168 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1169 u32 nesting_level, 1170 void *context, 1171 void **return_value) 1172 { 1173 struct acpi_device_info *info; 1174 acpi_status status; 1175 char *hid; 1176 int i; 1177 1178 status = acpi_get_object_info(obj_handle, &info); 1179 if (ACPI_FAILURE(status)) 1180 return AE_OK; 1181 1182 if (!(info->valid & ACPI_VALID_HID)) 1183 goto smo88xx_not_found; 1184 1185 hid = info->hardware_id.string; 1186 if (!hid) 1187 goto smo88xx_not_found; 1188 1189 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1190 if (i < 0) 1191 goto smo88xx_not_found; 1192 1193 kfree(info); 1194 1195 *return_value = NULL; 1196 return AE_CTRL_TERMINATE; 1197 1198 smo88xx_not_found: 1199 kfree(info); 1200 return AE_OK; 1201 } 1202 1203 static bool is_dell_system_with_lis3lv02d(void) 1204 { 1205 void *err = ERR_PTR(-ENOENT); 1206 1207 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc.")) 1208 return false; 1209 1210 /* 1211 * Check that ACPI device SMO88xx is present and is functioning. 1212 * Function acpi_get_devices() already filters all ACPI devices 1213 * which are not present or are not functioning. 1214 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1215 * accelerometer but unfortunately ACPI does not provide any other 1216 * information (like I2C address). 1217 */ 1218 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err); 1219 1220 return !IS_ERR(err); 1221 } 1222 1223 /* 1224 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1225 * so it is needed to define mapping table based on DMI product names. 1226 */ 1227 static const struct { 1228 const char *dmi_product_name; 1229 unsigned short i2c_addr; 1230 } dell_lis3lv02d_devices[] = { 1231 /* 1232 * Dell platform team told us that these Latitude devices have 1233 * ST microelectronics accelerometer at I2C address 0x29. 1234 */ 1235 { "Latitude E5250", 0x29 }, 1236 { "Latitude E5450", 0x29 }, 1237 { "Latitude E5550", 0x29 }, 1238 { "Latitude E6440", 0x29 }, 1239 { "Latitude E6440 ATG", 0x29 }, 1240 { "Latitude E6540", 0x29 }, 1241 /* 1242 * Additional individual entries were added after verification. 1243 */ 1244 { "Latitude 5480", 0x29 }, 1245 { "Precision 3540", 0x29 }, 1246 { "Vostro V131", 0x1d }, 1247 { "Vostro 5568", 0x29 }, 1248 { "XPS 15 7590", 0x29 }, 1249 }; 1250 1251 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1252 { 1253 struct i2c_board_info info; 1254 const char *dmi_product_name; 1255 int i; 1256 1257 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1258 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1259 if (strcmp(dmi_product_name, 1260 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1261 break; 1262 } 1263 1264 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1265 dev_warn(&priv->pci_dev->dev, 1266 "Accelerometer lis3lv02d is present on SMBus but its" 1267 " address is unknown, skipping registration\n"); 1268 return; 1269 } 1270 1271 memset(&info, 0, sizeof(struct i2c_board_info)); 1272 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1273 strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1274 i2c_new_client_device(&priv->adapter, &info); 1275 } 1276 1277 /* Register optional slaves */ 1278 static void i801_probe_optional_slaves(struct i801_priv *priv) 1279 { 1280 /* Only register slaves on main SMBus channel */ 1281 if (priv->features & FEATURE_IDF) 1282 return; 1283 1284 if (apanel_addr) { 1285 struct i2c_board_info info = { 1286 .addr = apanel_addr, 1287 .type = "fujitsu_apanel", 1288 }; 1289 1290 i2c_new_client_device(&priv->adapter, &info); 1291 } 1292 1293 if (dmi_name_in_vendors("FUJITSU")) 1294 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1295 1296 if (is_dell_system_with_lis3lv02d()) 1297 register_dell_lis3lv02d_i2c_device(priv); 1298 1299 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1300 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1301 if (!priv->mux_pdev) 1302 #endif 1303 i2c_register_spd(&priv->adapter); 1304 } 1305 #else 1306 static void __init input_apanel_init(void) {} 1307 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1308 #endif /* CONFIG_X86 && CONFIG_DMI */ 1309 1310 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1311 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1312 .gpio_chip = "gpio_ich", 1313 .values = { 0x02, 0x03 }, 1314 .n_values = 2, 1315 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1316 .gpios = { 52, 53 }, 1317 .n_gpios = 2, 1318 }; 1319 1320 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1321 .gpio_chip = "gpio_ich", 1322 .values = { 0x02, 0x03, 0x01 }, 1323 .n_values = 3, 1324 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1325 .gpios = { 52, 53 }, 1326 .n_gpios = 2, 1327 }; 1328 1329 static const struct dmi_system_id mux_dmi_table[] = { 1330 { 1331 .matches = { 1332 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1333 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1334 }, 1335 .driver_data = &i801_mux_config_asus_z8_d12, 1336 }, 1337 { 1338 .matches = { 1339 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1340 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1341 }, 1342 .driver_data = &i801_mux_config_asus_z8_d12, 1343 }, 1344 { 1345 .matches = { 1346 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1347 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1348 }, 1349 .driver_data = &i801_mux_config_asus_z8_d12, 1350 }, 1351 { 1352 .matches = { 1353 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1354 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1355 }, 1356 .driver_data = &i801_mux_config_asus_z8_d12, 1357 }, 1358 { 1359 .matches = { 1360 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1361 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1362 }, 1363 .driver_data = &i801_mux_config_asus_z8_d12, 1364 }, 1365 { 1366 .matches = { 1367 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1368 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1369 }, 1370 .driver_data = &i801_mux_config_asus_z8_d12, 1371 }, 1372 { 1373 .matches = { 1374 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1375 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1376 }, 1377 .driver_data = &i801_mux_config_asus_z8_d18, 1378 }, 1379 { 1380 .matches = { 1381 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1382 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1383 }, 1384 .driver_data = &i801_mux_config_asus_z8_d18, 1385 }, 1386 { 1387 .matches = { 1388 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1389 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1390 }, 1391 .driver_data = &i801_mux_config_asus_z8_d12, 1392 }, 1393 { } 1394 }; 1395 1396 /* Setup multiplexing if needed */ 1397 static void i801_add_mux(struct i801_priv *priv) 1398 { 1399 struct device *dev = &priv->adapter.dev; 1400 const struct i801_mux_config *mux_config; 1401 struct i2c_mux_gpio_platform_data gpio_data; 1402 struct gpiod_lookup_table *lookup; 1403 const struct dmi_system_id *id; 1404 int i; 1405 1406 id = dmi_first_match(mux_dmi_table); 1407 if (!id) 1408 return; 1409 1410 mux_config = id->driver_data; 1411 1412 /* Prepare the platform data */ 1413 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1414 gpio_data.parent = priv->adapter.nr; 1415 gpio_data.values = mux_config->values; 1416 gpio_data.n_values = mux_config->n_values; 1417 gpio_data.classes = mux_config->classes; 1418 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1419 1420 /* Register GPIO descriptor lookup table */ 1421 lookup = devm_kzalloc(dev, 1422 struct_size(lookup, table, mux_config->n_gpios + 1), 1423 GFP_KERNEL); 1424 if (!lookup) 1425 return; 1426 lookup->dev_id = "i2c-mux-gpio"; 1427 for (i = 0; i < mux_config->n_gpios; i++) 1428 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip, 1429 mux_config->gpios[i], "mux", 0); 1430 gpiod_add_lookup_table(lookup); 1431 1432 /* 1433 * Register the mux device, we use PLATFORM_DEVID_NONE here 1434 * because since we are referring to the GPIO chip by name we are 1435 * anyways in deep trouble if there is more than one of these 1436 * devices, and there should likely only be one platform controller 1437 * hub. 1438 */ 1439 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1440 PLATFORM_DEVID_NONE, &gpio_data, 1441 sizeof(struct i2c_mux_gpio_platform_data)); 1442 if (IS_ERR(priv->mux_pdev)) { 1443 gpiod_remove_lookup_table(lookup); 1444 devm_kfree(dev, lookup); 1445 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1446 } else { 1447 priv->lookup = lookup; 1448 } 1449 } 1450 1451 static void i801_del_mux(struct i801_priv *priv) 1452 { 1453 platform_device_unregister(priv->mux_pdev); 1454 gpiod_remove_lookup_table(priv->lookup); 1455 } 1456 #else 1457 static inline void i801_add_mux(struct i801_priv *priv) { } 1458 static inline void i801_del_mux(struct i801_priv *priv) { } 1459 #endif 1460 1461 static struct platform_device * 1462 i801_add_tco_spt(struct pci_dev *pci_dev, struct resource *tco_res) 1463 { 1464 static const struct itco_wdt_platform_data pldata = { 1465 .name = "Intel PCH", 1466 .version = 4, 1467 }; 1468 struct resource *res; 1469 int ret; 1470 1471 /* 1472 * We must access the NO_REBOOT bit over the Primary to Sideband 1473 * (P2SB) bridge. 1474 */ 1475 1476 res = &tco_res[1]; 1477 ret = p2sb_bar(pci_dev->bus, 0, res); 1478 if (ret) 1479 return ERR_PTR(ret); 1480 1481 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1482 res->start += SBREG_SMBCTRL_DNV; 1483 else 1484 res->start += SBREG_SMBCTRL; 1485 1486 res->end = res->start + 3; 1487 1488 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1489 tco_res, 2, &pldata, sizeof(pldata)); 1490 } 1491 1492 static struct platform_device * 1493 i801_add_tco_cnl(struct pci_dev *pci_dev, struct resource *tco_res) 1494 { 1495 static const struct itco_wdt_platform_data pldata = { 1496 .name = "Intel PCH", 1497 .version = 6, 1498 }; 1499 1500 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1501 tco_res, 1, &pldata, sizeof(pldata)); 1502 } 1503 1504 static void i801_add_tco(struct i801_priv *priv) 1505 { 1506 struct pci_dev *pci_dev = priv->pci_dev; 1507 struct resource tco_res[2], *res; 1508 u32 tco_base, tco_ctl; 1509 1510 /* If we have ACPI based watchdog use that instead */ 1511 if (acpi_has_watchdog()) 1512 return; 1513 1514 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1515 return; 1516 1517 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1518 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1519 if (!(tco_ctl & TCOCTL_EN)) 1520 return; 1521 1522 memset(tco_res, 0, sizeof(tco_res)); 1523 /* 1524 * Always populate the main iTCO IO resource here. The second entry 1525 * for NO_REBOOT MMIO is filled by the SPT specific function. 1526 */ 1527 res = &tco_res[0]; 1528 res->start = tco_base & ~1; 1529 res->end = res->start + 32 - 1; 1530 res->flags = IORESOURCE_IO; 1531 1532 if (priv->features & FEATURE_TCO_CNL) 1533 priv->tco_pdev = i801_add_tco_cnl(pci_dev, tco_res); 1534 else 1535 priv->tco_pdev = i801_add_tco_spt(pci_dev, tco_res); 1536 1537 if (IS_ERR(priv->tco_pdev)) 1538 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1539 } 1540 1541 #ifdef CONFIG_ACPI 1542 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1543 acpi_physical_address address) 1544 { 1545 return address >= priv->smba && 1546 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1547 } 1548 1549 static acpi_status 1550 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1551 u64 *value, void *handler_context, void *region_context) 1552 { 1553 struct i801_priv *priv = handler_context; 1554 struct pci_dev *pdev = priv->pci_dev; 1555 acpi_status status; 1556 1557 /* 1558 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1559 * further access from the driver itself. This device is now owned 1560 * by the system firmware. 1561 */ 1562 i2c_lock_bus(&priv->adapter, I2C_LOCK_SEGMENT); 1563 1564 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1565 priv->acpi_reserved = true; 1566 1567 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1568 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1569 1570 /* 1571 * BIOS is accessing the host controller so prevent it from 1572 * suspending automatically from now on. 1573 */ 1574 pm_runtime_get_sync(&pdev->dev); 1575 } 1576 1577 if ((function & ACPI_IO_MASK) == ACPI_READ) 1578 status = acpi_os_read_port(address, (u32 *)value, bits); 1579 else 1580 status = acpi_os_write_port(address, (u32)*value, bits); 1581 1582 i2c_unlock_bus(&priv->adapter, I2C_LOCK_SEGMENT); 1583 1584 return status; 1585 } 1586 1587 static int i801_acpi_probe(struct i801_priv *priv) 1588 { 1589 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1590 acpi_status status; 1591 1592 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, 1593 i801_acpi_io_handler, NULL, priv); 1594 if (ACPI_SUCCESS(status)) 1595 return 0; 1596 1597 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1598 } 1599 1600 static void i801_acpi_remove(struct i801_priv *priv) 1601 { 1602 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1603 1604 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1605 } 1606 #else 1607 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1608 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1609 #endif 1610 1611 static void i801_setup_hstcfg(struct i801_priv *priv) 1612 { 1613 unsigned char hstcfg = priv->original_hstcfg; 1614 1615 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1616 hstcfg |= SMBHSTCFG_HST_EN; 1617 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1618 } 1619 1620 static void i801_restore_regs(struct i801_priv *priv) 1621 { 1622 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1623 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1624 } 1625 1626 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1627 { 1628 int err, i; 1629 struct i801_priv *priv; 1630 1631 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1632 if (!priv) 1633 return -ENOMEM; 1634 1635 i2c_set_adapdata(&priv->adapter, priv); 1636 priv->adapter.owner = THIS_MODULE; 1637 priv->adapter.class = I2C_CLASS_HWMON; 1638 priv->adapter.algo = &smbus_algorithm; 1639 priv->adapter.dev.parent = &dev->dev; 1640 acpi_use_parent_companion(&priv->adapter.dev); 1641 priv->adapter.retries = 3; 1642 1643 priv->pci_dev = dev; 1644 priv->features = id->driver_data; 1645 1646 /* Disable features on user request */ 1647 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1648 if (priv->features & disable_features & (1 << i)) 1649 dev_notice(&dev->dev, "%s disabled by user\n", 1650 i801_feature_names[i]); 1651 } 1652 priv->features &= ~disable_features; 1653 1654 /* The block process call uses block buffer mode */ 1655 if (!(priv->features & FEATURE_BLOCK_BUFFER)) 1656 priv->features &= ~FEATURE_BLOCK_PROC; 1657 1658 err = pcim_enable_device(dev); 1659 if (err) { 1660 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1661 err); 1662 return err; 1663 } 1664 pcim_pin_device(dev); 1665 1666 /* Determine the address of the SMBus area */ 1667 priv->smba = pci_resource_start(dev, SMBBAR); 1668 if (!priv->smba) { 1669 dev_err(&dev->dev, 1670 "SMBus base address uninitialized, upgrade BIOS\n"); 1671 return -ENODEV; 1672 } 1673 1674 if (i801_acpi_probe(priv)) 1675 return -ENODEV; 1676 1677 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME); 1678 if (err) { 1679 dev_err(&dev->dev, 1680 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1681 priv->smba, 1682 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1683 i801_acpi_remove(priv); 1684 return err; 1685 } 1686 1687 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1688 i801_setup_hstcfg(priv); 1689 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1690 dev_info(&dev->dev, "Enabling SMBus device\n"); 1691 1692 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1693 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1694 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1695 priv->features &= ~FEATURE_IRQ; 1696 } 1697 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1698 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1699 1700 /* Clear special mode bits */ 1701 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1702 outb_p(inb_p(SMBAUXCTL(priv)) & 1703 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1704 1705 /* Default timeout in interrupt mode: 200 ms */ 1706 priv->adapter.timeout = HZ / 5; 1707 1708 if (dev->irq == IRQ_NOTCONNECTED) 1709 priv->features &= ~FEATURE_IRQ; 1710 1711 if (priv->features & FEATURE_IRQ) { 1712 u16 pcists; 1713 1714 /* Complain if an interrupt is already pending */ 1715 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1716 if (pcists & PCI_STATUS_INTERRUPT) 1717 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1718 } 1719 1720 if (priv->features & FEATURE_IRQ) { 1721 init_completion(&priv->done); 1722 1723 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1724 IRQF_SHARED, DRV_NAME, priv); 1725 if (err) { 1726 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1727 dev->irq, err); 1728 priv->features &= ~FEATURE_IRQ; 1729 } 1730 } 1731 dev_info(&dev->dev, "SMBus using %s\n", 1732 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1733 1734 /* Host notification uses an interrupt */ 1735 if (!(priv->features & FEATURE_IRQ)) 1736 priv->features &= ~FEATURE_HOST_NOTIFY; 1737 1738 /* Remember original Interrupt and Host Notify settings */ 1739 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL; 1740 if (priv->features & FEATURE_HOST_NOTIFY) 1741 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1742 1743 i801_add_tco(priv); 1744 1745 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1746 "SMBus I801 adapter at %04lx", priv->smba); 1747 err = i2c_add_adapter(&priv->adapter); 1748 if (err) { 1749 platform_device_unregister(priv->tco_pdev); 1750 i801_acpi_remove(priv); 1751 i801_restore_regs(priv); 1752 return err; 1753 } 1754 1755 i801_enable_host_notify(&priv->adapter); 1756 1757 /* We ignore errors - multiplexing is optional */ 1758 i801_add_mux(priv); 1759 i801_probe_optional_slaves(priv); 1760 1761 pci_set_drvdata(dev, priv); 1762 1763 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1764 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1765 pm_runtime_use_autosuspend(&dev->dev); 1766 pm_runtime_put_autosuspend(&dev->dev); 1767 pm_runtime_allow(&dev->dev); 1768 1769 return 0; 1770 } 1771 1772 static void i801_remove(struct pci_dev *dev) 1773 { 1774 struct i801_priv *priv = pci_get_drvdata(dev); 1775 1776 i801_disable_host_notify(priv); 1777 i801_del_mux(priv); 1778 i2c_del_adapter(&priv->adapter); 1779 i801_acpi_remove(priv); 1780 1781 platform_device_unregister(priv->tco_pdev); 1782 1783 /* if acpi_reserved is set then usage_count is incremented already */ 1784 if (!priv->acpi_reserved) 1785 pm_runtime_get_noresume(&dev->dev); 1786 1787 i801_restore_regs(priv); 1788 1789 /* 1790 * do not call pci_disable_device(dev) since it can cause hard hangs on 1791 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1792 */ 1793 } 1794 1795 static void i801_shutdown(struct pci_dev *dev) 1796 { 1797 struct i801_priv *priv = pci_get_drvdata(dev); 1798 1799 i801_disable_host_notify(priv); 1800 /* Restore config registers to avoid hard hang on some systems */ 1801 i801_restore_regs(priv); 1802 } 1803 1804 static int i801_suspend(struct device *dev) 1805 { 1806 struct i801_priv *priv = dev_get_drvdata(dev); 1807 1808 i2c_mark_adapter_suspended(&priv->adapter); 1809 i801_restore_regs(priv); 1810 1811 return 0; 1812 } 1813 1814 static int i801_resume(struct device *dev) 1815 { 1816 struct i801_priv *priv = dev_get_drvdata(dev); 1817 1818 i801_setup_hstcfg(priv); 1819 i801_enable_host_notify(&priv->adapter); 1820 i2c_mark_adapter_resumed(&priv->adapter); 1821 1822 return 0; 1823 } 1824 1825 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1826 1827 static struct pci_driver i801_driver = { 1828 .name = DRV_NAME, 1829 .id_table = i801_ids, 1830 .probe = i801_probe, 1831 .remove = i801_remove, 1832 .shutdown = i801_shutdown, 1833 .driver = { 1834 .pm = pm_sleep_ptr(&i801_pm_ops), 1835 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1836 }, 1837 }; 1838 1839 static int __init i2c_i801_init(struct pci_driver *drv) 1840 { 1841 if (dmi_name_in_vendors("FUJITSU")) 1842 input_apanel_init(); 1843 return pci_register_driver(drv); 1844 } 1845 1846 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1847 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1848 MODULE_DESCRIPTION("I801 SMBus driver"); 1849 MODULE_LICENSE("GPL"); 1850 1851 module_driver(i801_driver, i2c_i801_init, pci_unregister_driver); 1852