1 /* 2 * Copyright (c) 2014 Linaro Ltd. 3 * Copyright (c) 2014 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * Now only support 7 bit address. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/i2c.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 23 /* Register Map */ 24 #define HIX5I2C_CTRL 0x00 25 #define HIX5I2C_COM 0x04 26 #define HIX5I2C_ICR 0x08 27 #define HIX5I2C_SR 0x0c 28 #define HIX5I2C_SCL_H 0x10 29 #define HIX5I2C_SCL_L 0x14 30 #define HIX5I2C_TXR 0x18 31 #define HIX5I2C_RXR 0x1c 32 33 /* I2C_CTRL_REG */ 34 #define I2C_ENABLE BIT(8) 35 #define I2C_UNMASK_TOTAL BIT(7) 36 #define I2C_UNMASK_START BIT(6) 37 #define I2C_UNMASK_END BIT(5) 38 #define I2C_UNMASK_SEND BIT(4) 39 #define I2C_UNMASK_RECEIVE BIT(3) 40 #define I2C_UNMASK_ACK BIT(2) 41 #define I2C_UNMASK_ARBITRATE BIT(1) 42 #define I2C_UNMASK_OVER BIT(0) 43 #define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER) 44 45 /* I2C_COM_REG */ 46 #define I2C_NO_ACK BIT(4) 47 #define I2C_START BIT(3) 48 #define I2C_READ BIT(2) 49 #define I2C_WRITE BIT(1) 50 #define I2C_STOP BIT(0) 51 52 /* I2C_ICR_REG */ 53 #define I2C_CLEAR_START BIT(6) 54 #define I2C_CLEAR_END BIT(5) 55 #define I2C_CLEAR_SEND BIT(4) 56 #define I2C_CLEAR_RECEIVE BIT(3) 57 #define I2C_CLEAR_ACK BIT(2) 58 #define I2C_CLEAR_ARBITRATE BIT(1) 59 #define I2C_CLEAR_OVER BIT(0) 60 #define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \ 61 I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \ 62 I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \ 63 I2C_CLEAR_OVER) 64 65 /* I2C_SR_REG */ 66 #define I2C_BUSY BIT(7) 67 #define I2C_START_INTR BIT(6) 68 #define I2C_END_INTR BIT(5) 69 #define I2C_SEND_INTR BIT(4) 70 #define I2C_RECEIVE_INTR BIT(3) 71 #define I2C_ACK_INTR BIT(2) 72 #define I2C_ARBITRATE_INTR BIT(1) 73 #define I2C_OVER_INTR BIT(0) 74 75 #define HIX5I2C_MAX_FREQ 400000 /* 400k */ 76 #define HIX5I2C_READ_OPERATION 0x01 77 78 enum hix5hd2_i2c_state { 79 HIX5I2C_STAT_RW_ERR = -1, 80 HIX5I2C_STAT_INIT, 81 HIX5I2C_STAT_RW, 82 HIX5I2C_STAT_SND_STOP, 83 HIX5I2C_STAT_RW_SUCCESS, 84 }; 85 86 struct hix5hd2_i2c_priv { 87 struct i2c_adapter adap; 88 struct i2c_msg *msg; 89 struct completion msg_complete; 90 unsigned int msg_idx; 91 unsigned int msg_len; 92 int stop; 93 void __iomem *regs; 94 struct clk *clk; 95 struct device *dev; 96 spinlock_t lock; /* IRQ synchronization */ 97 int err; 98 unsigned int freq; 99 enum hix5hd2_i2c_state state; 100 }; 101 102 static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv) 103 { 104 u32 val = readl_relaxed(priv->regs + HIX5I2C_SR); 105 106 writel_relaxed(val, priv->regs + HIX5I2C_ICR); 107 108 return val; 109 } 110 111 static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv) 112 { 113 writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR); 114 } 115 116 static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv) 117 { 118 writel_relaxed(0, priv->regs + HIX5I2C_CTRL); 119 } 120 121 static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv) 122 { 123 writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL, 124 priv->regs + HIX5I2C_CTRL); 125 } 126 127 static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv) 128 { 129 u32 rate, val; 130 u32 scl, sysclock; 131 132 /* close all i2c interrupt */ 133 val = readl_relaxed(priv->regs + HIX5I2C_CTRL); 134 writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL); 135 136 rate = priv->freq; 137 sysclock = clk_get_rate(priv->clk); 138 scl = (sysclock / (rate * 2)) / 2 - 1; 139 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H); 140 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L); 141 142 /* restore original interrupt*/ 143 writel_relaxed(val, priv->regs + HIX5I2C_CTRL); 144 145 dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n", 146 __func__, sysclock, rate, scl); 147 } 148 149 static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv) 150 { 151 hix5hd2_i2c_disable_irq(priv); 152 hix5hd2_i2c_drv_setrate(priv); 153 hix5hd2_i2c_clr_all_irq(priv); 154 hix5hd2_i2c_enable_irq(priv); 155 } 156 157 static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv) 158 { 159 clk_disable_unprepare(priv->clk); 160 msleep(20); 161 clk_prepare_enable(priv->clk); 162 hix5hd2_i2c_init(priv); 163 } 164 165 static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv) 166 { 167 unsigned long stop_time; 168 u32 int_status; 169 170 /* wait for 100 milli seconds for the bus to be idle */ 171 stop_time = jiffies + msecs_to_jiffies(100); 172 do { 173 int_status = hix5hd2_i2c_clr_pend_irq(priv); 174 if (!(int_status & I2C_BUSY)) 175 return 0; 176 177 usleep_range(50, 200); 178 } while (time_before(jiffies, stop_time)); 179 180 return -EBUSY; 181 } 182 183 static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv) 184 { 185 if (priv->state == HIX5I2C_STAT_SND_STOP) 186 dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__); 187 else 188 dev_dbg(priv->dev, "%s: have not data to send\n", __func__); 189 190 priv->state = HIX5I2C_STAT_RW_SUCCESS; 191 priv->err = 0; 192 } 193 194 static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv) 195 { 196 if (priv->stop) { 197 priv->state = HIX5I2C_STAT_SND_STOP; 198 writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM); 199 } else { 200 hix5hd2_rw_over(priv); 201 } 202 } 203 204 static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv) 205 { 206 if (priv->msg_len == 1) { 207 /* the last byte don't need send ACK */ 208 writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM); 209 } else if (priv->msg_len > 1) { 210 /* if i2c master receive data will send ACK */ 211 writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM); 212 } else { 213 hix5hd2_rw_handle_stop(priv); 214 } 215 } 216 217 static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv) 218 { 219 u8 data; 220 221 if (priv->msg_len > 0) { 222 data = priv->msg->buf[priv->msg_idx++]; 223 writel_relaxed(data, priv->regs + HIX5I2C_TXR); 224 writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM); 225 } else { 226 hix5hd2_rw_handle_stop(priv); 227 } 228 } 229 230 static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv) 231 { 232 u8 data; 233 234 if (priv->state == HIX5I2C_STAT_INIT) { 235 priv->state = HIX5I2C_STAT_RW; 236 } else if (priv->state == HIX5I2C_STAT_RW) { 237 if (priv->msg->flags & I2C_M_RD) { 238 data = readl_relaxed(priv->regs + HIX5I2C_RXR); 239 priv->msg->buf[priv->msg_idx++] = data; 240 } 241 priv->msg_len--; 242 } else { 243 dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n", 244 __func__, priv->state, priv->msg_len); 245 return -EAGAIN; 246 } 247 return 0; 248 } 249 250 static irqreturn_t hix5hd2_i2c_irq(int irqno, void *dev_id) 251 { 252 struct hix5hd2_i2c_priv *priv = dev_id; 253 u32 int_status; 254 int ret; 255 256 spin_lock(&priv->lock); 257 258 int_status = hix5hd2_i2c_clr_pend_irq(priv); 259 260 /* handle error */ 261 if (int_status & I2C_ARBITRATE_INTR) { 262 /* bus error */ 263 dev_dbg(priv->dev, "ARB bus loss\n"); 264 priv->err = -EAGAIN; 265 priv->state = HIX5I2C_STAT_RW_ERR; 266 goto stop; 267 } else if (int_status & I2C_ACK_INTR) { 268 /* ack error */ 269 dev_dbg(priv->dev, "No ACK from device\n"); 270 priv->err = -ENXIO; 271 priv->state = HIX5I2C_STAT_RW_ERR; 272 goto stop; 273 } 274 275 if (int_status & I2C_OVER_INTR) { 276 if (priv->msg_len > 0) { 277 ret = hix5hd2_rw_preprocess(priv); 278 if (ret) { 279 priv->err = ret; 280 priv->state = HIX5I2C_STAT_RW_ERR; 281 goto stop; 282 } 283 if (priv->msg->flags & I2C_M_RD) 284 hix5hd2_read_handle(priv); 285 else 286 hix5hd2_write_handle(priv); 287 } else { 288 hix5hd2_rw_over(priv); 289 } 290 } 291 292 stop: 293 if ((priv->state == HIX5I2C_STAT_RW_SUCCESS && 294 priv->msg->len == priv->msg_idx) || 295 (priv->state == HIX5I2C_STAT_RW_ERR)) { 296 hix5hd2_i2c_disable_irq(priv); 297 hix5hd2_i2c_clr_pend_irq(priv); 298 complete(&priv->msg_complete); 299 } 300 301 spin_unlock(&priv->lock); 302 303 return IRQ_HANDLED; 304 } 305 306 static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop) 307 { 308 unsigned long flags; 309 310 spin_lock_irqsave(&priv->lock, flags); 311 hix5hd2_i2c_clr_all_irq(priv); 312 hix5hd2_i2c_enable_irq(priv); 313 314 if (priv->msg->flags & I2C_M_RD) 315 writel_relaxed((priv->msg->addr << 1) | HIX5I2C_READ_OPERATION, 316 priv->regs + HIX5I2C_TXR); 317 else 318 writel_relaxed(priv->msg->addr << 1, 319 priv->regs + HIX5I2C_TXR); 320 321 writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM); 322 spin_unlock_irqrestore(&priv->lock, flags); 323 } 324 325 static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv, 326 struct i2c_msg *msgs, int stop) 327 { 328 unsigned long timeout; 329 int ret; 330 331 priv->msg = msgs; 332 priv->msg_idx = 0; 333 priv->msg_len = priv->msg->len; 334 priv->stop = stop; 335 priv->err = 0; 336 priv->state = HIX5I2C_STAT_INIT; 337 338 reinit_completion(&priv->msg_complete); 339 hix5hd2_i2c_message_start(priv, stop); 340 341 timeout = wait_for_completion_timeout(&priv->msg_complete, 342 priv->adap.timeout); 343 if (timeout == 0) { 344 priv->state = HIX5I2C_STAT_RW_ERR; 345 priv->err = -ETIMEDOUT; 346 dev_warn(priv->dev, "%s timeout=%d\n", 347 msgs->flags & I2C_M_RD ? "rx" : "tx", 348 priv->adap.timeout); 349 } 350 ret = priv->state; 351 352 /* 353 * If this is the last message to be transfered (stop == 1) 354 * Then check if the bus can be brought back to idle. 355 */ 356 if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop) 357 ret = hix5hd2_i2c_wait_bus_idle(priv); 358 359 if (ret < 0) 360 hix5hd2_i2c_reset(priv); 361 362 return priv->err; 363 } 364 365 static int hix5hd2_i2c_xfer(struct i2c_adapter *adap, 366 struct i2c_msg *msgs, int num) 367 { 368 struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap); 369 int i, ret, stop; 370 371 pm_runtime_get_sync(priv->dev); 372 373 for (i = 0; i < num; i++, msgs++) { 374 stop = (i == num - 1); 375 ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop); 376 if (ret < 0) 377 goto out; 378 } 379 380 if (i == num) { 381 ret = num; 382 } else { 383 /* Only one message, cannot access the device */ 384 if (i == 1) 385 ret = -EREMOTEIO; 386 else 387 ret = i; 388 389 dev_warn(priv->dev, "xfer message failed\n"); 390 } 391 392 out: 393 pm_runtime_mark_last_busy(priv->dev); 394 pm_runtime_put_autosuspend(priv->dev); 395 return ret; 396 } 397 398 static u32 hix5hd2_i2c_func(struct i2c_adapter *adap) 399 { 400 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 401 } 402 403 static const struct i2c_algorithm hix5hd2_i2c_algorithm = { 404 .master_xfer = hix5hd2_i2c_xfer, 405 .functionality = hix5hd2_i2c_func, 406 }; 407 408 static int hix5hd2_i2c_probe(struct platform_device *pdev) 409 { 410 struct device_node *np = pdev->dev.of_node; 411 struct hix5hd2_i2c_priv *priv; 412 struct resource *mem; 413 unsigned int freq; 414 int irq, ret; 415 416 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 417 if (!priv) 418 return -ENOMEM; 419 420 if (of_property_read_u32(np, "clock-frequency", &freq)) { 421 /* use 100k as default value */ 422 priv->freq = 100000; 423 } else { 424 if (freq > HIX5I2C_MAX_FREQ) { 425 priv->freq = HIX5I2C_MAX_FREQ; 426 dev_warn(priv->dev, "use max freq %d instead\n", 427 HIX5I2C_MAX_FREQ); 428 } else { 429 priv->freq = freq; 430 } 431 } 432 433 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 434 priv->regs = devm_ioremap_resource(&pdev->dev, mem); 435 if (IS_ERR(priv->regs)) 436 return PTR_ERR(priv->regs); 437 438 irq = platform_get_irq(pdev, 0); 439 if (irq <= 0) { 440 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n"); 441 return irq; 442 } 443 444 priv->clk = devm_clk_get(&pdev->dev, NULL); 445 if (IS_ERR(priv->clk)) { 446 dev_err(&pdev->dev, "cannot get clock\n"); 447 return PTR_ERR(priv->clk); 448 } 449 clk_prepare_enable(priv->clk); 450 451 strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); 452 priv->dev = &pdev->dev; 453 priv->adap.owner = THIS_MODULE; 454 priv->adap.algo = &hix5hd2_i2c_algorithm; 455 priv->adap.retries = 3; 456 priv->adap.dev.of_node = np; 457 priv->adap.algo_data = priv; 458 priv->adap.dev.parent = &pdev->dev; 459 i2c_set_adapdata(&priv->adap, priv); 460 platform_set_drvdata(pdev, priv); 461 spin_lock_init(&priv->lock); 462 init_completion(&priv->msg_complete); 463 464 hix5hd2_i2c_init(priv); 465 466 ret = devm_request_irq(&pdev->dev, irq, hix5hd2_i2c_irq, 467 IRQF_NO_SUSPEND | IRQF_ONESHOT, 468 dev_name(&pdev->dev), priv); 469 if (ret != 0) { 470 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", irq); 471 goto err_clk; 472 } 473 474 pm_suspend_ignore_children(&pdev->dev, true); 475 pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC); 476 pm_runtime_use_autosuspend(priv->dev); 477 pm_runtime_set_active(priv->dev); 478 pm_runtime_enable(priv->dev); 479 480 ret = i2c_add_adapter(&priv->adap); 481 if (ret < 0) 482 goto err_runtime; 483 484 return ret; 485 486 err_runtime: 487 pm_runtime_disable(priv->dev); 488 pm_runtime_set_suspended(priv->dev); 489 err_clk: 490 clk_disable_unprepare(priv->clk); 491 return ret; 492 } 493 494 static int hix5hd2_i2c_remove(struct platform_device *pdev) 495 { 496 struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); 497 498 i2c_del_adapter(&priv->adap); 499 pm_runtime_disable(priv->dev); 500 pm_runtime_set_suspended(priv->dev); 501 502 return 0; 503 } 504 505 #ifdef CONFIG_PM 506 static int hix5hd2_i2c_runtime_suspend(struct device *dev) 507 { 508 struct platform_device *pdev = to_platform_device(dev); 509 struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); 510 511 clk_disable_unprepare(priv->clk); 512 513 return 0; 514 } 515 516 static int hix5hd2_i2c_runtime_resume(struct device *dev) 517 { 518 struct platform_device *pdev = to_platform_device(dev); 519 struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); 520 521 clk_prepare_enable(priv->clk); 522 hix5hd2_i2c_init(priv); 523 524 return 0; 525 } 526 #endif 527 528 static const struct dev_pm_ops hix5hd2_i2c_pm_ops = { 529 SET_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend, 530 hix5hd2_i2c_runtime_resume, 531 NULL) 532 }; 533 534 static const struct of_device_id hix5hd2_i2c_match[] = { 535 { .compatible = "hisilicon,hix5hd2-i2c" }, 536 {}, 537 }; 538 MODULE_DEVICE_TABLE(of, hix5hd2_i2c_match); 539 540 static struct platform_driver hix5hd2_i2c_driver = { 541 .probe = hix5hd2_i2c_probe, 542 .remove = hix5hd2_i2c_remove, 543 .driver = { 544 .name = "hix5hd2-i2c", 545 .pm = &hix5hd2_i2c_pm_ops, 546 .of_match_table = hix5hd2_i2c_match, 547 }, 548 }; 549 550 module_platform_driver(hix5hd2_i2c_driver); 551 552 MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver"); 553 MODULE_AUTHOR("Wei Yan <sledge.yanwei@huawei.com>"); 554 MODULE_LICENSE("GPL"); 555 MODULE_ALIAS("platform:hix5hd2-i2c"); 556