1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * HiSilicon I2C Controller Driver for Kunpeng SoC 4 * 5 * Copyright (c) 2021 HiSilicon Technologies Co., Ltd. 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/i2c.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 #include <linux/units.h> 20 21 #define HISI_I2C_FRAME_CTRL 0x0000 22 #define HISI_I2C_FRAME_CTRL_SPEED_MODE GENMASK(1, 0) 23 #define HISI_I2C_FRAME_CTRL_ADDR_TEN BIT(2) 24 #define HISI_I2C_SLV_ADDR 0x0004 25 #define HISI_I2C_SLV_ADDR_VAL GENMASK(9, 0) 26 #define HISI_I2C_SLV_ADDR_GC_S_MODE BIT(10) 27 #define HISI_I2C_SLV_ADDR_GC_S_EN BIT(11) 28 #define HISI_I2C_CMD_TXDATA 0x0008 29 #define HISI_I2C_CMD_TXDATA_DATA GENMASK(7, 0) 30 #define HISI_I2C_CMD_TXDATA_RW BIT(8) 31 #define HISI_I2C_CMD_TXDATA_P_EN BIT(9) 32 #define HISI_I2C_CMD_TXDATA_SR_EN BIT(10) 33 #define HISI_I2C_RXDATA 0x000c 34 #define HISI_I2C_RXDATA_DATA GENMASK(7, 0) 35 #define HISI_I2C_SS_SCL_HCNT 0x0010 36 #define HISI_I2C_SS_SCL_LCNT 0x0014 37 #define HISI_I2C_FS_SCL_HCNT 0x0018 38 #define HISI_I2C_FS_SCL_LCNT 0x001c 39 #define HISI_I2C_HS_SCL_HCNT 0x0020 40 #define HISI_I2C_HS_SCL_LCNT 0x0024 41 #define HISI_I2C_FIFO_CTRL 0x0028 42 #define HISI_I2C_FIFO_RX_CLR BIT(0) 43 #define HISI_I2C_FIFO_TX_CLR BIT(1) 44 #define HISI_I2C_FIFO_RX_AF_THRESH GENMASK(7, 2) 45 #define HISI_I2C_FIFO_TX_AE_THRESH GENMASK(13, 8) 46 #define HISI_I2C_FIFO_STATE 0x002c 47 #define HISI_I2C_FIFO_STATE_RX_RERR BIT(0) 48 #define HISI_I2C_FIFO_STATE_RX_WERR BIT(1) 49 #define HISI_I2C_FIFO_STATE_RX_EMPTY BIT(3) 50 #define HISI_I2C_FIFO_STATE_TX_RERR BIT(6) 51 #define HISI_I2C_FIFO_STATE_TX_WERR BIT(7) 52 #define HISI_I2C_FIFO_STATE_TX_FULL BIT(11) 53 #define HISI_I2C_SDA_HOLD 0x0030 54 #define HISI_I2C_SDA_HOLD_TX GENMASK(15, 0) 55 #define HISI_I2C_SDA_HOLD_RX GENMASK(23, 16) 56 #define HISI_I2C_FS_SPK_LEN 0x0038 57 #define HISI_I2C_FS_SPK_LEN_CNT GENMASK(7, 0) 58 #define HISI_I2C_HS_SPK_LEN 0x003c 59 #define HISI_I2C_HS_SPK_LEN_CNT GENMASK(7, 0) 60 #define HISI_I2C_TX_INT_CLR 0x0040 61 #define HISI_I2C_TX_AEMPTY_INT BIT(0) 62 #define HISI_I2C_INT_MSTAT 0x0044 63 #define HISI_I2C_INT_CLR 0x0048 64 #define HISI_I2C_INT_MASK 0x004C 65 #define HISI_I2C_TRANS_STATE 0x0050 66 #define HISI_I2C_TRANS_ERR 0x0054 67 #define HISI_I2C_VERSION 0x0058 68 69 #define HISI_I2C_INT_ALL GENMASK(4, 0) 70 #define HISI_I2C_INT_TRANS_CPLT BIT(0) 71 #define HISI_I2C_INT_TRANS_ERR BIT(1) 72 #define HISI_I2C_INT_FIFO_ERR BIT(2) 73 #define HISI_I2C_INT_RX_FULL BIT(3) 74 #define HISI_I2C_INT_TX_EMPTY BIT(4) 75 #define HISI_I2C_INT_ERR \ 76 (HISI_I2C_INT_TRANS_ERR | HISI_I2C_INT_FIFO_ERR) 77 78 #define HISI_I2C_STD_SPEED_MODE 0 79 #define HISI_I2C_FAST_SPEED_MODE 1 80 #define HISI_I2C_HIGH_SPEED_MODE 2 81 82 #define HISI_I2C_TX_FIFO_DEPTH 64 83 #define HISI_I2C_RX_FIFO_DEPTH 64 84 #define HISI_I2C_TX_F_AE_THRESH 1 85 #define HISI_I2C_RX_F_AF_THRESH 60 86 87 #define NSEC_TO_CYCLES(ns, clk_rate_khz) \ 88 DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC) 89 90 struct hisi_i2c_controller { 91 struct i2c_adapter adapter; 92 void __iomem *iobase; 93 struct device *dev; 94 struct clk *clk; 95 int irq; 96 97 /* Intermediates for recording the transfer process */ 98 struct completion *completion; 99 struct i2c_msg *msgs; 100 int msg_num; 101 int msg_tx_idx; 102 int buf_tx_idx; 103 int msg_rx_idx; 104 int buf_rx_idx; 105 u16 tar_addr; 106 u32 xfer_err; 107 108 /* I2C bus configuration */ 109 struct i2c_timings t; 110 u32 clk_rate_khz; 111 u32 spk_len; 112 }; 113 114 static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask) 115 { 116 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); 117 } 118 119 static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask) 120 { 121 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); 122 } 123 124 static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) 125 { 126 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); 127 } 128 129 static void hisi_i2c_clear_tx_int(struct hisi_i2c_controller *ctlr, u32 mask) 130 { 131 writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR); 132 } 133 134 static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) 135 { 136 u32 int_err = ctlr->xfer_err, reg; 137 138 if (int_err & HISI_I2C_INT_FIFO_ERR) { 139 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 140 141 if (reg & HISI_I2C_FIFO_STATE_RX_RERR) 142 dev_err(ctlr->dev, "rx fifo error read\n"); 143 144 if (reg & HISI_I2C_FIFO_STATE_RX_WERR) 145 dev_err(ctlr->dev, "rx fifo error write\n"); 146 147 if (reg & HISI_I2C_FIFO_STATE_TX_RERR) 148 dev_err(ctlr->dev, "tx fifo error read\n"); 149 150 if (reg & HISI_I2C_FIFO_STATE_TX_WERR) 151 dev_err(ctlr->dev, "tx fifo error write\n"); 152 } 153 } 154 155 static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) 156 { 157 struct i2c_msg *msg = ctlr->msgs; 158 u32 reg; 159 160 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 161 reg &= ~HISI_I2C_FRAME_CTRL_ADDR_TEN; 162 if (msg->flags & I2C_M_TEN) 163 reg |= HISI_I2C_FRAME_CTRL_ADDR_TEN; 164 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 165 166 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); 167 reg &= ~HISI_I2C_SLV_ADDR_VAL; 168 reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr); 169 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); 170 171 reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); 172 reg |= HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR; 173 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 174 reg &= ~(HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR); 175 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 176 177 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 178 hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); 179 hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL); 180 181 return 0; 182 } 183 184 static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr) 185 { 186 ctlr->msg_num = 0; 187 ctlr->xfer_err = 0; 188 ctlr->msg_tx_idx = 0; 189 ctlr->msg_rx_idx = 0; 190 ctlr->buf_tx_idx = 0; 191 ctlr->buf_rx_idx = 0; 192 } 193 194 /* 195 * Initialize the transfer information and start the I2C bus transfer. 196 * We only configure the transfer and do some pre/post works here, and 197 * wait for the transfer done. The major transfer process is performed 198 * in the IRQ handler. 199 */ 200 static int hisi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 201 int num) 202 { 203 struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); 204 DECLARE_COMPLETION_ONSTACK(done); 205 int ret = num; 206 207 hisi_i2c_reset_xfer(ctlr); 208 ctlr->completion = &done; 209 ctlr->msg_num = num; 210 ctlr->msgs = msgs; 211 212 hisi_i2c_start_xfer(ctlr); 213 214 if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) { 215 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 216 synchronize_irq(ctlr->irq); 217 i2c_recover_bus(&ctlr->adapter); 218 dev_err(ctlr->dev, "bus transfer timeout\n"); 219 ret = -EIO; 220 } 221 222 if (ctlr->xfer_err) { 223 hisi_i2c_handle_errors(ctlr); 224 ret = -EIO; 225 } 226 227 hisi_i2c_reset_xfer(ctlr); 228 ctlr->completion = NULL; 229 230 return ret; 231 } 232 233 static u32 hisi_i2c_functionality(struct i2c_adapter *adap) 234 { 235 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 236 } 237 238 static const struct i2c_algorithm hisi_i2c_algo = { 239 .xfer = hisi_i2c_xfer, 240 .functionality = hisi_i2c_functionality, 241 }; 242 243 static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) 244 { 245 struct i2c_msg *cur_msg; 246 u32 fifo_state; 247 248 while (ctlr->msg_rx_idx < ctlr->msg_num) { 249 cur_msg = ctlr->msgs + ctlr->msg_rx_idx; 250 251 if (!(cur_msg->flags & I2C_M_RD)) { 252 ctlr->msg_rx_idx++; 253 continue; 254 } 255 256 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 257 while (!(fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) && 258 ctlr->buf_rx_idx < cur_msg->len) { 259 cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA); 260 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 261 } 262 263 if (ctlr->buf_rx_idx == cur_msg->len) { 264 ctlr->buf_rx_idx = 0; 265 ctlr->msg_rx_idx++; 266 } 267 268 if (fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) 269 break; 270 } 271 272 return 0; 273 } 274 275 static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) 276 { 277 int max_write = HISI_I2C_TX_FIFO_DEPTH - HISI_I2C_TX_F_AE_THRESH; 278 bool need_restart = false, last_msg; 279 struct i2c_msg *cur_msg; 280 u32 cmd, fifo_state; 281 282 while (ctlr->msg_tx_idx < ctlr->msg_num) { 283 cur_msg = ctlr->msgs + ctlr->msg_tx_idx; 284 last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1); 285 286 /* Signal the SR bit when we start transferring a new message */ 287 if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx) 288 need_restart = true; 289 290 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 291 while (!(fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) && 292 ctlr->buf_tx_idx < cur_msg->len && max_write) { 293 cmd = 0; 294 295 if (need_restart) { 296 cmd |= HISI_I2C_CMD_TXDATA_SR_EN; 297 need_restart = false; 298 } 299 300 /* Signal the STOP bit at the last frame of the last message */ 301 if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg) 302 cmd |= HISI_I2C_CMD_TXDATA_P_EN; 303 304 if (cur_msg->flags & I2C_M_RD) 305 cmd |= HISI_I2C_CMD_TXDATA_RW; 306 else 307 cmd |= FIELD_PREP(HISI_I2C_CMD_TXDATA_DATA, 308 cur_msg->buf[ctlr->buf_tx_idx]); 309 310 writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA); 311 ctlr->buf_tx_idx++; 312 max_write--; 313 314 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 315 } 316 317 /* Update the transfer index after per message transfer is done. */ 318 if (ctlr->buf_tx_idx == cur_msg->len) { 319 ctlr->buf_tx_idx = 0; 320 ctlr->msg_tx_idx++; 321 } 322 323 if ((fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) || 324 max_write == 0) 325 break; 326 } 327 328 /* 329 * Disable the TX_EMPTY interrupt after finishing all the messages to 330 * avoid overwhelming the CPU. 331 */ 332 if (ctlr->msg_tx_idx == ctlr->msg_num) 333 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_TX_EMPTY); 334 335 hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); 336 } 337 338 static irqreturn_t hisi_i2c_irq(int irq, void *context) 339 { 340 struct hisi_i2c_controller *ctlr = context; 341 u32 int_stat; 342 343 /* 344 * Don't handle the interrupt if cltr->completion is NULL. We may 345 * reach here because the interrupt is spurious or the transfer is 346 * started by another port (e.g. firmware) rather than us. 347 */ 348 if (!ctlr->completion) 349 return IRQ_NONE; 350 351 int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); 352 hisi_i2c_clear_int(ctlr, int_stat); 353 if (!(int_stat & HISI_I2C_INT_ALL)) 354 return IRQ_NONE; 355 356 if (int_stat & HISI_I2C_INT_TX_EMPTY) 357 hisi_i2c_xfer_msg(ctlr); 358 359 if (int_stat & HISI_I2C_INT_ERR) { 360 ctlr->xfer_err = int_stat; 361 goto out; 362 } 363 364 /* Drain the rx fifo before finish the transfer */ 365 if (int_stat & (HISI_I2C_INT_TRANS_CPLT | HISI_I2C_INT_RX_FULL)) 366 hisi_i2c_read_rx_fifo(ctlr); 367 368 out: 369 /* 370 * Only use TRANS_CPLT to indicate the completion. On error cases we'll 371 * get two interrupts, INT_ERR first then TRANS_CPLT. 372 */ 373 if (int_stat & HISI_I2C_INT_TRANS_CPLT) { 374 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 375 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 376 hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); 377 complete(ctlr->completion); 378 } 379 380 return IRQ_HANDLED; 381 } 382 383 /* 384 * Helper function for calculating and configuring the HIGH and LOW 385 * periods of SCL clock. The caller will pass the ratio of the 386 * counts (divide / divisor) according to the target speed mode, 387 * and the target registers. 388 */ 389 static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr, 390 u32 divide, u32 divisor, 391 u32 reg_hcnt, u32 reg_lcnt) 392 { 393 u32 total_cnt, t_scl_hcnt, t_scl_lcnt, scl_fall_cnt, scl_rise_cnt; 394 u32 scl_hcnt, scl_lcnt; 395 396 /* Total SCL clock cycles per speed period */ 397 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); 398 /* Total HIGH level SCL clock cycles including edges */ 399 t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor); 400 /* Total LOW level SCL clock cycles including edges */ 401 t_scl_lcnt = total_cnt - t_scl_hcnt; 402 /* Fall edge SCL clock cycles */ 403 scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); 404 /* Rise edge SCL clock cycles */ 405 scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); 406 407 /* Calculated HIGH and LOW periods of SCL clock */ 408 scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt; 409 scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt; 410 411 writel(scl_hcnt, ctlr->iobase + reg_hcnt); 412 writel(scl_lcnt, ctlr->iobase + reg_lcnt); 413 } 414 415 static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr) 416 { 417 u32 reg, sda_hold_cnt, speed_mode; 418 419 i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true); 420 ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); 421 422 switch (ctlr->t.bus_freq_hz) { 423 case I2C_MAX_FAST_MODE_FREQ: 424 speed_mode = HISI_I2C_FAST_SPEED_MODE; 425 hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT); 426 break; 427 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 428 speed_mode = HISI_I2C_HIGH_SPEED_MODE; 429 hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT); 430 break; 431 case I2C_MAX_STANDARD_MODE_FREQ: 432 default: 433 speed_mode = HISI_I2C_STD_SPEED_MODE; 434 435 /* For default condition force the bus speed to standard mode. */ 436 ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 437 hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT); 438 break; 439 } 440 441 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 442 reg &= ~HISI_I2C_FRAME_CTRL_SPEED_MODE; 443 reg |= FIELD_PREP(HISI_I2C_FRAME_CTRL_SPEED_MODE, speed_mode); 444 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 445 446 sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); 447 448 reg = FIELD_PREP(HISI_I2C_SDA_HOLD_TX, sda_hold_cnt); 449 writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); 450 451 writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN); 452 453 reg = FIELD_PREP(HISI_I2C_FIFO_RX_AF_THRESH, HISI_I2C_RX_F_AF_THRESH); 454 reg |= FIELD_PREP(HISI_I2C_FIFO_TX_AE_THRESH, HISI_I2C_TX_F_AE_THRESH); 455 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 456 } 457 458 static int hisi_i2c_probe(struct platform_device *pdev) 459 { 460 struct hisi_i2c_controller *ctlr; 461 struct device *dev = &pdev->dev; 462 struct i2c_adapter *adapter; 463 u64 clk_rate_hz; 464 u32 hw_version; 465 int ret; 466 467 ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL); 468 if (!ctlr) 469 return -ENOMEM; 470 471 ctlr->iobase = devm_platform_ioremap_resource(pdev, 0); 472 if (IS_ERR(ctlr->iobase)) 473 return PTR_ERR(ctlr->iobase); 474 475 ctlr->irq = platform_get_irq(pdev, 0); 476 if (ctlr->irq < 0) 477 return ctlr->irq; 478 479 ctlr->dev = dev; 480 481 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 482 483 ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr); 484 if (ret) 485 return dev_err_probe(dev, ret, "failed to request irq handler\n"); 486 487 ctlr->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 488 if (IS_ERR_OR_NULL(ctlr->clk)) { 489 ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz); 490 if (ret) 491 return dev_err_probe(dev, ret, "failed to get clock frequency\n"); 492 } else { 493 clk_rate_hz = clk_get_rate(ctlr->clk); 494 } 495 496 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); 497 498 hisi_i2c_configure_bus(ctlr); 499 500 adapter = &ctlr->adapter; 501 snprintf(adapter->name, sizeof(adapter->name), 502 "HiSilicon I2C Controller %s", dev_name(dev)); 503 adapter->owner = THIS_MODULE; 504 adapter->algo = &hisi_i2c_algo; 505 adapter->dev.parent = dev; 506 i2c_set_adapdata(adapter, ctlr); 507 508 ret = devm_i2c_add_adapter(dev, adapter); 509 if (ret) 510 return ret; 511 512 hw_version = readl(ctlr->iobase + HISI_I2C_VERSION); 513 dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n", 514 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version); 515 516 return 0; 517 } 518 519 static const struct acpi_device_id hisi_i2c_acpi_ids[] = { 520 { "HISI03D1", 0 }, 521 { } 522 }; 523 MODULE_DEVICE_TABLE(acpi, hisi_i2c_acpi_ids); 524 525 static const struct of_device_id hisi_i2c_dts_ids[] = { 526 { .compatible = "hisilicon,ascend910-i2c", }, 527 { } 528 }; 529 MODULE_DEVICE_TABLE(of, hisi_i2c_dts_ids); 530 531 static struct platform_driver hisi_i2c_driver = { 532 .probe = hisi_i2c_probe, 533 .driver = { 534 .name = "hisi-i2c", 535 .acpi_match_table = hisi_i2c_acpi_ids, 536 .of_match_table = hisi_i2c_dts_ids, 537 }, 538 }; 539 module_platform_driver(hisi_i2c_driver); 540 541 MODULE_AUTHOR("Yicong Yang <yangyicong@hisilicon.com>"); 542 MODULE_DESCRIPTION("HiSilicon I2C Controller Driver"); 543 MODULE_LICENSE("GPL"); 544