1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * HiSilicon I2C Controller Driver for Kunpeng SoC 4 * 5 * Copyright (c) 2021 HiSilicon Technologies Co., Ltd. 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/i2c.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/units.h> 19 20 #define HISI_I2C_FRAME_CTRL 0x0000 21 #define HISI_I2C_FRAME_CTRL_SPEED_MODE GENMASK(1, 0) 22 #define HISI_I2C_FRAME_CTRL_ADDR_TEN BIT(2) 23 #define HISI_I2C_SLV_ADDR 0x0004 24 #define HISI_I2C_SLV_ADDR_VAL GENMASK(9, 0) 25 #define HISI_I2C_SLV_ADDR_GC_S_MODE BIT(10) 26 #define HISI_I2C_SLV_ADDR_GC_S_EN BIT(11) 27 #define HISI_I2C_CMD_TXDATA 0x0008 28 #define HISI_I2C_CMD_TXDATA_DATA GENMASK(7, 0) 29 #define HISI_I2C_CMD_TXDATA_RW BIT(8) 30 #define HISI_I2C_CMD_TXDATA_P_EN BIT(9) 31 #define HISI_I2C_CMD_TXDATA_SR_EN BIT(10) 32 #define HISI_I2C_RXDATA 0x000c 33 #define HISI_I2C_RXDATA_DATA GENMASK(7, 0) 34 #define HISI_I2C_SS_SCL_HCNT 0x0010 35 #define HISI_I2C_SS_SCL_LCNT 0x0014 36 #define HISI_I2C_FS_SCL_HCNT 0x0018 37 #define HISI_I2C_FS_SCL_LCNT 0x001c 38 #define HISI_I2C_HS_SCL_HCNT 0x0020 39 #define HISI_I2C_HS_SCL_LCNT 0x0024 40 #define HISI_I2C_FIFO_CTRL 0x0028 41 #define HISI_I2C_FIFO_RX_CLR BIT(0) 42 #define HISI_I2C_FIFO_TX_CLR BIT(1) 43 #define HISI_I2C_FIFO_RX_AF_THRESH GENMASK(7, 2) 44 #define HISI_I2C_FIFO_TX_AE_THRESH GENMASK(13, 8) 45 #define HISI_I2C_FIFO_STATE 0x002c 46 #define HISI_I2C_FIFO_STATE_RX_RERR BIT(0) 47 #define HISI_I2C_FIFO_STATE_RX_WERR BIT(1) 48 #define HISI_I2C_FIFO_STATE_RX_EMPTY BIT(3) 49 #define HISI_I2C_FIFO_STATE_TX_RERR BIT(6) 50 #define HISI_I2C_FIFO_STATE_TX_WERR BIT(7) 51 #define HISI_I2C_FIFO_STATE_TX_FULL BIT(11) 52 #define HISI_I2C_SDA_HOLD 0x0030 53 #define HISI_I2C_SDA_HOLD_TX GENMASK(15, 0) 54 #define HISI_I2C_SDA_HOLD_RX GENMASK(23, 16) 55 #define HISI_I2C_FS_SPK_LEN 0x0038 56 #define HISI_I2C_FS_SPK_LEN_CNT GENMASK(7, 0) 57 #define HISI_I2C_HS_SPK_LEN 0x003c 58 #define HISI_I2C_HS_SPK_LEN_CNT GENMASK(7, 0) 59 #define HISI_I2C_TX_INT_CLR 0x0040 60 #define HISI_I2C_TX_AEMPTY_INT BIT(0) 61 #define HISI_I2C_INT_MSTAT 0x0044 62 #define HISI_I2C_INT_CLR 0x0048 63 #define HISI_I2C_INT_MASK 0x004C 64 #define HISI_I2C_TRANS_STATE 0x0050 65 #define HISI_I2C_TRANS_ERR 0x0054 66 #define HISI_I2C_VERSION 0x0058 67 68 #define HISI_I2C_INT_ALL GENMASK(4, 0) 69 #define HISI_I2C_INT_TRANS_CPLT BIT(0) 70 #define HISI_I2C_INT_TRANS_ERR BIT(1) 71 #define HISI_I2C_INT_FIFO_ERR BIT(2) 72 #define HISI_I2C_INT_RX_FULL BIT(3) 73 #define HISI_I2C_INT_TX_EMPTY BIT(4) 74 #define HISI_I2C_INT_ERR \ 75 (HISI_I2C_INT_TRANS_ERR | HISI_I2C_INT_FIFO_ERR) 76 77 #define HISI_I2C_STD_SPEED_MODE 0 78 #define HISI_I2C_FAST_SPEED_MODE 1 79 #define HISI_I2C_HIGH_SPEED_MODE 2 80 81 #define HISI_I2C_TX_FIFO_DEPTH 64 82 #define HISI_I2C_RX_FIFO_DEPTH 64 83 #define HISI_I2C_TX_F_AE_THRESH 1 84 #define HISI_I2C_RX_F_AF_THRESH 60 85 86 #define NSEC_TO_CYCLES(ns, clk_rate_khz) \ 87 DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC) 88 89 struct hisi_i2c_controller { 90 struct i2c_adapter adapter; 91 void __iomem *iobase; 92 struct device *dev; 93 struct clk *clk; 94 int irq; 95 96 /* Intermediates for recording the transfer process */ 97 struct completion *completion; 98 struct i2c_msg *msgs; 99 int msg_num; 100 int msg_tx_idx; 101 int buf_tx_idx; 102 int msg_rx_idx; 103 int buf_rx_idx; 104 u16 tar_addr; 105 u32 xfer_err; 106 107 /* I2C bus configuration */ 108 struct i2c_timings t; 109 u32 clk_rate_khz; 110 u32 spk_len; 111 }; 112 113 static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask) 114 { 115 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); 116 } 117 118 static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask) 119 { 120 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); 121 } 122 123 static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) 124 { 125 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); 126 } 127 128 static void hisi_i2c_clear_tx_int(struct hisi_i2c_controller *ctlr, u32 mask) 129 { 130 writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR); 131 } 132 133 static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) 134 { 135 u32 int_err = ctlr->xfer_err, reg; 136 137 if (int_err & HISI_I2C_INT_FIFO_ERR) { 138 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 139 140 if (reg & HISI_I2C_FIFO_STATE_RX_RERR) 141 dev_err(ctlr->dev, "rx fifo error read\n"); 142 143 if (reg & HISI_I2C_FIFO_STATE_RX_WERR) 144 dev_err(ctlr->dev, "rx fifo error write\n"); 145 146 if (reg & HISI_I2C_FIFO_STATE_TX_RERR) 147 dev_err(ctlr->dev, "tx fifo error read\n"); 148 149 if (reg & HISI_I2C_FIFO_STATE_TX_WERR) 150 dev_err(ctlr->dev, "tx fifo error write\n"); 151 } 152 } 153 154 static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) 155 { 156 struct i2c_msg *msg = ctlr->msgs; 157 u32 reg; 158 159 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 160 reg &= ~HISI_I2C_FRAME_CTRL_ADDR_TEN; 161 if (msg->flags & I2C_M_TEN) 162 reg |= HISI_I2C_FRAME_CTRL_ADDR_TEN; 163 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 164 165 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); 166 reg &= ~HISI_I2C_SLV_ADDR_VAL; 167 reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr); 168 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); 169 170 reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); 171 reg |= HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR; 172 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 173 reg &= ~(HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR); 174 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 175 176 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 177 hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); 178 hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL); 179 180 return 0; 181 } 182 183 static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr) 184 { 185 ctlr->msg_num = 0; 186 ctlr->xfer_err = 0; 187 ctlr->msg_tx_idx = 0; 188 ctlr->msg_rx_idx = 0; 189 ctlr->buf_tx_idx = 0; 190 ctlr->buf_rx_idx = 0; 191 } 192 193 /* 194 * Initialize the transfer information and start the I2C bus transfer. 195 * We only configure the transfer and do some pre/post works here, and 196 * wait for the transfer done. The major transfer process is performed 197 * in the IRQ handler. 198 */ 199 static int hisi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 200 int num) 201 { 202 struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); 203 DECLARE_COMPLETION_ONSTACK(done); 204 int ret = num; 205 206 hisi_i2c_reset_xfer(ctlr); 207 ctlr->completion = &done; 208 ctlr->msg_num = num; 209 ctlr->msgs = msgs; 210 211 hisi_i2c_start_xfer(ctlr); 212 213 if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) { 214 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 215 synchronize_irq(ctlr->irq); 216 i2c_recover_bus(&ctlr->adapter); 217 dev_err(ctlr->dev, "bus transfer timeout\n"); 218 ret = -EIO; 219 } 220 221 if (ctlr->xfer_err) { 222 hisi_i2c_handle_errors(ctlr); 223 ret = -EIO; 224 } 225 226 hisi_i2c_reset_xfer(ctlr); 227 ctlr->completion = NULL; 228 229 return ret; 230 } 231 232 static u32 hisi_i2c_functionality(struct i2c_adapter *adap) 233 { 234 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 235 } 236 237 static const struct i2c_algorithm hisi_i2c_algo = { 238 .xfer = hisi_i2c_xfer, 239 .functionality = hisi_i2c_functionality, 240 }; 241 242 static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) 243 { 244 struct i2c_msg *cur_msg; 245 u32 fifo_state; 246 247 while (ctlr->msg_rx_idx < ctlr->msg_num) { 248 cur_msg = ctlr->msgs + ctlr->msg_rx_idx; 249 250 if (!(cur_msg->flags & I2C_M_RD)) { 251 ctlr->msg_rx_idx++; 252 continue; 253 } 254 255 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 256 while (!(fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) && 257 ctlr->buf_rx_idx < cur_msg->len) { 258 cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA); 259 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 260 } 261 262 if (ctlr->buf_rx_idx == cur_msg->len) { 263 ctlr->buf_rx_idx = 0; 264 ctlr->msg_rx_idx++; 265 } 266 267 if (fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) 268 break; 269 } 270 271 return 0; 272 } 273 274 static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) 275 { 276 int max_write = HISI_I2C_TX_FIFO_DEPTH - HISI_I2C_TX_F_AE_THRESH; 277 bool need_restart = false, last_msg; 278 struct i2c_msg *cur_msg; 279 u32 cmd, fifo_state; 280 281 while (ctlr->msg_tx_idx < ctlr->msg_num) { 282 cur_msg = ctlr->msgs + ctlr->msg_tx_idx; 283 last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1); 284 285 /* Signal the SR bit when we start transferring a new message */ 286 if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx) 287 need_restart = true; 288 289 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 290 while (!(fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) && 291 ctlr->buf_tx_idx < cur_msg->len && max_write) { 292 cmd = 0; 293 294 if (need_restart) { 295 cmd |= HISI_I2C_CMD_TXDATA_SR_EN; 296 need_restart = false; 297 } 298 299 /* Signal the STOP bit at the last frame of the last message */ 300 if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg) 301 cmd |= HISI_I2C_CMD_TXDATA_P_EN; 302 303 if (cur_msg->flags & I2C_M_RD) 304 cmd |= HISI_I2C_CMD_TXDATA_RW; 305 else 306 cmd |= FIELD_PREP(HISI_I2C_CMD_TXDATA_DATA, 307 cur_msg->buf[ctlr->buf_tx_idx]); 308 309 writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA); 310 ctlr->buf_tx_idx++; 311 max_write--; 312 313 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 314 } 315 316 /* Update the transfer index after per message transfer is done. */ 317 if (ctlr->buf_tx_idx == cur_msg->len) { 318 ctlr->buf_tx_idx = 0; 319 ctlr->msg_tx_idx++; 320 } 321 322 if ((fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) || 323 max_write == 0) 324 break; 325 } 326 327 /* 328 * Disable the TX_EMPTY interrupt after finishing all the messages to 329 * avoid overwhelming the CPU. 330 */ 331 if (ctlr->msg_tx_idx == ctlr->msg_num) 332 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_TX_EMPTY); 333 334 hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); 335 } 336 337 static irqreturn_t hisi_i2c_irq(int irq, void *context) 338 { 339 struct hisi_i2c_controller *ctlr = context; 340 u32 int_stat; 341 342 /* 343 * Don't handle the interrupt if cltr->completion is NULL. We may 344 * reach here because the interrupt is spurious or the transfer is 345 * started by another port (e.g. firmware) rather than us. 346 */ 347 if (!ctlr->completion) 348 return IRQ_NONE; 349 350 int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); 351 hisi_i2c_clear_int(ctlr, int_stat); 352 if (!(int_stat & HISI_I2C_INT_ALL)) 353 return IRQ_NONE; 354 355 if (int_stat & HISI_I2C_INT_TX_EMPTY) 356 hisi_i2c_xfer_msg(ctlr); 357 358 if (int_stat & HISI_I2C_INT_ERR) { 359 ctlr->xfer_err = int_stat; 360 goto out; 361 } 362 363 /* Drain the rx fifo before finish the transfer */ 364 if (int_stat & (HISI_I2C_INT_TRANS_CPLT | HISI_I2C_INT_RX_FULL)) 365 hisi_i2c_read_rx_fifo(ctlr); 366 367 out: 368 /* 369 * Only use TRANS_CPLT to indicate the completion. On error cases we'll 370 * get two interrupts, INT_ERR first then TRANS_CPLT. 371 */ 372 if (int_stat & HISI_I2C_INT_TRANS_CPLT) { 373 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 374 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 375 hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); 376 complete(ctlr->completion); 377 } 378 379 return IRQ_HANDLED; 380 } 381 382 /* 383 * Helper function for calculating and configuring the HIGH and LOW 384 * periods of SCL clock. The caller will pass the ratio of the 385 * counts (divide / divisor) according to the target speed mode, 386 * and the target registers. 387 */ 388 static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr, 389 u32 divide, u32 divisor, 390 u32 reg_hcnt, u32 reg_lcnt) 391 { 392 u32 total_cnt, t_scl_hcnt, t_scl_lcnt, scl_fall_cnt, scl_rise_cnt; 393 u32 scl_hcnt, scl_lcnt; 394 395 /* Total SCL clock cycles per speed period */ 396 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); 397 /* Total HIGH level SCL clock cycles including edges */ 398 t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor); 399 /* Total LOW level SCL clock cycles including edges */ 400 t_scl_lcnt = total_cnt - t_scl_hcnt; 401 /* Fall edge SCL clock cycles */ 402 scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); 403 /* Rise edge SCL clock cycles */ 404 scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); 405 406 /* Calculated HIGH and LOW periods of SCL clock */ 407 scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt; 408 scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt; 409 410 writel(scl_hcnt, ctlr->iobase + reg_hcnt); 411 writel(scl_lcnt, ctlr->iobase + reg_lcnt); 412 } 413 414 static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr) 415 { 416 u32 reg, sda_hold_cnt, speed_mode; 417 418 i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true); 419 ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); 420 421 switch (ctlr->t.bus_freq_hz) { 422 case I2C_MAX_FAST_MODE_FREQ: 423 speed_mode = HISI_I2C_FAST_SPEED_MODE; 424 hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT); 425 break; 426 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 427 speed_mode = HISI_I2C_HIGH_SPEED_MODE; 428 hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT); 429 break; 430 case I2C_MAX_STANDARD_MODE_FREQ: 431 default: 432 speed_mode = HISI_I2C_STD_SPEED_MODE; 433 434 /* For default condition force the bus speed to standard mode. */ 435 ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 436 hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT); 437 break; 438 } 439 440 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 441 reg &= ~HISI_I2C_FRAME_CTRL_SPEED_MODE; 442 reg |= FIELD_PREP(HISI_I2C_FRAME_CTRL_SPEED_MODE, speed_mode); 443 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 444 445 sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); 446 447 reg = FIELD_PREP(HISI_I2C_SDA_HOLD_TX, sda_hold_cnt); 448 writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); 449 450 writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN); 451 452 reg = FIELD_PREP(HISI_I2C_FIFO_RX_AF_THRESH, HISI_I2C_RX_F_AF_THRESH); 453 reg |= FIELD_PREP(HISI_I2C_FIFO_TX_AE_THRESH, HISI_I2C_TX_F_AE_THRESH); 454 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 455 } 456 457 static int hisi_i2c_probe(struct platform_device *pdev) 458 { 459 struct hisi_i2c_controller *ctlr; 460 struct device *dev = &pdev->dev; 461 struct i2c_adapter *adapter; 462 u64 clk_rate_hz; 463 u32 hw_version; 464 int ret; 465 466 ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL); 467 if (!ctlr) 468 return -ENOMEM; 469 470 ctlr->iobase = devm_platform_ioremap_resource(pdev, 0); 471 if (IS_ERR(ctlr->iobase)) 472 return PTR_ERR(ctlr->iobase); 473 474 ctlr->irq = platform_get_irq(pdev, 0); 475 if (ctlr->irq < 0) 476 return ctlr->irq; 477 478 ctlr->dev = dev; 479 480 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 481 482 ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr); 483 if (ret) 484 return ret; 485 486 ctlr->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 487 if (IS_ERR_OR_NULL(ctlr->clk)) { 488 ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz); 489 if (ret) 490 return dev_err_probe(dev, ret, "failed to get clock frequency\n"); 491 } else { 492 clk_rate_hz = clk_get_rate(ctlr->clk); 493 } 494 495 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); 496 497 hisi_i2c_configure_bus(ctlr); 498 499 adapter = &ctlr->adapter; 500 snprintf(adapter->name, sizeof(adapter->name), 501 "HiSilicon I2C Controller %s", dev_name(dev)); 502 adapter->owner = THIS_MODULE; 503 adapter->algo = &hisi_i2c_algo; 504 adapter->dev.parent = dev; 505 i2c_set_adapdata(adapter, ctlr); 506 507 ret = devm_i2c_add_adapter(dev, adapter); 508 if (ret) 509 return ret; 510 511 hw_version = readl(ctlr->iobase + HISI_I2C_VERSION); 512 dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n", 513 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version); 514 515 return 0; 516 } 517 518 static const struct acpi_device_id hisi_i2c_acpi_ids[] = { 519 { "HISI03D1", 0 }, 520 { } 521 }; 522 MODULE_DEVICE_TABLE(acpi, hisi_i2c_acpi_ids); 523 524 static const struct of_device_id hisi_i2c_dts_ids[] = { 525 { .compatible = "hisilicon,ascend910-i2c", }, 526 { } 527 }; 528 MODULE_DEVICE_TABLE(of, hisi_i2c_dts_ids); 529 530 static struct platform_driver hisi_i2c_driver = { 531 .probe = hisi_i2c_probe, 532 .driver = { 533 .name = "hisi-i2c", 534 .acpi_match_table = hisi_i2c_acpi_ids, 535 .of_match_table = hisi_i2c_dts_ids, 536 }, 537 }; 538 module_platform_driver(hisi_i2c_driver); 539 540 MODULE_AUTHOR("Yicong Yang <yangyicong@hisilicon.com>"); 541 MODULE_DESCRIPTION("HiSilicon I2C Controller Driver"); 542 MODULE_LICENSE("GPL"); 543