1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare I2C adapter driver (slave only). 4 * 5 * Based on the Synopsys DesignWare I2C adapter driver (master). 6 * 7 * Copyright (C) 2016 Synopsys Inc. 8 */ 9 10 #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW" 11 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/i2c.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 22 #include "i2c-designware-core.h" 23 24 static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev) 25 { 26 /* Configure Tx/Rx FIFO threshold levels. */ 27 regmap_write(dev->map, DW_IC_TX_TL, 0); 28 regmap_write(dev->map, DW_IC_RX_TL, 0); 29 30 /* Configure the I2C slave. */ 31 regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); 32 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); 33 } 34 35 /** 36 * i2c_dw_init_slave() - Initialize the DesignWare i2c slave hardware 37 * @dev: device private data 38 * 39 * This function configures and enables the I2C in slave mode. 40 * This function is called during I2C init function, and in case of timeout at 41 * run time. 42 * 43 * Return: 0 on success, or negative errno otherwise. 44 */ 45 static int i2c_dw_init_slave(struct dw_i2c_dev *dev) 46 { 47 int ret; 48 49 ret = i2c_dw_acquire_lock(dev); 50 if (ret) 51 return ret; 52 53 /* Disable the adapter. */ 54 __i2c_dw_disable(dev); 55 56 /* Write SDA hold time if supported */ 57 if (dev->sda_hold_time) 58 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); 59 60 i2c_dw_configure_fifo_slave(dev); 61 i2c_dw_release_lock(dev); 62 63 return 0; 64 } 65 66 static int i2c_dw_reg_slave(struct i2c_client *slave) 67 { 68 struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter); 69 70 if (dev->slave) 71 return -EBUSY; 72 if (slave->flags & I2C_CLIENT_TEN) 73 return -EAFNOSUPPORT; 74 pm_runtime_get_sync(dev->dev); 75 76 /* 77 * Set slave address in the IC_SAR register, 78 * the address to which the DW_apb_i2c responds. 79 */ 80 __i2c_dw_disable_nowait(dev); 81 regmap_write(dev->map, DW_IC_SAR, slave->addr); 82 dev->slave = slave; 83 84 __i2c_dw_enable(dev); 85 86 dev->status = 0; 87 88 return 0; 89 } 90 91 static int i2c_dw_unreg_slave(struct i2c_client *slave) 92 { 93 struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter); 94 95 regmap_write(dev->map, DW_IC_INTR_MASK, 0); 96 i2c_dw_disable(dev); 97 synchronize_irq(dev->irq); 98 dev->slave = NULL; 99 pm_runtime_put(dev->dev); 100 101 return 0; 102 } 103 104 static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev *dev) 105 { 106 unsigned int stat, dummy; 107 108 /* 109 * The IC_INTR_STAT register just indicates "enabled" interrupts. 110 * The unmasked raw version of interrupt status bits is available 111 * in the IC_RAW_INTR_STAT register. 112 * 113 * That is, 114 * stat = readl(IC_INTR_STAT); 115 * equals to, 116 * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); 117 * 118 * The raw version might be useful for debugging purposes. 119 */ 120 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); 121 122 /* 123 * Do not use the IC_CLR_INTR register to clear interrupts, or 124 * you'll miss some interrupts, triggered during the period from 125 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). 126 * 127 * Instead, use the separately-prepared IC_CLR_* registers. 128 */ 129 if (stat & DW_IC_INTR_TX_ABRT) 130 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); 131 if (stat & DW_IC_INTR_RX_UNDER) 132 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); 133 if (stat & DW_IC_INTR_RX_OVER) 134 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); 135 if (stat & DW_IC_INTR_TX_OVER) 136 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); 137 if (stat & DW_IC_INTR_RX_DONE) 138 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); 139 if (stat & DW_IC_INTR_ACTIVITY) 140 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); 141 if (stat & DW_IC_INTR_STOP_DET) 142 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); 143 if (stat & DW_IC_INTR_START_DET) 144 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); 145 if (stat & DW_IC_INTR_GEN_CALL) 146 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); 147 148 return stat; 149 } 150 151 /* 152 * Interrupt service routine. This gets called whenever an I2C slave interrupt 153 * occurs. 154 */ 155 static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id) 156 { 157 struct dw_i2c_dev *dev = dev_id; 158 unsigned int raw_stat, stat, enabled, tmp; 159 u8 val = 0, slave_activity; 160 161 regmap_read(dev->map, DW_IC_ENABLE, &enabled); 162 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_stat); 163 regmap_read(dev->map, DW_IC_STATUS, &tmp); 164 slave_activity = ((tmp & DW_IC_STATUS_SLAVE_ACTIVITY) >> 6); 165 166 if (!enabled || !(raw_stat & ~DW_IC_INTR_ACTIVITY) || !dev->slave) 167 return IRQ_NONE; 168 169 stat = i2c_dw_read_clear_intrbits_slave(dev); 170 dev_dbg(dev->dev, 171 "%#x STATUS SLAVE_ACTIVITY=%#x : RAW_INTR_STAT=%#x : INTR_STAT=%#x\n", 172 enabled, slave_activity, raw_stat, stat); 173 174 if (stat & DW_IC_INTR_RX_FULL) { 175 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { 176 dev->status |= STATUS_WRITE_IN_PROGRESS; 177 dev->status &= ~STATUS_READ_IN_PROGRESS; 178 i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, 179 &val); 180 } 181 182 do { 183 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); 184 if (tmp & DW_IC_DATA_CMD_FIRST_DATA_BYTE) 185 i2c_slave_event(dev->slave, 186 I2C_SLAVE_WRITE_REQUESTED, 187 &val); 188 val = tmp; 189 i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED, 190 &val); 191 regmap_read(dev->map, DW_IC_STATUS, &tmp); 192 } while (tmp & DW_IC_STATUS_RFNE); 193 } 194 195 if (stat & DW_IC_INTR_RD_REQ) { 196 if (slave_activity) { 197 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp); 198 199 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { 200 i2c_slave_event(dev->slave, 201 I2C_SLAVE_READ_REQUESTED, 202 &val); 203 dev->status |= STATUS_READ_IN_PROGRESS; 204 dev->status &= ~STATUS_WRITE_IN_PROGRESS; 205 } else { 206 i2c_slave_event(dev->slave, 207 I2C_SLAVE_READ_PROCESSED, 208 &val); 209 } 210 regmap_write(dev->map, DW_IC_DATA_CMD, val); 211 } 212 } 213 214 if (stat & DW_IC_INTR_STOP_DET) 215 i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val); 216 217 return IRQ_HANDLED; 218 } 219 220 static const struct i2c_algorithm i2c_dw_algo = { 221 .functionality = i2c_dw_func, 222 .reg_slave = i2c_dw_reg_slave, 223 .unreg_slave = i2c_dw_unreg_slave, 224 }; 225 226 void i2c_dw_configure_slave(struct dw_i2c_dev *dev) 227 { 228 dev->functionality = I2C_FUNC_SLAVE; 229 230 dev->slave_cfg = DW_IC_CON_RX_FIFO_FULL_HLD_CTRL | 231 DW_IC_CON_RESTART_EN | DW_IC_CON_STOP_DET_IFADDRESSED; 232 233 dev->mode = DW_IC_SLAVE; 234 } 235 EXPORT_SYMBOL_GPL(i2c_dw_configure_slave); 236 237 int i2c_dw_probe_slave(struct dw_i2c_dev *dev) 238 { 239 struct i2c_adapter *adap = &dev->adapter; 240 int ret; 241 242 dev->init = i2c_dw_init_slave; 243 244 ret = i2c_dw_init_regmap(dev); 245 if (ret) 246 return ret; 247 248 ret = i2c_dw_set_sda_hold(dev); 249 if (ret) 250 return ret; 251 252 ret = i2c_dw_set_fifo_size(dev); 253 if (ret) 254 return ret; 255 256 ret = dev->init(dev); 257 if (ret) 258 return ret; 259 260 snprintf(adap->name, sizeof(adap->name), 261 "Synopsys DesignWare I2C Slave adapter"); 262 adap->retries = 3; 263 adap->algo = &i2c_dw_algo; 264 adap->dev.parent = dev->dev; 265 i2c_set_adapdata(adap, dev); 266 267 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr_slave, 268 IRQF_SHARED, dev_name(dev->dev), dev); 269 if (ret) { 270 dev_err(dev->dev, "failure requesting IRQ %i: %d\n", 271 dev->irq, ret); 272 return ret; 273 } 274 275 ret = i2c_add_numbered_adapter(adap); 276 if (ret) 277 dev_err(dev->dev, "failure adding adapter: %d\n", ret); 278 279 return ret; 280 } 281 EXPORT_SYMBOL_GPL(i2c_dw_probe_slave); 282 283 MODULE_AUTHOR("Luis Oliveira <lolivei@synopsys.com>"); 284 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus slave adapter"); 285 MODULE_LICENSE("GPL v2"); 286 MODULE_IMPORT_NS("I2C_DW_COMMON"); 287