1 /* 2 * Synopsys DesignWare I2C adapter driver (master only). 3 * 4 * Based on the TI DAVINCI I2C adapter driver. 5 * 6 * Copyright (C) 2006 Texas Instruments. 7 * Copyright (C) 2007 MontaVista Software Inc. 8 * Copyright (C) 2009 Provigent Ltd. 9 * Copyright (C) 2011, 2015 Intel Corporation. 10 * 11 * ---------------------------------------------------------------------------- 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * ---------------------------------------------------------------------------- 23 * 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/delay.h> 29 #include <linux/i2c.h> 30 #include <linux/errno.h> 31 #include <linux/sched.h> 32 #include <linux/err.h> 33 #include <linux/interrupt.h> 34 #include <linux/io.h> 35 #include <linux/slab.h> 36 #include <linux/pci.h> 37 #include <linux/pm_runtime.h> 38 #include "i2c-designware-core.h" 39 40 #define DRIVER_NAME "i2c-designware-pci" 41 42 enum dw_pci_ctl_id_t { 43 medfield_0, 44 medfield_1, 45 medfield_2, 46 medfield_3, 47 medfield_4, 48 medfield_5, 49 50 baytrail, 51 haswell, 52 }; 53 54 struct dw_scl_sda_cfg { 55 u32 ss_hcnt; 56 u32 fs_hcnt; 57 u32 ss_lcnt; 58 u32 fs_lcnt; 59 u32 sda_hold; 60 }; 61 62 struct dw_pci_controller { 63 u32 bus_num; 64 u32 bus_cfg; 65 u32 tx_fifo_depth; 66 u32 rx_fifo_depth; 67 u32 clk_khz; 68 u32 functionality; 69 struct dw_scl_sda_cfg *scl_sda_cfg; 70 }; 71 72 #define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \ 73 DW_IC_CON_SLAVE_DISABLE | \ 74 DW_IC_CON_RESTART_EN) 75 76 #define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ 77 I2C_FUNC_SMBUS_BYTE | \ 78 I2C_FUNC_SMBUS_BYTE_DATA | \ 79 I2C_FUNC_SMBUS_WORD_DATA | \ 80 I2C_FUNC_SMBUS_I2C_BLOCK) 81 82 /* BayTrail HCNT/LCNT/SDA hold time */ 83 static struct dw_scl_sda_cfg byt_config = { 84 .ss_hcnt = 0x200, 85 .fs_hcnt = 0x55, 86 .ss_lcnt = 0x200, 87 .fs_lcnt = 0x99, 88 .sda_hold = 0x6, 89 }; 90 91 /* Haswell HCNT/LCNT/SDA hold time */ 92 static struct dw_scl_sda_cfg hsw_config = { 93 .ss_hcnt = 0x01b0, 94 .fs_hcnt = 0x48, 95 .ss_lcnt = 0x01fb, 96 .fs_lcnt = 0xa0, 97 .sda_hold = 0x9, 98 }; 99 100 static struct dw_pci_controller dw_pci_controllers[] = { 101 [medfield_0] = { 102 .bus_num = 0, 103 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 104 .tx_fifo_depth = 32, 105 .rx_fifo_depth = 32, 106 .clk_khz = 25000, 107 }, 108 [medfield_1] = { 109 .bus_num = 1, 110 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 111 .tx_fifo_depth = 32, 112 .rx_fifo_depth = 32, 113 .clk_khz = 25000, 114 }, 115 [medfield_2] = { 116 .bus_num = 2, 117 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 118 .tx_fifo_depth = 32, 119 .rx_fifo_depth = 32, 120 .clk_khz = 25000, 121 }, 122 [medfield_3] = { 123 .bus_num = 3, 124 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD, 125 .tx_fifo_depth = 32, 126 .rx_fifo_depth = 32, 127 .clk_khz = 25000, 128 }, 129 [medfield_4] = { 130 .bus_num = 4, 131 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 132 .tx_fifo_depth = 32, 133 .rx_fifo_depth = 32, 134 .clk_khz = 25000, 135 }, 136 [medfield_5] = { 137 .bus_num = 5, 138 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 139 .tx_fifo_depth = 32, 140 .rx_fifo_depth = 32, 141 .clk_khz = 25000, 142 }, 143 [baytrail] = { 144 .bus_num = -1, 145 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 146 .tx_fifo_depth = 32, 147 .rx_fifo_depth = 32, 148 .functionality = I2C_FUNC_10BIT_ADDR, 149 .scl_sda_cfg = &byt_config, 150 }, 151 [haswell] = { 152 .bus_num = -1, 153 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 154 .tx_fifo_depth = 32, 155 .rx_fifo_depth = 32, 156 .functionality = I2C_FUNC_10BIT_ADDR, 157 .scl_sda_cfg = &hsw_config, 158 }, 159 }; 160 161 static struct i2c_algorithm i2c_dw_algo = { 162 .master_xfer = i2c_dw_xfer, 163 .functionality = i2c_dw_func, 164 }; 165 166 #ifdef CONFIG_PM 167 static int i2c_dw_pci_suspend(struct device *dev) 168 { 169 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 170 171 i2c_dw_disable(pci_get_drvdata(pdev)); 172 return 0; 173 } 174 175 static int i2c_dw_pci_resume(struct device *dev) 176 { 177 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 178 179 return i2c_dw_init(pci_get_drvdata(pdev)); 180 } 181 #endif 182 183 static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend, 184 i2c_dw_pci_resume, NULL); 185 186 static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev) 187 { 188 return dev->controller->clk_khz; 189 } 190 191 static int i2c_dw_pci_probe(struct pci_dev *pdev, 192 const struct pci_device_id *id) 193 { 194 struct dw_i2c_dev *dev; 195 struct i2c_adapter *adap; 196 int r; 197 struct dw_pci_controller *controller; 198 struct dw_scl_sda_cfg *cfg; 199 200 if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) { 201 dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__, 202 id->driver_data); 203 return -EINVAL; 204 } 205 206 controller = &dw_pci_controllers[id->driver_data]; 207 208 r = pcim_enable_device(pdev); 209 if (r) { 210 dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n", 211 r); 212 return r; 213 } 214 215 r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev)); 216 if (r) { 217 dev_err(&pdev->dev, "I/O memory remapping failed\n"); 218 return r; 219 } 220 221 dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL); 222 if (!dev) 223 return -ENOMEM; 224 225 init_completion(&dev->cmd_complete); 226 mutex_init(&dev->lock); 227 dev->clk = NULL; 228 dev->controller = controller; 229 dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz; 230 dev->base = pcim_iomap_table(pdev)[0]; 231 dev->dev = &pdev->dev; 232 dev->functionality = controller->functionality | 233 DW_DEFAULT_FUNCTIONALITY; 234 235 dev->master_cfg = controller->bus_cfg; 236 if (controller->scl_sda_cfg) { 237 cfg = controller->scl_sda_cfg; 238 dev->ss_hcnt = cfg->ss_hcnt; 239 dev->fs_hcnt = cfg->fs_hcnt; 240 dev->ss_lcnt = cfg->ss_lcnt; 241 dev->fs_lcnt = cfg->fs_lcnt; 242 dev->sda_hold_time = cfg->sda_hold; 243 } 244 245 pci_set_drvdata(pdev, dev); 246 247 dev->tx_fifo_depth = controller->tx_fifo_depth; 248 dev->rx_fifo_depth = controller->rx_fifo_depth; 249 r = i2c_dw_init(dev); 250 if (r) 251 return r; 252 253 adap = &dev->adapter; 254 i2c_set_adapdata(adap, dev); 255 adap->owner = THIS_MODULE; 256 adap->class = 0; 257 adap->algo = &i2c_dw_algo; 258 adap->dev.parent = &pdev->dev; 259 adap->nr = controller->bus_num; 260 261 snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci"); 262 263 r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED, 264 adap->name, dev); 265 if (r) { 266 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); 267 return r; 268 } 269 270 i2c_dw_disable_int(dev); 271 i2c_dw_clear_int(dev); 272 r = i2c_add_numbered_adapter(adap); 273 if (r) { 274 dev_err(&pdev->dev, "failure adding adapter\n"); 275 return r; 276 } 277 278 pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); 279 pm_runtime_use_autosuspend(&pdev->dev); 280 pm_runtime_put_autosuspend(&pdev->dev); 281 pm_runtime_allow(&pdev->dev); 282 283 return 0; 284 } 285 286 static void i2c_dw_pci_remove(struct pci_dev *pdev) 287 { 288 struct dw_i2c_dev *dev = pci_get_drvdata(pdev); 289 290 i2c_dw_disable(dev); 291 pm_runtime_forbid(&pdev->dev); 292 pm_runtime_get_noresume(&pdev->dev); 293 294 i2c_del_adapter(&dev->adapter); 295 } 296 297 /* work with hotplug and coldplug */ 298 MODULE_ALIAS("i2c_designware-pci"); 299 300 static const struct pci_device_id i2_designware_pci_ids[] = { 301 /* Medfield */ 302 { PCI_VDEVICE(INTEL, 0x0817), medfield_3 }, 303 { PCI_VDEVICE(INTEL, 0x0818), medfield_4 }, 304 { PCI_VDEVICE(INTEL, 0x0819), medfield_5 }, 305 { PCI_VDEVICE(INTEL, 0x082C), medfield_0 }, 306 { PCI_VDEVICE(INTEL, 0x082D), medfield_1 }, 307 { PCI_VDEVICE(INTEL, 0x082E), medfield_2 }, 308 /* Baytrail */ 309 { PCI_VDEVICE(INTEL, 0x0F41), baytrail }, 310 { PCI_VDEVICE(INTEL, 0x0F42), baytrail }, 311 { PCI_VDEVICE(INTEL, 0x0F43), baytrail }, 312 { PCI_VDEVICE(INTEL, 0x0F44), baytrail }, 313 { PCI_VDEVICE(INTEL, 0x0F45), baytrail }, 314 { PCI_VDEVICE(INTEL, 0x0F46), baytrail }, 315 { PCI_VDEVICE(INTEL, 0x0F47), baytrail }, 316 /* Haswell */ 317 { PCI_VDEVICE(INTEL, 0x9c61), haswell }, 318 { PCI_VDEVICE(INTEL, 0x9c62), haswell }, 319 /* Braswell / Cherrytrail */ 320 { PCI_VDEVICE(INTEL, 0x22C1), baytrail }, 321 { PCI_VDEVICE(INTEL, 0x22C2), baytrail }, 322 { PCI_VDEVICE(INTEL, 0x22C3), baytrail }, 323 { PCI_VDEVICE(INTEL, 0x22C4), baytrail }, 324 { PCI_VDEVICE(INTEL, 0x22C5), baytrail }, 325 { PCI_VDEVICE(INTEL, 0x22C6), baytrail }, 326 { PCI_VDEVICE(INTEL, 0x22C7), baytrail }, 327 { 0,} 328 }; 329 MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids); 330 331 static struct pci_driver dw_i2c_driver = { 332 .name = DRIVER_NAME, 333 .id_table = i2_designware_pci_ids, 334 .probe = i2c_dw_pci_probe, 335 .remove = i2c_dw_pci_remove, 336 .driver = { 337 .pm = &i2c_dw_pm_ops, 338 }, 339 }; 340 341 module_pci_driver(dw_i2c_driver); 342 343 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); 344 MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter"); 345 MODULE_LICENSE("GPL"); 346