xref: /linux/drivers/i2c/busses/i2c-designware-master.c (revision de73b5a97bba1538f065e1e90d8eeac399db7510)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Synopsys DesignWare I2C adapter driver (master only).
4  *
5  * Based on the TI DAVINCI I2C adapter driver.
6  *
7  * Copyright (C) 2006 Texas Instruments.
8  * Copyright (C) 2007 MontaVista Software Inc.
9  * Copyright (C) 2009 Provigent Ltd.
10  */
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/export.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23 
24 #include "i2c-designware-core.h"
25 
26 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
27 {
28 	/* Configure Tx/Rx FIFO threshold levels */
29 	regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
30 	regmap_write(dev->map, DW_IC_RX_TL, 0);
31 
32 	/* Configure the I2C master */
33 	regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
34 }
35 
36 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
37 {
38 	const char *mode_str, *fp_str = "";
39 	u32 comp_param1;
40 	u32 sda_falling_time, scl_falling_time;
41 	struct i2c_timings *t = &dev->timings;
42 	u32 ic_clk;
43 	int ret;
44 
45 	ret = i2c_dw_acquire_lock(dev);
46 	if (ret)
47 		return ret;
48 
49 	ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
50 	i2c_dw_release_lock(dev);
51 	if (ret)
52 		return ret;
53 
54 	/* Set standard and fast speed dividers for high/low periods */
55 	sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
56 	scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
57 
58 	/* Calculate SCL timing parameters for standard mode if not set */
59 	if (!dev->ss_hcnt || !dev->ss_lcnt) {
60 		ic_clk = i2c_dw_clk_rate(dev);
61 		dev->ss_hcnt =
62 			i2c_dw_scl_hcnt(ic_clk,
63 					4000,	/* tHD;STA = tHIGH = 4.0 us */
64 					sda_falling_time,
65 					0,	/* 0: DW default, 1: Ideal */
66 					0);	/* No offset */
67 		dev->ss_lcnt =
68 			i2c_dw_scl_lcnt(ic_clk,
69 					4700,	/* tLOW = 4.7 us */
70 					scl_falling_time,
71 					0);	/* No offset */
72 	}
73 	dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
74 		dev->ss_hcnt, dev->ss_lcnt);
75 
76 	/*
77 	 * Set SCL timing parameters for fast mode or fast mode plus. Only
78 	 * difference is the timing parameter values since the registers are
79 	 * the same.
80 	 */
81 	if (t->bus_freq_hz == 1000000) {
82 		/*
83 		 * Check are Fast Mode Plus parameters available. Calculate
84 		 * SCL timing parameters for Fast Mode Plus if not set.
85 		 */
86 		if (dev->fp_hcnt && dev->fp_lcnt) {
87 			dev->fs_hcnt = dev->fp_hcnt;
88 			dev->fs_lcnt = dev->fp_lcnt;
89 		} else {
90 			ic_clk = i2c_dw_clk_rate(dev);
91 			dev->fs_hcnt =
92 				i2c_dw_scl_hcnt(ic_clk,
93 						260,	/* tHIGH = 260 ns */
94 						sda_falling_time,
95 						0,	/* DW default */
96 						0);	/* No offset */
97 			dev->fs_lcnt =
98 				i2c_dw_scl_lcnt(ic_clk,
99 						500,	/* tLOW = 500 ns */
100 						scl_falling_time,
101 						0);	/* No offset */
102 		}
103 		fp_str = " Plus";
104 	}
105 	/*
106 	 * Calculate SCL timing parameters for fast mode if not set. They are
107 	 * needed also in high speed mode.
108 	 */
109 	if (!dev->fs_hcnt || !dev->fs_lcnt) {
110 		ic_clk = i2c_dw_clk_rate(dev);
111 		dev->fs_hcnt =
112 			i2c_dw_scl_hcnt(ic_clk,
113 					600,	/* tHD;STA = tHIGH = 0.6 us */
114 					sda_falling_time,
115 					0,	/* 0: DW default, 1: Ideal */
116 					0);	/* No offset */
117 		dev->fs_lcnt =
118 			i2c_dw_scl_lcnt(ic_clk,
119 					1300,	/* tLOW = 1.3 us */
120 					scl_falling_time,
121 					0);	/* No offset */
122 	}
123 	dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
124 		fp_str, dev->fs_hcnt, dev->fs_lcnt);
125 
126 	/* Check is high speed possible and fall back to fast mode if not */
127 	if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
128 		DW_IC_CON_SPEED_HIGH) {
129 		if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
130 			!= DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
131 			dev_err(dev->dev, "High Speed not supported!\n");
132 			dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
133 			dev->master_cfg |= DW_IC_CON_SPEED_FAST;
134 			dev->hs_hcnt = 0;
135 			dev->hs_lcnt = 0;
136 		} else if (!dev->hs_hcnt || !dev->hs_lcnt) {
137 			ic_clk = i2c_dw_clk_rate(dev);
138 			dev->hs_hcnt =
139 				i2c_dw_scl_hcnt(ic_clk,
140 						160,	/* tHIGH = 160 ns */
141 						sda_falling_time,
142 						0,	/* DW default */
143 						0);	/* No offset */
144 			dev->hs_lcnt =
145 				i2c_dw_scl_lcnt(ic_clk,
146 						320,	/* tLOW = 320 ns */
147 						scl_falling_time,
148 						0);	/* No offset */
149 		}
150 		dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
151 			dev->hs_hcnt, dev->hs_lcnt);
152 	}
153 
154 	ret = i2c_dw_set_sda_hold(dev);
155 	if (ret)
156 		goto out;
157 
158 	switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) {
159 	case DW_IC_CON_SPEED_STD:
160 		mode_str = "Standard Mode";
161 		break;
162 	case DW_IC_CON_SPEED_HIGH:
163 		mode_str = "High Speed Mode";
164 		break;
165 	default:
166 		mode_str = "Fast Mode";
167 	}
168 	dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str);
169 
170 out:
171 	return ret;
172 }
173 
174 /**
175  * i2c_dw_init() - Initialize the designware I2C master hardware
176  * @dev: device private data
177  *
178  * This functions configures and enables the I2C master.
179  * This function is called during I2C init function, and in case of timeout at
180  * run time.
181  */
182 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
183 {
184 	int ret;
185 
186 	ret = i2c_dw_acquire_lock(dev);
187 	if (ret)
188 		return ret;
189 
190 	/* Disable the adapter */
191 	__i2c_dw_disable(dev);
192 
193 	/* Write standard speed timing parameters */
194 	regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
195 	regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
196 
197 	/* Write fast mode/fast mode plus timing parameters */
198 	regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
199 	regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
200 
201 	/* Write high speed timing parameters if supported */
202 	if (dev->hs_hcnt && dev->hs_lcnt) {
203 		regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
204 		regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
205 	}
206 
207 	/* Write SDA hold time if supported */
208 	if (dev->sda_hold_time)
209 		regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
210 
211 	i2c_dw_configure_fifo_master(dev);
212 	i2c_dw_release_lock(dev);
213 
214 	return 0;
215 }
216 
217 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
218 {
219 	struct i2c_msg *msgs = dev->msgs;
220 	u32 ic_con = 0, ic_tar = 0;
221 	u32 dummy;
222 
223 	/* Disable the adapter */
224 	__i2c_dw_disable(dev);
225 
226 	/* If the slave address is ten bit address, enable 10BITADDR */
227 	if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
228 		ic_con = DW_IC_CON_10BITADDR_MASTER;
229 		/*
230 		 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
231 		 * mode has to be enabled via bit 12 of IC_TAR register.
232 		 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
233 		 * detected from registers.
234 		 */
235 		ic_tar = DW_IC_TAR_10BITADDR_MASTER;
236 	}
237 
238 	regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
239 			   ic_con);
240 
241 	/*
242 	 * Set the slave (target) address and enable 10-bit addressing mode
243 	 * if applicable.
244 	 */
245 	regmap_write(dev->map, DW_IC_TAR,
246 		     msgs[dev->msg_write_idx].addr | ic_tar);
247 
248 	/* Enforce disabled interrupts (due to HW issues) */
249 	i2c_dw_disable_int(dev);
250 
251 	/* Enable the adapter */
252 	__i2c_dw_enable(dev);
253 
254 	/* Dummy read to avoid the register getting stuck on Bay Trail */
255 	regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
256 
257 	/* Clear and enable interrupts */
258 	regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
259 	regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
260 }
261 
262 /*
263  * Initiate (and continue) low level master read/write transaction.
264  * This function is only called from i2c_dw_isr, and pumping i2c_msg
265  * messages into the tx buffer.  Even if the size of i2c_msg data is
266  * longer than the size of the tx buffer, it handles everything.
267  */
268 static void
269 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
270 {
271 	struct i2c_msg *msgs = dev->msgs;
272 	u32 intr_mask;
273 	int tx_limit, rx_limit;
274 	u32 addr = msgs[dev->msg_write_idx].addr;
275 	u32 buf_len = dev->tx_buf_len;
276 	u8 *buf = dev->tx_buf;
277 	bool need_restart = false;
278 	unsigned int flr;
279 
280 	intr_mask = DW_IC_INTR_MASTER_MASK;
281 
282 	for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
283 		u32 flags = msgs[dev->msg_write_idx].flags;
284 
285 		/*
286 		 * If target address has changed, we need to
287 		 * reprogram the target address in the I2C
288 		 * adapter when we are done with this transfer.
289 		 */
290 		if (msgs[dev->msg_write_idx].addr != addr) {
291 			dev_err(dev->dev,
292 				"%s: invalid target address\n", __func__);
293 			dev->msg_err = -EINVAL;
294 			break;
295 		}
296 
297 		if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
298 			/* new i2c_msg */
299 			buf = msgs[dev->msg_write_idx].buf;
300 			buf_len = msgs[dev->msg_write_idx].len;
301 
302 			/* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
303 			 * IC_RESTART_EN are set, we must manually
304 			 * set restart bit between messages.
305 			 */
306 			if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
307 					(dev->msg_write_idx > 0))
308 				need_restart = true;
309 		}
310 
311 		regmap_read(dev->map, DW_IC_TXFLR, &flr);
312 		tx_limit = dev->tx_fifo_depth - flr;
313 
314 		regmap_read(dev->map, DW_IC_RXFLR, &flr);
315 		rx_limit = dev->rx_fifo_depth - flr;
316 
317 		while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
318 			u32 cmd = 0;
319 
320 			/*
321 			 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
322 			 * manually set the stop bit. However, it cannot be
323 			 * detected from the registers so we set it always
324 			 * when writing/reading the last byte.
325 			 */
326 
327 			/*
328 			 * i2c-core always sets the buffer length of
329 			 * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
330 			 * be adjusted when receiving the first byte.
331 			 * Thus we can't stop the transaction here.
332 			 */
333 			if (dev->msg_write_idx == dev->msgs_num - 1 &&
334 			    buf_len == 1 && !(flags & I2C_M_RECV_LEN))
335 				cmd |= BIT(9);
336 
337 			if (need_restart) {
338 				cmd |= BIT(10);
339 				need_restart = false;
340 			}
341 
342 			if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
343 
344 				/* Avoid rx buffer overrun */
345 				if (dev->rx_outstanding >= dev->rx_fifo_depth)
346 					break;
347 
348 				regmap_write(dev->map, DW_IC_DATA_CMD,
349 					     cmd | 0x100);
350 				rx_limit--;
351 				dev->rx_outstanding++;
352 			} else {
353 				regmap_write(dev->map, DW_IC_DATA_CMD,
354 					     cmd | *buf++);
355 			}
356 			tx_limit--; buf_len--;
357 		}
358 
359 		dev->tx_buf = buf;
360 		dev->tx_buf_len = buf_len;
361 
362 		/*
363 		 * Because we don't know the buffer length in the
364 		 * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
365 		 * the transaction here.
366 		 */
367 		if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
368 			/* more bytes to be written */
369 			dev->status |= STATUS_WRITE_IN_PROGRESS;
370 			break;
371 		} else
372 			dev->status &= ~STATUS_WRITE_IN_PROGRESS;
373 	}
374 
375 	/*
376 	 * If i2c_msg index search is completed, we don't need TX_EMPTY
377 	 * interrupt any more.
378 	 */
379 	if (dev->msg_write_idx == dev->msgs_num)
380 		intr_mask &= ~DW_IC_INTR_TX_EMPTY;
381 
382 	if (dev->msg_err)
383 		intr_mask = 0;
384 
385 	regmap_write(dev->map,  DW_IC_INTR_MASK, intr_mask);
386 }
387 
388 static u8
389 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
390 {
391 	struct i2c_msg *msgs = dev->msgs;
392 	u32 flags = msgs[dev->msg_read_idx].flags;
393 
394 	/*
395 	 * Adjust the buffer length and mask the flag
396 	 * after receiving the first byte.
397 	 */
398 	len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
399 	dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
400 	msgs[dev->msg_read_idx].len = len;
401 	msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
402 
403 	return len;
404 }
405 
406 static void
407 i2c_dw_read(struct dw_i2c_dev *dev)
408 {
409 	struct i2c_msg *msgs = dev->msgs;
410 	unsigned int rx_valid;
411 
412 	for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
413 		u32 len, tmp;
414 		u8 *buf;
415 
416 		if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
417 			continue;
418 
419 		if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
420 			len = msgs[dev->msg_read_idx].len;
421 			buf = msgs[dev->msg_read_idx].buf;
422 		} else {
423 			len = dev->rx_buf_len;
424 			buf = dev->rx_buf;
425 		}
426 
427 		regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
428 
429 		for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
430 			u32 flags = msgs[dev->msg_read_idx].flags;
431 
432 			regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
433 			/* Ensure length byte is a valid value */
434 			if (flags & I2C_M_RECV_LEN &&
435 			    (tmp & DW_IC_DATA_CMD_DAT) <= I2C_SMBUS_BLOCK_MAX && tmp > 0) {
436 				len = i2c_dw_recv_len(dev, tmp);
437 			}
438 			*buf++ = tmp;
439 			dev->rx_outstanding--;
440 		}
441 
442 		if (len > 0) {
443 			dev->status |= STATUS_READ_IN_PROGRESS;
444 			dev->rx_buf_len = len;
445 			dev->rx_buf = buf;
446 			return;
447 		} else
448 			dev->status &= ~STATUS_READ_IN_PROGRESS;
449 	}
450 }
451 
452 /*
453  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
454  */
455 static int
456 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
457 {
458 	struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
459 	int ret;
460 
461 	dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
462 
463 	pm_runtime_get_sync(dev->dev);
464 
465 	if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) {
466 		ret = -ESHUTDOWN;
467 		goto done_nolock;
468 	}
469 
470 	reinit_completion(&dev->cmd_complete);
471 	dev->msgs = msgs;
472 	dev->msgs_num = num;
473 	dev->cmd_err = 0;
474 	dev->msg_write_idx = 0;
475 	dev->msg_read_idx = 0;
476 	dev->msg_err = 0;
477 	dev->status = STATUS_IDLE;
478 	dev->abort_source = 0;
479 	dev->rx_outstanding = 0;
480 
481 	ret = i2c_dw_acquire_lock(dev);
482 	if (ret)
483 		goto done_nolock;
484 
485 	ret = i2c_dw_wait_bus_not_busy(dev);
486 	if (ret < 0)
487 		goto done;
488 
489 	/* Start the transfers */
490 	i2c_dw_xfer_init(dev);
491 
492 	/* Wait for tx to complete */
493 	if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
494 		dev_err(dev->dev, "controller timed out\n");
495 		/* i2c_dw_init implicitly disables the adapter */
496 		i2c_recover_bus(&dev->adapter);
497 		i2c_dw_init_master(dev);
498 		ret = -ETIMEDOUT;
499 		goto done;
500 	}
501 
502 	/*
503 	 * We must disable the adapter before returning and signaling the end
504 	 * of the current transfer. Otherwise the hardware might continue
505 	 * generating interrupts which in turn causes a race condition with
506 	 * the following transfer.  Needs some more investigation if the
507 	 * additional interrupts are a hardware bug or this driver doesn't
508 	 * handle them correctly yet.
509 	 */
510 	__i2c_dw_disable_nowait(dev);
511 
512 	if (dev->msg_err) {
513 		ret = dev->msg_err;
514 		goto done;
515 	}
516 
517 	/* No error */
518 	if (likely(!dev->cmd_err && !dev->status)) {
519 		ret = num;
520 		goto done;
521 	}
522 
523 	/* We have an error */
524 	if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
525 		ret = i2c_dw_handle_tx_abort(dev);
526 		goto done;
527 	}
528 
529 	if (dev->status)
530 		dev_err(dev->dev,
531 			"transfer terminated early - interrupt latency too high?\n");
532 
533 	ret = -EIO;
534 
535 done:
536 	i2c_dw_release_lock(dev);
537 
538 done_nolock:
539 	pm_runtime_mark_last_busy(dev->dev);
540 	pm_runtime_put_autosuspend(dev->dev);
541 
542 	return ret;
543 }
544 
545 static const struct i2c_algorithm i2c_dw_algo = {
546 	.master_xfer = i2c_dw_xfer,
547 	.functionality = i2c_dw_func,
548 };
549 
550 static const struct i2c_adapter_quirks i2c_dw_quirks = {
551 	.flags = I2C_AQ_NO_ZERO_LEN,
552 };
553 
554 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
555 {
556 	u32 stat, dummy;
557 
558 	/*
559 	 * The IC_INTR_STAT register just indicates "enabled" interrupts.
560 	 * The unmasked raw version of interrupt status bits is available
561 	 * in the IC_RAW_INTR_STAT register.
562 	 *
563 	 * That is,
564 	 *   stat = readl(IC_INTR_STAT);
565 	 * equals to,
566 	 *   stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
567 	 *
568 	 * The raw version might be useful for debugging purposes.
569 	 */
570 	regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
571 
572 	/*
573 	 * Do not use the IC_CLR_INTR register to clear interrupts, or
574 	 * you'll miss some interrupts, triggered during the period from
575 	 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
576 	 *
577 	 * Instead, use the separately-prepared IC_CLR_* registers.
578 	 */
579 	if (stat & DW_IC_INTR_RX_UNDER)
580 		regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
581 	if (stat & DW_IC_INTR_RX_OVER)
582 		regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
583 	if (stat & DW_IC_INTR_TX_OVER)
584 		regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
585 	if (stat & DW_IC_INTR_RD_REQ)
586 		regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
587 	if (stat & DW_IC_INTR_TX_ABRT) {
588 		/*
589 		 * The IC_TX_ABRT_SOURCE register is cleared whenever
590 		 * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
591 		 */
592 		regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
593 		regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
594 	}
595 	if (stat & DW_IC_INTR_RX_DONE)
596 		regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
597 	if (stat & DW_IC_INTR_ACTIVITY)
598 		regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
599 	if (stat & DW_IC_INTR_STOP_DET)
600 		regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
601 	if (stat & DW_IC_INTR_START_DET)
602 		regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
603 	if (stat & DW_IC_INTR_GEN_CALL)
604 		regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
605 
606 	return stat;
607 }
608 
609 /*
610  * Interrupt service routine. This gets called whenever an I2C master interrupt
611  * occurs.
612  */
613 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
614 {
615 	u32 stat;
616 
617 	stat = i2c_dw_read_clear_intrbits(dev);
618 	if (stat & DW_IC_INTR_TX_ABRT) {
619 		dev->cmd_err |= DW_IC_ERR_TX_ABRT;
620 		dev->status = STATUS_IDLE;
621 
622 		/*
623 		 * Anytime TX_ABRT is set, the contents of the tx/rx
624 		 * buffers are flushed. Make sure to skip them.
625 		 */
626 		regmap_write(dev->map, DW_IC_INTR_MASK, 0);
627 		goto tx_aborted;
628 	}
629 
630 	if (stat & DW_IC_INTR_RX_FULL)
631 		i2c_dw_read(dev);
632 
633 	if (stat & DW_IC_INTR_TX_EMPTY)
634 		i2c_dw_xfer_msg(dev);
635 
636 	/*
637 	 * No need to modify or disable the interrupt mask here.
638 	 * i2c_dw_xfer_msg() will take care of it according to
639 	 * the current transmit status.
640 	 */
641 
642 tx_aborted:
643 	if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
644 		complete(&dev->cmd_complete);
645 	else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
646 		/* Workaround to trigger pending interrupt */
647 		regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
648 		i2c_dw_disable_int(dev);
649 		regmap_write(dev->map, DW_IC_INTR_MASK, stat);
650 	}
651 
652 	return 0;
653 }
654 
655 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
656 {
657 	struct dw_i2c_dev *dev = dev_id;
658 	u32 stat, enabled;
659 
660 	regmap_read(dev->map, DW_IC_ENABLE, &enabled);
661 	regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
662 	dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
663 	if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
664 		return IRQ_NONE;
665 
666 	i2c_dw_irq_handler_master(dev);
667 
668 	return IRQ_HANDLED;
669 }
670 
671 void i2c_dw_configure_master(struct dw_i2c_dev *dev)
672 {
673 	struct i2c_timings *t = &dev->timings;
674 
675 	dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
676 
677 	dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
678 			  DW_IC_CON_RESTART_EN;
679 
680 	dev->mode = DW_IC_MASTER;
681 
682 	switch (t->bus_freq_hz) {
683 	case I2C_MAX_STANDARD_MODE_FREQ:
684 		dev->master_cfg |= DW_IC_CON_SPEED_STD;
685 		break;
686 	case I2C_MAX_HIGH_SPEED_MODE_FREQ:
687 		dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
688 		break;
689 	default:
690 		dev->master_cfg |= DW_IC_CON_SPEED_FAST;
691 	}
692 }
693 EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
694 
695 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
696 {
697 	struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
698 
699 	i2c_dw_disable(dev);
700 	reset_control_assert(dev->rst);
701 	i2c_dw_prepare_clk(dev, false);
702 }
703 
704 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
705 {
706 	struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
707 
708 	i2c_dw_prepare_clk(dev, true);
709 	reset_control_deassert(dev->rst);
710 	i2c_dw_init_master(dev);
711 }
712 
713 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
714 {
715 	struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
716 	struct i2c_adapter *adap = &dev->adapter;
717 	struct gpio_desc *gpio;
718 
719 	gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
720 	if (IS_ERR_OR_NULL(gpio))
721 		return PTR_ERR_OR_ZERO(gpio);
722 
723 	rinfo->scl_gpiod = gpio;
724 
725 	gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
726 	if (IS_ERR(gpio))
727 		return PTR_ERR(gpio);
728 	rinfo->sda_gpiod = gpio;
729 
730 	rinfo->recover_bus = i2c_generic_scl_recovery;
731 	rinfo->prepare_recovery = i2c_dw_prepare_recovery;
732 	rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
733 	adap->bus_recovery_info = rinfo;
734 
735 	dev_info(dev->dev, "running with gpio recovery mode! scl%s",
736 		 rinfo->sda_gpiod ? ",sda" : "");
737 
738 	return 0;
739 }
740 
741 int i2c_dw_probe_master(struct dw_i2c_dev *dev)
742 {
743 	struct i2c_adapter *adap = &dev->adapter;
744 	unsigned long irq_flags;
745 	int ret;
746 
747 	init_completion(&dev->cmd_complete);
748 
749 	dev->init = i2c_dw_init_master;
750 	dev->disable = i2c_dw_disable;
751 	dev->disable_int = i2c_dw_disable_int;
752 
753 	ret = i2c_dw_init_regmap(dev);
754 	if (ret)
755 		return ret;
756 
757 	ret = i2c_dw_set_timings_master(dev);
758 	if (ret)
759 		return ret;
760 
761 	ret = i2c_dw_set_fifo_size(dev);
762 	if (ret)
763 		return ret;
764 
765 	ret = dev->init(dev);
766 	if (ret)
767 		return ret;
768 
769 	snprintf(adap->name, sizeof(adap->name),
770 		 "Synopsys DesignWare I2C adapter");
771 	adap->retries = 3;
772 	adap->algo = &i2c_dw_algo;
773 	adap->quirks = &i2c_dw_quirks;
774 	adap->dev.parent = dev->dev;
775 	i2c_set_adapdata(adap, dev);
776 
777 	if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
778 		irq_flags = IRQF_NO_SUSPEND;
779 	} else {
780 		irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
781 	}
782 
783 	i2c_dw_disable_int(dev);
784 	ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
785 			       dev_name(dev->dev), dev);
786 	if (ret) {
787 		dev_err(dev->dev, "failure requesting irq %i: %d\n",
788 			dev->irq, ret);
789 		return ret;
790 	}
791 
792 	ret = i2c_dw_init_recovery_info(dev);
793 	if (ret)
794 		return ret;
795 
796 	/*
797 	 * Increment PM usage count during adapter registration in order to
798 	 * avoid possible spurious runtime suspend when adapter device is
799 	 * registered to the device core and immediate resume in case bus has
800 	 * registered I2C slaves that do I2C transfers in their probe.
801 	 */
802 	pm_runtime_get_noresume(dev->dev);
803 	ret = i2c_add_numbered_adapter(adap);
804 	if (ret)
805 		dev_err(dev->dev, "failure adding adapter: %d\n", ret);
806 	pm_runtime_put_noidle(dev->dev);
807 
808 	return ret;
809 }
810 EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
811 
812 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
813 MODULE_LICENSE("GPL");
814