1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Synopsys DesignWare I2C adapter driver (master only). 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/export.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 25 #define DEFAULT_SYMBOL_NAMESPACE I2C_DW 26 27 #include "i2c-designware-core.h" 28 29 #define AMD_TIMEOUT_MIN_US 25 30 #define AMD_TIMEOUT_MAX_US 250 31 #define AMD_MASTERCFG_MASK GENMASK(15, 0) 32 33 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev) 34 { 35 /* Configure Tx/Rx FIFO threshold levels */ 36 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); 37 regmap_write(dev->map, DW_IC_RX_TL, 0); 38 39 /* Configure the I2C master */ 40 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); 41 } 42 43 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) 44 { 45 unsigned int comp_param1; 46 u32 sda_falling_time, scl_falling_time; 47 struct i2c_timings *t = &dev->timings; 48 const char *fp_str = ""; 49 u32 ic_clk; 50 int ret; 51 52 ret = i2c_dw_acquire_lock(dev); 53 if (ret) 54 return ret; 55 56 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); 57 i2c_dw_release_lock(dev); 58 if (ret) 59 return ret; 60 61 /* Set standard and fast speed dividers for high/low periods */ 62 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ 63 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ 64 65 /* Calculate SCL timing parameters for standard mode if not set */ 66 if (!dev->ss_hcnt || !dev->ss_lcnt) { 67 ic_clk = i2c_dw_clk_rate(dev); 68 dev->ss_hcnt = 69 i2c_dw_scl_hcnt(dev, 70 DW_IC_SS_SCL_HCNT, 71 ic_clk, 72 4000, /* tHD;STA = tHIGH = 4.0 us */ 73 sda_falling_time, 74 0, /* 0: DW default, 1: Ideal */ 75 0); /* No offset */ 76 dev->ss_lcnt = 77 i2c_dw_scl_lcnt(dev, 78 DW_IC_SS_SCL_LCNT, 79 ic_clk, 80 4700, /* tLOW = 4.7 us */ 81 scl_falling_time, 82 0); /* No offset */ 83 } 84 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", 85 dev->ss_hcnt, dev->ss_lcnt); 86 87 /* 88 * Set SCL timing parameters for fast mode or fast mode plus. Only 89 * difference is the timing parameter values since the registers are 90 * the same. 91 */ 92 if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) { 93 /* 94 * Check are Fast Mode Plus parameters available. Calculate 95 * SCL timing parameters for Fast Mode Plus if not set. 96 */ 97 if (dev->fp_hcnt && dev->fp_lcnt) { 98 dev->fs_hcnt = dev->fp_hcnt; 99 dev->fs_lcnt = dev->fp_lcnt; 100 } else { 101 ic_clk = i2c_dw_clk_rate(dev); 102 dev->fs_hcnt = 103 i2c_dw_scl_hcnt(dev, 104 DW_IC_FS_SCL_HCNT, 105 ic_clk, 106 260, /* tHIGH = 260 ns */ 107 sda_falling_time, 108 0, /* DW default */ 109 0); /* No offset */ 110 dev->fs_lcnt = 111 i2c_dw_scl_lcnt(dev, 112 DW_IC_FS_SCL_LCNT, 113 ic_clk, 114 500, /* tLOW = 500 ns */ 115 scl_falling_time, 116 0); /* No offset */ 117 } 118 fp_str = " Plus"; 119 } 120 /* 121 * Calculate SCL timing parameters for fast mode if not set. They are 122 * needed also in high speed mode. 123 */ 124 if (!dev->fs_hcnt || !dev->fs_lcnt) { 125 ic_clk = i2c_dw_clk_rate(dev); 126 dev->fs_hcnt = 127 i2c_dw_scl_hcnt(dev, 128 DW_IC_FS_SCL_HCNT, 129 ic_clk, 130 600, /* tHD;STA = tHIGH = 0.6 us */ 131 sda_falling_time, 132 0, /* 0: DW default, 1: Ideal */ 133 0); /* No offset */ 134 dev->fs_lcnt = 135 i2c_dw_scl_lcnt(dev, 136 DW_IC_FS_SCL_LCNT, 137 ic_clk, 138 1300, /* tLOW = 1.3 us */ 139 scl_falling_time, 140 0); /* No offset */ 141 } 142 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", 143 fp_str, dev->fs_hcnt, dev->fs_lcnt); 144 145 /* Check is high speed possible and fall back to fast mode if not */ 146 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == 147 DW_IC_CON_SPEED_HIGH) { 148 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK) 149 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) { 150 dev_err(dev->dev, "High Speed not supported!\n"); 151 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; 152 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; 153 dev->master_cfg |= DW_IC_CON_SPEED_FAST; 154 dev->hs_hcnt = 0; 155 dev->hs_lcnt = 0; 156 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { 157 ic_clk = i2c_dw_clk_rate(dev); 158 dev->hs_hcnt = 159 i2c_dw_scl_hcnt(dev, 160 DW_IC_HS_SCL_HCNT, 161 ic_clk, 162 160, /* tHIGH = 160 ns */ 163 sda_falling_time, 164 0, /* DW default */ 165 0); /* No offset */ 166 dev->hs_lcnt = 167 i2c_dw_scl_lcnt(dev, 168 DW_IC_HS_SCL_LCNT, 169 ic_clk, 170 320, /* tLOW = 320 ns */ 171 scl_falling_time, 172 0); /* No offset */ 173 } 174 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", 175 dev->hs_hcnt, dev->hs_lcnt); 176 } 177 178 ret = i2c_dw_set_sda_hold(dev); 179 if (ret) 180 return ret; 181 182 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); 183 return 0; 184 } 185 186 /** 187 * i2c_dw_init_master() - Initialize the designware I2C master hardware 188 * @dev: device private data 189 * 190 * This functions configures and enables the I2C master. 191 * This function is called during I2C init function, and in case of timeout at 192 * run time. 193 */ 194 static int i2c_dw_init_master(struct dw_i2c_dev *dev) 195 { 196 int ret; 197 198 ret = i2c_dw_acquire_lock(dev); 199 if (ret) 200 return ret; 201 202 /* Disable the adapter */ 203 __i2c_dw_disable(dev); 204 205 /* Write standard speed timing parameters */ 206 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); 207 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); 208 209 /* Write fast mode/fast mode plus timing parameters */ 210 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); 211 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); 212 213 /* Write high speed timing parameters if supported */ 214 if (dev->hs_hcnt && dev->hs_lcnt) { 215 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); 216 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); 217 } 218 219 /* Write SDA hold time if supported */ 220 if (dev->sda_hold_time) 221 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); 222 223 i2c_dw_configure_fifo_master(dev); 224 i2c_dw_release_lock(dev); 225 226 return 0; 227 } 228 229 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) 230 { 231 struct i2c_msg *msgs = dev->msgs; 232 u32 ic_con = 0, ic_tar = 0; 233 unsigned int dummy; 234 235 /* Disable the adapter */ 236 __i2c_dw_disable(dev); 237 238 /* If the slave address is ten bit address, enable 10BITADDR */ 239 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { 240 ic_con = DW_IC_CON_10BITADDR_MASTER; 241 /* 242 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing 243 * mode has to be enabled via bit 12 of IC_TAR register. 244 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be 245 * detected from registers. 246 */ 247 ic_tar = DW_IC_TAR_10BITADDR_MASTER; 248 } 249 250 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER, 251 ic_con); 252 253 /* 254 * Set the slave (target) address and enable 10-bit addressing mode 255 * if applicable. 256 */ 257 regmap_write(dev->map, DW_IC_TAR, 258 msgs[dev->msg_write_idx].addr | ic_tar); 259 260 /* Enforce disabled interrupts (due to HW issues) */ 261 __i2c_dw_write_intr_mask(dev, 0); 262 263 /* Enable the adapter */ 264 __i2c_dw_enable(dev); 265 266 /* Dummy read to avoid the register getting stuck on Bay Trail */ 267 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy); 268 269 /* Clear and enable interrupts */ 270 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); 271 __i2c_dw_write_intr_mask(dev, DW_IC_INTR_MASTER_MASK); 272 } 273 274 static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev) 275 { 276 u32 val; 277 int ret; 278 279 ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val, 280 !(val & DW_IC_INTR_STOP_DET), 281 1100, 20000); 282 if (ret) 283 dev_err(dev->dev, "i2c timeout error %d\n", ret); 284 285 return ret; 286 } 287 288 static int i2c_dw_status(struct dw_i2c_dev *dev) 289 { 290 int status; 291 292 status = i2c_dw_wait_bus_not_busy(dev); 293 if (status) 294 return status; 295 296 return i2c_dw_check_stopbit(dev); 297 } 298 299 /* 300 * Initiate and continue master read/write transaction with polling 301 * based transfer routine afterward write messages into the Tx buffer. 302 */ 303 static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs) 304 { 305 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 306 int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx; 307 int cmd = 0, status; 308 u8 *tx_buf; 309 unsigned int val; 310 311 /* 312 * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card, 313 * it is mandatory to set the right value in specific register 314 * (offset:0x474) as per the hardware IP specification. 315 */ 316 regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN); 317 318 dev->msgs = msgs; 319 dev->msgs_num = num_msgs; 320 i2c_dw_xfer_init(dev); 321 322 /* Initiate messages read/write transaction */ 323 for (msg_wrt_idx = 0; msg_wrt_idx < num_msgs; msg_wrt_idx++) { 324 tx_buf = msgs[msg_wrt_idx].buf; 325 buf_len = msgs[msg_wrt_idx].len; 326 327 if (!(msgs[msg_wrt_idx].flags & I2C_M_RD)) 328 regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1); 329 /* 330 * Initiate the i2c read/write transaction of buffer length, 331 * and poll for bus busy status. For the last message transfer, 332 * update the command with stopbit enable. 333 */ 334 for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) { 335 if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1) 336 cmd |= BIT(9); 337 338 if (msgs[msg_wrt_idx].flags & I2C_M_RD) { 339 /* Due to hardware bug, need to write the same command twice. */ 340 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100); 341 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd); 342 if (cmd) { 343 regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1)); 344 regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1)); 345 /* 346 * Need to check the stop bit. However, it cannot be 347 * detected from the registers so we check it always 348 * when read/write the last byte. 349 */ 350 status = i2c_dw_status(dev); 351 if (status) 352 return status; 353 354 for (data_idx = 0; data_idx < buf_len; data_idx++) { 355 regmap_read(dev->map, DW_IC_DATA_CMD, &val); 356 tx_buf[data_idx] = val; 357 } 358 status = i2c_dw_check_stopbit(dev); 359 if (status) 360 return status; 361 } 362 } else { 363 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd); 364 usleep_range(AMD_TIMEOUT_MIN_US, AMD_TIMEOUT_MAX_US); 365 } 366 } 367 status = i2c_dw_check_stopbit(dev); 368 if (status) 369 return status; 370 } 371 372 return 0; 373 } 374 375 /* 376 * Initiate (and continue) low level master read/write transaction. 377 * This function is only called from i2c_dw_isr, and pumping i2c_msg 378 * messages into the tx buffer. Even if the size of i2c_msg data is 379 * longer than the size of the tx buffer, it handles everything. 380 */ 381 static void 382 i2c_dw_xfer_msg(struct dw_i2c_dev *dev) 383 { 384 struct i2c_msg *msgs = dev->msgs; 385 u32 intr_mask; 386 int tx_limit, rx_limit; 387 u32 addr = msgs[dev->msg_write_idx].addr; 388 u32 buf_len = dev->tx_buf_len; 389 u8 *buf = dev->tx_buf; 390 bool need_restart = false; 391 unsigned int flr; 392 393 intr_mask = DW_IC_INTR_MASTER_MASK; 394 395 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { 396 u32 flags = msgs[dev->msg_write_idx].flags; 397 398 /* 399 * If target address has changed, we need to 400 * reprogram the target address in the I2C 401 * adapter when we are done with this transfer. 402 */ 403 if (msgs[dev->msg_write_idx].addr != addr) { 404 dev_err(dev->dev, 405 "%s: invalid target address\n", __func__); 406 dev->msg_err = -EINVAL; 407 break; 408 } 409 410 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { 411 /* new i2c_msg */ 412 buf = msgs[dev->msg_write_idx].buf; 413 buf_len = msgs[dev->msg_write_idx].len; 414 415 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and 416 * IC_RESTART_EN are set, we must manually 417 * set restart bit between messages. 418 */ 419 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && 420 (dev->msg_write_idx > 0)) 421 need_restart = true; 422 } 423 424 regmap_read(dev->map, DW_IC_TXFLR, &flr); 425 tx_limit = dev->tx_fifo_depth - flr; 426 427 regmap_read(dev->map, DW_IC_RXFLR, &flr); 428 rx_limit = dev->rx_fifo_depth - flr; 429 430 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { 431 u32 cmd = 0; 432 433 /* 434 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must 435 * manually set the stop bit. However, it cannot be 436 * detected from the registers so we set it always 437 * when writing/reading the last byte. 438 */ 439 440 /* 441 * i2c-core always sets the buffer length of 442 * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will 443 * be adjusted when receiving the first byte. 444 * Thus we can't stop the transaction here. 445 */ 446 if (dev->msg_write_idx == dev->msgs_num - 1 && 447 buf_len == 1 && !(flags & I2C_M_RECV_LEN)) 448 cmd |= BIT(9); 449 450 if (need_restart) { 451 cmd |= BIT(10); 452 need_restart = false; 453 } 454 455 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { 456 457 /* Avoid rx buffer overrun */ 458 if (dev->rx_outstanding >= dev->rx_fifo_depth) 459 break; 460 461 regmap_write(dev->map, DW_IC_DATA_CMD, 462 cmd | 0x100); 463 rx_limit--; 464 dev->rx_outstanding++; 465 } else { 466 regmap_write(dev->map, DW_IC_DATA_CMD, 467 cmd | *buf++); 468 } 469 tx_limit--; buf_len--; 470 } 471 472 dev->tx_buf = buf; 473 dev->tx_buf_len = buf_len; 474 475 /* 476 * Because we don't know the buffer length in the 477 * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop the 478 * transaction here. Also disable the TX_EMPTY IRQ 479 * while waiting for the data length byte to avoid the 480 * bogus interrupts flood. 481 */ 482 if (flags & I2C_M_RECV_LEN) { 483 dev->status |= STATUS_WRITE_IN_PROGRESS; 484 intr_mask &= ~DW_IC_INTR_TX_EMPTY; 485 break; 486 } else if (buf_len > 0) { 487 /* more bytes to be written */ 488 dev->status |= STATUS_WRITE_IN_PROGRESS; 489 break; 490 } else 491 dev->status &= ~STATUS_WRITE_IN_PROGRESS; 492 } 493 494 /* 495 * If i2c_msg index search is completed, we don't need TX_EMPTY 496 * interrupt any more. 497 */ 498 if (dev->msg_write_idx == dev->msgs_num) 499 intr_mask &= ~DW_IC_INTR_TX_EMPTY; 500 501 if (dev->msg_err) 502 intr_mask = 0; 503 504 __i2c_dw_write_intr_mask(dev, intr_mask); 505 } 506 507 static u8 508 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len) 509 { 510 struct i2c_msg *msgs = dev->msgs; 511 u32 flags = msgs[dev->msg_read_idx].flags; 512 unsigned int intr_mask; 513 514 /* 515 * Adjust the buffer length and mask the flag 516 * after receiving the first byte. 517 */ 518 len += (flags & I2C_CLIENT_PEC) ? 2 : 1; 519 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); 520 msgs[dev->msg_read_idx].len = len; 521 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; 522 523 /* 524 * Received buffer length, re-enable TX_EMPTY interrupt 525 * to resume the SMBUS transaction. 526 */ 527 __i2c_dw_read_intr_mask(dev, &intr_mask); 528 intr_mask |= DW_IC_INTR_TX_EMPTY; 529 __i2c_dw_write_intr_mask(dev, intr_mask); 530 531 return len; 532 } 533 534 static void 535 i2c_dw_read(struct dw_i2c_dev *dev) 536 { 537 struct i2c_msg *msgs = dev->msgs; 538 unsigned int rx_valid; 539 540 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { 541 unsigned int tmp; 542 u32 len; 543 u8 *buf; 544 545 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) 546 continue; 547 548 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { 549 len = msgs[dev->msg_read_idx].len; 550 buf = msgs[dev->msg_read_idx].buf; 551 } else { 552 len = dev->rx_buf_len; 553 buf = dev->rx_buf; 554 } 555 556 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); 557 558 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { 559 u32 flags = msgs[dev->msg_read_idx].flags; 560 561 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); 562 tmp &= DW_IC_DATA_CMD_DAT; 563 /* Ensure length byte is a valid value */ 564 if (flags & I2C_M_RECV_LEN) { 565 /* 566 * if IC_EMPTYFIFO_HOLD_MASTER_EN is set, which cannot be 567 * detected from the registers, the controller can be 568 * disabled if the STOP bit is set. But it is only set 569 * after receiving block data response length in 570 * I2C_FUNC_SMBUS_BLOCK_DATA case. That needs to read 571 * another byte with STOP bit set when the block data 572 * response length is invalid to complete the transaction. 573 */ 574 if (!tmp || tmp > I2C_SMBUS_BLOCK_MAX) 575 tmp = 1; 576 577 len = i2c_dw_recv_len(dev, tmp); 578 } 579 *buf++ = tmp; 580 dev->rx_outstanding--; 581 } 582 583 if (len > 0) { 584 dev->status |= STATUS_READ_IN_PROGRESS; 585 dev->rx_buf_len = len; 586 dev->rx_buf = buf; 587 return; 588 } else 589 dev->status &= ~STATUS_READ_IN_PROGRESS; 590 } 591 } 592 593 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) 594 { 595 unsigned int stat, dummy; 596 597 /* 598 * The IC_INTR_STAT register just indicates "enabled" interrupts. 599 * The unmasked raw version of interrupt status bits is available 600 * in the IC_RAW_INTR_STAT register. 601 * 602 * That is, 603 * stat = readl(IC_INTR_STAT); 604 * equals to, 605 * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); 606 * 607 * The raw version might be useful for debugging purposes. 608 */ 609 if (!(dev->flags & ACCESS_POLLING)) { 610 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); 611 } else { 612 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); 613 stat &= dev->sw_mask; 614 } 615 616 /* 617 * Do not use the IC_CLR_INTR register to clear interrupts, or 618 * you'll miss some interrupts, triggered during the period from 619 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). 620 * 621 * Instead, use the separately-prepared IC_CLR_* registers. 622 */ 623 if (stat & DW_IC_INTR_RX_UNDER) 624 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); 625 if (stat & DW_IC_INTR_RX_OVER) 626 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); 627 if (stat & DW_IC_INTR_TX_OVER) 628 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); 629 if (stat & DW_IC_INTR_RD_REQ) 630 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy); 631 if (stat & DW_IC_INTR_TX_ABRT) { 632 /* 633 * The IC_TX_ABRT_SOURCE register is cleared whenever 634 * the IC_CLR_TX_ABRT is read. Preserve it beforehand. 635 */ 636 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source); 637 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); 638 } 639 if (stat & DW_IC_INTR_RX_DONE) 640 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); 641 if (stat & DW_IC_INTR_ACTIVITY) 642 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); 643 if ((stat & DW_IC_INTR_STOP_DET) && 644 ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL))) 645 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); 646 if (stat & DW_IC_INTR_START_DET) 647 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); 648 if (stat & DW_IC_INTR_GEN_CALL) 649 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); 650 651 return stat; 652 } 653 654 static void i2c_dw_process_transfer(struct dw_i2c_dev *dev, unsigned int stat) 655 { 656 if (stat & DW_IC_INTR_TX_ABRT) { 657 dev->cmd_err |= DW_IC_ERR_TX_ABRT; 658 dev->status &= ~STATUS_MASK; 659 dev->rx_outstanding = 0; 660 661 /* 662 * Anytime TX_ABRT is set, the contents of the tx/rx 663 * buffers are flushed. Make sure to skip them. 664 */ 665 __i2c_dw_write_intr_mask(dev, 0); 666 goto tx_aborted; 667 } 668 669 if (stat & DW_IC_INTR_RX_FULL) 670 i2c_dw_read(dev); 671 672 if (stat & DW_IC_INTR_TX_EMPTY) 673 i2c_dw_xfer_msg(dev); 674 675 /* 676 * No need to modify or disable the interrupt mask here. 677 * i2c_dw_xfer_msg() will take care of it according to 678 * the current transmit status. 679 */ 680 681 tx_aborted: 682 if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) && 683 (dev->rx_outstanding == 0)) 684 complete(&dev->cmd_complete); 685 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { 686 /* Workaround to trigger pending interrupt */ 687 __i2c_dw_read_intr_mask(dev, &stat); 688 __i2c_dw_write_intr_mask(dev, 0); 689 __i2c_dw_write_intr_mask(dev, stat); 690 } 691 } 692 693 /* 694 * Interrupt service routine. This gets called whenever an I2C master interrupt 695 * occurs. 696 */ 697 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) 698 { 699 struct dw_i2c_dev *dev = dev_id; 700 unsigned int stat, enabled; 701 702 regmap_read(dev->map, DW_IC_ENABLE, &enabled); 703 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); 704 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) 705 return IRQ_NONE; 706 if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0)) 707 return IRQ_NONE; 708 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); 709 710 stat = i2c_dw_read_clear_intrbits(dev); 711 712 if (!(dev->status & STATUS_ACTIVE)) { 713 /* 714 * Unexpected interrupt in driver point of view. State 715 * variables are either unset or stale so acknowledge and 716 * disable interrupts for suppressing further interrupts if 717 * interrupt really came from this HW (E.g. firmware has left 718 * the HW active). 719 */ 720 __i2c_dw_write_intr_mask(dev, 0); 721 return IRQ_HANDLED; 722 } 723 724 i2c_dw_process_transfer(dev, stat); 725 726 return IRQ_HANDLED; 727 } 728 729 static int i2c_dw_wait_transfer(struct dw_i2c_dev *dev) 730 { 731 unsigned long timeout = dev->adapter.timeout; 732 unsigned int stat; 733 int ret; 734 735 if (!(dev->flags & ACCESS_POLLING)) { 736 ret = wait_for_completion_timeout(&dev->cmd_complete, timeout); 737 } else { 738 timeout += jiffies; 739 do { 740 ret = try_wait_for_completion(&dev->cmd_complete); 741 if (ret) 742 break; 743 744 stat = i2c_dw_read_clear_intrbits(dev); 745 if (stat) 746 i2c_dw_process_transfer(dev, stat); 747 else 748 /* Try save some power */ 749 usleep_range(3, 25); 750 } while (time_before(jiffies, timeout)); 751 } 752 753 return ret ? 0 : -ETIMEDOUT; 754 } 755 756 /* 757 * Prepare controller for a transaction and call i2c_dw_xfer_msg. 758 */ 759 static int 760 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 761 { 762 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 763 int ret; 764 765 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 766 767 pm_runtime_get_sync(dev->dev); 768 769 switch (dev->flags & MODEL_MASK) { 770 case MODEL_AMD_NAVI_GPU: 771 ret = amd_i2c_dw_xfer_quirk(adap, msgs, num); 772 goto done_nolock; 773 default: 774 break; 775 } 776 777 reinit_completion(&dev->cmd_complete); 778 dev->msgs = msgs; 779 dev->msgs_num = num; 780 dev->cmd_err = 0; 781 dev->msg_write_idx = 0; 782 dev->msg_read_idx = 0; 783 dev->msg_err = 0; 784 dev->status = 0; 785 dev->abort_source = 0; 786 dev->rx_outstanding = 0; 787 788 ret = i2c_dw_acquire_lock(dev); 789 if (ret) 790 goto done_nolock; 791 792 ret = i2c_dw_wait_bus_not_busy(dev); 793 if (ret < 0) 794 goto done; 795 796 /* Start the transfers */ 797 i2c_dw_xfer_init(dev); 798 799 /* Wait for tx to complete */ 800 ret = i2c_dw_wait_transfer(dev); 801 if (ret) { 802 dev_err(dev->dev, "controller timed out\n"); 803 /* i2c_dw_init_master() implicitly disables the adapter */ 804 i2c_recover_bus(&dev->adapter); 805 i2c_dw_init_master(dev); 806 goto done; 807 } 808 809 /* 810 * We must disable the adapter before returning and signaling the end 811 * of the current transfer. Otherwise the hardware might continue 812 * generating interrupts which in turn causes a race condition with 813 * the following transfer. Needs some more investigation if the 814 * additional interrupts are a hardware bug or this driver doesn't 815 * handle them correctly yet. 816 */ 817 __i2c_dw_disable_nowait(dev); 818 819 if (dev->msg_err) { 820 ret = dev->msg_err; 821 goto done; 822 } 823 824 /* No error */ 825 if (likely(!dev->cmd_err && !dev->status)) { 826 ret = num; 827 goto done; 828 } 829 830 /* We have an error */ 831 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { 832 ret = i2c_dw_handle_tx_abort(dev); 833 goto done; 834 } 835 836 if (dev->status) 837 dev_err(dev->dev, 838 "transfer terminated early - interrupt latency too high?\n"); 839 840 ret = -EIO; 841 842 done: 843 i2c_dw_release_lock(dev); 844 845 done_nolock: 846 pm_runtime_mark_last_busy(dev->dev); 847 pm_runtime_put_autosuspend(dev->dev); 848 849 return ret; 850 } 851 852 static const struct i2c_algorithm i2c_dw_algo = { 853 .master_xfer = i2c_dw_xfer, 854 .functionality = i2c_dw_func, 855 }; 856 857 static const struct i2c_adapter_quirks i2c_dw_quirks = { 858 .flags = I2C_AQ_NO_ZERO_LEN, 859 }; 860 861 void i2c_dw_configure_master(struct dw_i2c_dev *dev) 862 { 863 struct i2c_timings *t = &dev->timings; 864 865 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; 866 867 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | 868 DW_IC_CON_RESTART_EN; 869 870 dev->mode = DW_IC_MASTER; 871 872 switch (t->bus_freq_hz) { 873 case I2C_MAX_STANDARD_MODE_FREQ: 874 dev->master_cfg |= DW_IC_CON_SPEED_STD; 875 break; 876 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 877 dev->master_cfg |= DW_IC_CON_SPEED_HIGH; 878 break; 879 default: 880 dev->master_cfg |= DW_IC_CON_SPEED_FAST; 881 } 882 } 883 EXPORT_SYMBOL_GPL(i2c_dw_configure_master); 884 885 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap) 886 { 887 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 888 889 i2c_dw_disable(dev); 890 reset_control_assert(dev->rst); 891 i2c_dw_prepare_clk(dev, false); 892 } 893 894 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap) 895 { 896 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 897 898 i2c_dw_prepare_clk(dev, true); 899 reset_control_deassert(dev->rst); 900 i2c_dw_init_master(dev); 901 } 902 903 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev) 904 { 905 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; 906 struct i2c_adapter *adap = &dev->adapter; 907 struct gpio_desc *gpio; 908 909 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH); 910 if (IS_ERR_OR_NULL(gpio)) 911 return PTR_ERR_OR_ZERO(gpio); 912 913 rinfo->scl_gpiod = gpio; 914 915 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); 916 if (IS_ERR(gpio)) 917 return PTR_ERR(gpio); 918 rinfo->sda_gpiod = gpio; 919 920 rinfo->pinctrl = devm_pinctrl_get(dev->dev); 921 if (IS_ERR(rinfo->pinctrl)) { 922 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER) 923 return PTR_ERR(rinfo->pinctrl); 924 925 rinfo->pinctrl = NULL; 926 dev_err(dev->dev, "getting pinctrl info failed: bus recovery might not work\n"); 927 } else if (!rinfo->pinctrl) { 928 dev_dbg(dev->dev, "pinctrl is disabled, bus recovery might not work\n"); 929 } 930 931 rinfo->recover_bus = i2c_generic_scl_recovery; 932 rinfo->prepare_recovery = i2c_dw_prepare_recovery; 933 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; 934 adap->bus_recovery_info = rinfo; 935 936 dev_info(dev->dev, "running with gpio recovery mode! scl%s", 937 rinfo->sda_gpiod ? ",sda" : ""); 938 939 return 0; 940 } 941 942 int i2c_dw_probe_master(struct dw_i2c_dev *dev) 943 { 944 struct i2c_adapter *adap = &dev->adapter; 945 unsigned long irq_flags; 946 unsigned int ic_con; 947 int ret; 948 949 init_completion(&dev->cmd_complete); 950 951 dev->init = i2c_dw_init_master; 952 953 ret = i2c_dw_init_regmap(dev); 954 if (ret) 955 return ret; 956 957 ret = i2c_dw_set_timings_master(dev); 958 if (ret) 959 return ret; 960 961 ret = i2c_dw_set_fifo_size(dev); 962 if (ret) 963 return ret; 964 965 /* Lock the bus for accessing DW_IC_CON */ 966 ret = i2c_dw_acquire_lock(dev); 967 if (ret) 968 return ret; 969 970 /* 971 * On AMD platforms BIOS advertises the bus clear feature 972 * and enables the SCL/SDA stuck low. SMU FW does the 973 * bus recovery process. Driver should not ignore this BIOS 974 * advertisement of bus clear feature. 975 */ 976 ret = regmap_read(dev->map, DW_IC_CON, &ic_con); 977 i2c_dw_release_lock(dev); 978 if (ret) 979 return ret; 980 981 if (ic_con & DW_IC_CON_BUS_CLEAR_CTRL) 982 dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL; 983 984 ret = dev->init(dev); 985 if (ret) 986 return ret; 987 988 snprintf(adap->name, sizeof(adap->name), 989 "Synopsys DesignWare I2C adapter"); 990 adap->retries = 3; 991 adap->algo = &i2c_dw_algo; 992 adap->quirks = &i2c_dw_quirks; 993 adap->dev.parent = dev->dev; 994 i2c_set_adapdata(adap, dev); 995 996 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { 997 irq_flags = IRQF_NO_SUSPEND; 998 } else { 999 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND; 1000 } 1001 1002 ret = i2c_dw_acquire_lock(dev); 1003 if (ret) 1004 return ret; 1005 1006 __i2c_dw_write_intr_mask(dev, 0); 1007 i2c_dw_release_lock(dev); 1008 1009 if (!(dev->flags & ACCESS_POLLING)) { 1010 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, 1011 irq_flags, dev_name(dev->dev), dev); 1012 if (ret) { 1013 dev_err(dev->dev, "failure requesting irq %i: %d\n", 1014 dev->irq, ret); 1015 return ret; 1016 } 1017 } 1018 1019 ret = i2c_dw_init_recovery_info(dev); 1020 if (ret) 1021 return ret; 1022 1023 /* 1024 * Increment PM usage count during adapter registration in order to 1025 * avoid possible spurious runtime suspend when adapter device is 1026 * registered to the device core and immediate resume in case bus has 1027 * registered I2C slaves that do I2C transfers in their probe. 1028 */ 1029 pm_runtime_get_noresume(dev->dev); 1030 ret = i2c_add_numbered_adapter(adap); 1031 if (ret) 1032 dev_err(dev->dev, "failure adding adapter: %d\n", ret); 1033 pm_runtime_put_noidle(dev->dev); 1034 1035 return ret; 1036 } 1037 EXPORT_SYMBOL_GPL(i2c_dw_probe_master); 1038 1039 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter"); 1040 MODULE_LICENSE("GPL"); 1041 MODULE_IMPORT_NS(I2C_DW_COMMON); 1042