1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Synopsys DesignWare I2C adapter driver (master only). 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 12 #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW" 13 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/errno.h> 17 #include <linux/export.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/i2c.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/module.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/regmap.h> 26 #include <linux/reset.h> 27 28 #include <linux/designware_i2c.h> 29 30 #include "i2c-designware-core.h" 31 32 #define AMD_TIMEOUT_MIN_US 25 33 #define AMD_TIMEOUT_MAX_US 250 34 #define AMD_MASTERCFG_MASK GENMASK(15, 0) 35 36 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) 37 { 38 unsigned int comp_param1; 39 u32 sda_falling_time, scl_falling_time; 40 struct i2c_timings *t = &dev->timings; 41 const char *fp_str = ""; 42 u32 ic_clk; 43 int ret; 44 45 ret = i2c_dw_acquire_lock(dev); 46 if (ret) 47 return ret; 48 49 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); 50 i2c_dw_release_lock(dev); 51 if (ret) 52 return ret; 53 54 /* Set standard and fast speed dividers for high/low periods */ 55 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ 56 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ 57 58 /* Calculate SCL timing parameters for standard mode if not set */ 59 if (!dev->ss_hcnt || !dev->ss_lcnt) { 60 ic_clk = i2c_dw_clk_rate(dev); 61 dev->ss_hcnt = 62 i2c_dw_scl_hcnt(dev, 63 DW_IC_SS_SCL_HCNT, 64 ic_clk, 65 4000, /* tHD;STA = tHIGH = 4.0 us */ 66 sda_falling_time, 67 0); /* No offset */ 68 dev->ss_lcnt = 69 i2c_dw_scl_lcnt(dev, 70 DW_IC_SS_SCL_LCNT, 71 ic_clk, 72 4700, /* tLOW = 4.7 us */ 73 scl_falling_time, 74 0); /* No offset */ 75 } 76 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", 77 dev->ss_hcnt, dev->ss_lcnt); 78 79 /* 80 * Set SCL timing parameters for fast mode or fast mode plus. Only 81 * difference is the timing parameter values since the registers are 82 * the same. 83 */ 84 if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) { 85 /* 86 * Check are Fast Mode Plus parameters available. Calculate 87 * SCL timing parameters for Fast Mode Plus if not set. 88 */ 89 if (dev->fp_hcnt && dev->fp_lcnt) { 90 dev->fs_hcnt = dev->fp_hcnt; 91 dev->fs_lcnt = dev->fp_lcnt; 92 } else { 93 ic_clk = i2c_dw_clk_rate(dev); 94 dev->fs_hcnt = 95 i2c_dw_scl_hcnt(dev, 96 DW_IC_FS_SCL_HCNT, 97 ic_clk, 98 260, /* tHIGH = 260 ns */ 99 sda_falling_time, 100 0); /* No offset */ 101 dev->fs_lcnt = 102 i2c_dw_scl_lcnt(dev, 103 DW_IC_FS_SCL_LCNT, 104 ic_clk, 105 500, /* tLOW = 500 ns */ 106 scl_falling_time, 107 0); /* No offset */ 108 } 109 fp_str = " Plus"; 110 } 111 /* 112 * Calculate SCL timing parameters for fast mode if not set. They are 113 * needed also in high speed mode. 114 */ 115 if (!dev->fs_hcnt || !dev->fs_lcnt) { 116 ic_clk = i2c_dw_clk_rate(dev); 117 dev->fs_hcnt = 118 i2c_dw_scl_hcnt(dev, 119 DW_IC_FS_SCL_HCNT, 120 ic_clk, 121 600, /* tHD;STA = tHIGH = 0.6 us */ 122 sda_falling_time, 123 0); /* No offset */ 124 dev->fs_lcnt = 125 i2c_dw_scl_lcnt(dev, 126 DW_IC_FS_SCL_LCNT, 127 ic_clk, 128 1300, /* tLOW = 1.3 us */ 129 scl_falling_time, 130 0); /* No offset */ 131 } 132 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", 133 fp_str, dev->fs_hcnt, dev->fs_lcnt); 134 135 /* Check is high speed possible and fall back to fast mode if not */ 136 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == 137 DW_IC_CON_SPEED_HIGH) { 138 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK) 139 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) { 140 dev_err(dev->dev, "High Speed not supported!\n"); 141 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; 142 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; 143 dev->master_cfg |= DW_IC_CON_SPEED_FAST; 144 dev->hs_hcnt = 0; 145 dev->hs_lcnt = 0; 146 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { 147 u32 t_high, t_low; 148 149 /* 150 * The legal values stated in the databook for bus 151 * capacitance are only 100pF and 400pF. 152 * If dev->bus_capacitance_pF is greater than or equals 153 * to 400, t_high and t_low are assumed to be 154 * appropriate values for 400pF, otherwise 100pF. 155 */ 156 if (dev->bus_capacitance_pF >= 400) { 157 /* assume bus capacitance is 400pF */ 158 t_high = dev->clk_freq_optimized ? 160 : 120; 159 t_low = 320; 160 } else { 161 /* assume bus capacitance is 100pF */ 162 t_high = 60; 163 t_low = dev->clk_freq_optimized ? 120 : 160; 164 } 165 166 ic_clk = i2c_dw_clk_rate(dev); 167 dev->hs_hcnt = 168 i2c_dw_scl_hcnt(dev, 169 DW_IC_HS_SCL_HCNT, 170 ic_clk, 171 t_high, 172 sda_falling_time, 173 0); /* No offset */ 174 dev->hs_lcnt = 175 i2c_dw_scl_lcnt(dev, 176 DW_IC_HS_SCL_LCNT, 177 ic_clk, 178 t_low, 179 scl_falling_time, 180 0); /* No offset */ 181 } 182 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", 183 dev->hs_hcnt, dev->hs_lcnt); 184 } 185 186 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); 187 return 0; 188 } 189 190 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) 191 { 192 struct i2c_msg *msgs = dev->msgs; 193 u32 ic_con = 0, ic_tar = 0; 194 unsigned int dummy; 195 196 /* Disable the adapter */ 197 __i2c_dw_disable(dev); 198 199 i2c_dw_set_mode(dev, DW_IC_MASTER); 200 201 /* If the slave address is ten bit address, enable 10BITADDR */ 202 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { 203 ic_con = DW_IC_CON_10BITADDR_MASTER; 204 /* 205 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing 206 * mode has to be enabled via bit 12 of IC_TAR register. 207 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be 208 * detected from registers. 209 */ 210 ic_tar = DW_IC_TAR_10BITADDR_MASTER; 211 } 212 213 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER, 214 ic_con); 215 216 /* 217 * Set the slave (target) address and enable 10-bit addressing mode 218 * if applicable. 219 */ 220 regmap_write(dev->map, DW_IC_TAR, 221 msgs[dev->msg_write_idx].addr | ic_tar); 222 223 /* Enforce disabled interrupts (due to HW issues) */ 224 __i2c_dw_write_intr_mask(dev, 0); 225 226 /* Enable the adapter */ 227 __i2c_dw_enable(dev); 228 229 /* Dummy read to avoid the register getting stuck on Bay Trail */ 230 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy); 231 232 /* Clear and enable interrupts */ 233 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); 234 __i2c_dw_write_intr_mask(dev, DW_IC_INTR_MASTER_MASK); 235 } 236 237 /* 238 * This function waits for the controller to be idle before disabling I2C 239 * When the controller is not in the IDLE state, the MST_ACTIVITY bit 240 * (IC_STATUS[5]) is set. 241 * 242 * Values: 243 * 0x1 (ACTIVE): Controller not idle 244 * 0x0 (IDLE): Controller is idle 245 * 246 * The function is called after completing the current transfer. 247 * 248 * Returns: 249 * False when the controller is in the IDLE state. 250 * True when the controller is in the ACTIVE state. 251 */ 252 static bool i2c_dw_is_controller_active(struct dw_i2c_dev *dev) 253 { 254 u32 status; 255 256 regmap_read(dev->map, DW_IC_STATUS, &status); 257 if (!(status & DW_IC_STATUS_MASTER_ACTIVITY)) 258 return false; 259 260 return regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, 261 !(status & DW_IC_STATUS_MASTER_ACTIVITY), 262 1100, 20000) != 0; 263 } 264 265 static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev) 266 { 267 u32 val; 268 int ret; 269 270 ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val, 271 !(val & DW_IC_INTR_STOP_DET), 272 1100, 20000); 273 if (ret) 274 dev_err(dev->dev, "i2c timeout error %d\n", ret); 275 276 return ret; 277 } 278 279 static int i2c_dw_status(struct dw_i2c_dev *dev) 280 { 281 int status; 282 283 status = i2c_dw_wait_bus_not_busy(dev); 284 if (status) 285 return status; 286 287 return i2c_dw_check_stopbit(dev); 288 } 289 290 /* 291 * Initiate and continue master read/write transaction with polling 292 * based transfer routine afterward write messages into the Tx buffer. 293 */ 294 static int amd_i2c_dw_xfer_quirk(struct dw_i2c_dev *dev, struct i2c_msg *msgs, int num_msgs) 295 { 296 int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx; 297 int cmd = 0, status; 298 u8 *tx_buf; 299 unsigned int val; 300 301 PM_RUNTIME_ACQUIRE_AUTOSUSPEND(dev->dev, pm); 302 if (PM_RUNTIME_ACQUIRE_ERR(&pm)) 303 return -ENXIO; 304 305 /* 306 * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card, 307 * it is mandatory to set the right value in specific register 308 * (offset:0x474) as per the hardware IP specification. 309 */ 310 regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN); 311 312 dev->msgs = msgs; 313 dev->msgs_num = num_msgs; 314 dev->msg_write_idx = 0; 315 i2c_dw_xfer_init(dev); 316 317 /* Initiate messages read/write transaction */ 318 for (msg_wrt_idx = 0; msg_wrt_idx < num_msgs; msg_wrt_idx++) { 319 tx_buf = msgs[msg_wrt_idx].buf; 320 buf_len = msgs[msg_wrt_idx].len; 321 322 if (!(msgs[msg_wrt_idx].flags & I2C_M_RD)) 323 regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1); 324 /* 325 * Initiate the i2c read/write transaction of buffer length, 326 * and poll for bus busy status. For the last message transfer, 327 * update the command with stop bit enable. 328 */ 329 for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) { 330 if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1) 331 cmd |= BIT(9); 332 333 if (msgs[msg_wrt_idx].flags & I2C_M_RD) { 334 /* Due to hardware bug, need to write the same command twice. */ 335 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100); 336 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd); 337 if (cmd) { 338 regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1)); 339 regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1)); 340 /* 341 * Need to check the stop bit. However, it cannot be 342 * detected from the registers so we check it always 343 * when read/write the last byte. 344 */ 345 status = i2c_dw_status(dev); 346 if (status) 347 return status; 348 349 for (data_idx = 0; data_idx < buf_len; data_idx++) { 350 regmap_read(dev->map, DW_IC_DATA_CMD, &val); 351 tx_buf[data_idx] = val; 352 } 353 status = i2c_dw_check_stopbit(dev); 354 if (status) 355 return status; 356 } 357 } else { 358 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd); 359 usleep_range(AMD_TIMEOUT_MIN_US, AMD_TIMEOUT_MAX_US); 360 } 361 } 362 status = i2c_dw_check_stopbit(dev); 363 if (status) 364 return status; 365 } 366 367 return 0; 368 } 369 370 /* 371 * Initiate (and continue) low level master read/write transaction. 372 * This function is only called from i2c_dw_isr(), and pumping i2c_msg 373 * messages into the tx buffer. Even if the size of i2c_msg data is 374 * longer than the size of the tx buffer, it handles everything. 375 */ 376 static void 377 i2c_dw_xfer_msg(struct dw_i2c_dev *dev) 378 { 379 struct i2c_msg *msgs = dev->msgs; 380 u32 intr_mask; 381 int tx_limit, rx_limit; 382 u32 buf_len = dev->tx_buf_len; 383 u8 *buf = dev->tx_buf; 384 bool need_restart = false; 385 unsigned int flr; 386 387 intr_mask = DW_IC_INTR_MASTER_MASK; 388 389 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { 390 u32 flags = msgs[dev->msg_write_idx].flags; 391 392 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { 393 /* new i2c_msg */ 394 buf = msgs[dev->msg_write_idx].buf; 395 buf_len = msgs[dev->msg_write_idx].len; 396 397 /* 398 * If both IC_EMPTYFIFO_HOLD_MASTER_EN and 399 * IC_RESTART_EN are set, we must manually 400 * set restart bit between messages. 401 */ 402 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && 403 (dev->msg_write_idx > 0)) 404 need_restart = true; 405 } 406 407 regmap_read(dev->map, DW_IC_TXFLR, &flr); 408 tx_limit = dev->tx_fifo_depth - flr; 409 410 regmap_read(dev->map, DW_IC_RXFLR, &flr); 411 rx_limit = dev->rx_fifo_depth - flr; 412 413 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { 414 u32 cmd = 0; 415 416 /* 417 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must 418 * manually set the stop bit. However, it cannot be 419 * detected from the registers so we set it always 420 * when writing/reading the last byte. 421 */ 422 423 /* 424 * i2c-core always sets the buffer length of 425 * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will 426 * be adjusted when receiving the first byte. 427 * Thus we can't stop the transaction here. 428 */ 429 if (dev->msg_write_idx == dev->msgs_num - 1 && 430 buf_len == 1 && !(flags & I2C_M_RECV_LEN)) 431 cmd |= BIT(9); 432 433 if (need_restart) { 434 cmd |= BIT(10); 435 need_restart = false; 436 } 437 438 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { 439 440 /* Avoid rx buffer overrun */ 441 if (dev->rx_outstanding >= dev->rx_fifo_depth) 442 break; 443 444 regmap_write(dev->map, DW_IC_DATA_CMD, 445 cmd | 0x100); 446 rx_limit--; 447 dev->rx_outstanding++; 448 } else { 449 regmap_write(dev->map, DW_IC_DATA_CMD, 450 cmd | *buf++); 451 } 452 tx_limit--; buf_len--; 453 } 454 455 dev->tx_buf = buf; 456 dev->tx_buf_len = buf_len; 457 458 /* 459 * Because we don't know the buffer length in the 460 * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop the 461 * transaction here. Also disable the TX_EMPTY IRQ 462 * while waiting for the data length byte to avoid the 463 * bogus interrupts flood. 464 */ 465 if (flags & I2C_M_RECV_LEN) { 466 dev->status |= STATUS_WRITE_IN_PROGRESS; 467 intr_mask &= ~DW_IC_INTR_TX_EMPTY; 468 break; 469 } else if (buf_len > 0) { 470 /* more bytes to be written */ 471 dev->status |= STATUS_WRITE_IN_PROGRESS; 472 break; 473 } else 474 dev->status &= ~STATUS_WRITE_IN_PROGRESS; 475 } 476 477 /* 478 * If i2c_msg index search is completed, we don't need TX_EMPTY 479 * interrupt any more. 480 */ 481 if (dev->msg_write_idx == dev->msgs_num) 482 intr_mask &= ~DW_IC_INTR_TX_EMPTY; 483 484 if (dev->msg_err) 485 intr_mask = 0; 486 487 __i2c_dw_write_intr_mask(dev, intr_mask); 488 } 489 490 static u8 491 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len) 492 { 493 struct i2c_msg *msgs = dev->msgs; 494 u32 flags = msgs[dev->msg_read_idx].flags; 495 unsigned int intr_mask; 496 497 /* 498 * Adjust the buffer length and mask the flag 499 * after receiving the first byte. 500 */ 501 len += (flags & I2C_CLIENT_PEC) ? 2 : 1; 502 dev->tx_buf_len = len - min(len, dev->rx_outstanding); 503 msgs[dev->msg_read_idx].len = len; 504 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; 505 506 /* 507 * Received buffer length, re-enable TX_EMPTY interrupt 508 * to resume the SMBUS transaction. 509 */ 510 __i2c_dw_read_intr_mask(dev, &intr_mask); 511 intr_mask |= DW_IC_INTR_TX_EMPTY; 512 __i2c_dw_write_intr_mask(dev, intr_mask); 513 514 return len; 515 } 516 517 static void 518 i2c_dw_read(struct dw_i2c_dev *dev) 519 { 520 struct i2c_msg *msgs = dev->msgs; 521 unsigned int rx_valid; 522 523 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { 524 u32 flags = msgs[dev->msg_read_idx].flags; 525 unsigned int tmp; 526 u32 len; 527 u8 *buf; 528 529 if (!(flags & I2C_M_RD)) 530 continue; 531 532 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { 533 len = msgs[dev->msg_read_idx].len; 534 buf = msgs[dev->msg_read_idx].buf; 535 } else { 536 len = dev->rx_buf_len; 537 buf = dev->rx_buf; 538 } 539 540 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); 541 542 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { 543 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); 544 tmp &= DW_IC_DATA_CMD_DAT; 545 /* Ensure length byte is a valid value */ 546 if (flags & I2C_M_RECV_LEN) { 547 /* 548 * if IC_EMPTYFIFO_HOLD_MASTER_EN is set, which cannot be 549 * detected from the registers, the controller can be 550 * disabled if the STOP bit is set. But it is only set 551 * after receiving block data response length in 552 * I2C_FUNC_SMBUS_BLOCK_DATA case. That needs to read 553 * another byte with STOP bit set when the block data 554 * response length is invalid to complete the transaction. 555 */ 556 if (!tmp || tmp > I2C_SMBUS_BLOCK_MAX) 557 tmp = 1; 558 559 len = i2c_dw_recv_len(dev, tmp); 560 } 561 *buf++ = tmp; 562 dev->rx_outstanding--; 563 } 564 565 if (len > 0) { 566 dev->status |= STATUS_READ_IN_PROGRESS; 567 dev->rx_buf_len = len; 568 dev->rx_buf = buf; 569 return; 570 } else 571 dev->status &= ~STATUS_READ_IN_PROGRESS; 572 } 573 } 574 575 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) 576 { 577 unsigned int stat, dummy; 578 579 /* 580 * The IC_INTR_STAT register just indicates "enabled" interrupts. 581 * The unmasked raw version of interrupt status bits is available 582 * in the IC_RAW_INTR_STAT register. 583 * 584 * That is, 585 * stat = readl(IC_INTR_STAT); 586 * equals to, 587 * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); 588 * 589 * The raw version might be useful for debugging purposes. 590 */ 591 if (!(dev->flags & ACCESS_POLLING)) { 592 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); 593 } else { 594 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); 595 stat &= dev->sw_mask; 596 } 597 598 /* 599 * Do not use the IC_CLR_INTR register to clear interrupts, or 600 * you'll miss some interrupts, triggered during the period from 601 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). 602 * 603 * Instead, use the separately-prepared IC_CLR_* registers. 604 */ 605 if (stat & DW_IC_INTR_RX_UNDER) 606 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); 607 if (stat & DW_IC_INTR_RX_OVER) 608 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); 609 if (stat & DW_IC_INTR_TX_OVER) 610 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); 611 if (stat & DW_IC_INTR_RD_REQ) 612 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy); 613 if (stat & DW_IC_INTR_TX_ABRT) { 614 /* 615 * The IC_TX_ABRT_SOURCE register is cleared whenever 616 * the IC_CLR_TX_ABRT is read. Preserve it beforehand. 617 */ 618 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source); 619 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); 620 } 621 if (stat & DW_IC_INTR_RX_DONE) 622 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); 623 if (stat & DW_IC_INTR_ACTIVITY) 624 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); 625 if ((stat & DW_IC_INTR_STOP_DET) && 626 ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL))) 627 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); 628 if (stat & DW_IC_INTR_START_DET) 629 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); 630 if (stat & DW_IC_INTR_GEN_CALL) 631 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); 632 633 return stat; 634 } 635 636 static void i2c_dw_process_transfer(struct dw_i2c_dev *dev, unsigned int stat) 637 { 638 if (stat & DW_IC_INTR_TX_ABRT) { 639 dev->cmd_err |= DW_IC_ERR_TX_ABRT; 640 dev->status &= ~STATUS_MASK; 641 dev->rx_outstanding = 0; 642 643 /* 644 * Anytime TX_ABRT is set, the contents of the tx/rx 645 * buffers are flushed. Make sure to skip them. 646 */ 647 __i2c_dw_write_intr_mask(dev, 0); 648 goto tx_aborted; 649 } 650 651 if (stat & DW_IC_INTR_RX_FULL) 652 i2c_dw_read(dev); 653 654 if (stat & DW_IC_INTR_TX_EMPTY) 655 i2c_dw_xfer_msg(dev); 656 657 /* Abort if we detect a STOP in the middle of a read or a write */ 658 if ((stat & DW_IC_INTR_STOP_DET) && 659 (dev->status & (STATUS_READ_IN_PROGRESS | STATUS_WRITE_IN_PROGRESS))) { 660 dev_err(dev->dev, "spurious STOP detected\n"); 661 dev->rx_outstanding = 0; 662 dev->msg_err = -EIO; 663 } 664 665 /* 666 * No need to modify or disable the interrupt mask here. 667 * i2c_dw_xfer_msg() will take care of it according to 668 * the current transmit status. 669 */ 670 671 tx_aborted: 672 if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) && 673 (dev->rx_outstanding == 0)) 674 complete(&dev->cmd_complete); 675 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { 676 /* Workaround to trigger pending interrupt */ 677 __i2c_dw_read_intr_mask(dev, &stat); 678 __i2c_dw_write_intr_mask(dev, 0); 679 __i2c_dw_write_intr_mask(dev, stat); 680 } 681 } 682 683 /* 684 * Interrupt service routine. This gets called whenever an I2C master interrupt 685 * occurs. 686 */ 687 irqreturn_t i2c_dw_isr_master(struct dw_i2c_dev *dev) 688 { 689 unsigned int stat, enabled; 690 691 regmap_read(dev->map, DW_IC_ENABLE, &enabled); 692 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); 693 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) 694 return IRQ_NONE; 695 if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0)) 696 return IRQ_NONE; 697 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); 698 699 stat = i2c_dw_read_clear_intrbits(dev); 700 701 if (!(dev->status & STATUS_ACTIVE)) { 702 /* 703 * Unexpected interrupt in driver point of view. State 704 * variables are either unset or stale so acknowledge and 705 * disable interrupts for suppressing further interrupts if 706 * interrupt really came from this HW (E.g. firmware has left 707 * the HW active). 708 */ 709 __i2c_dw_write_intr_mask(dev, 0); 710 return IRQ_HANDLED; 711 } 712 713 i2c_dw_process_transfer(dev, stat); 714 715 return IRQ_HANDLED; 716 } 717 718 static int i2c_dw_wait_transfer(struct dw_i2c_dev *dev) 719 { 720 unsigned long timeout = dev->adapter.timeout; 721 unsigned int stat; 722 int ret; 723 724 if (!(dev->flags & ACCESS_POLLING)) { 725 ret = wait_for_completion_timeout(&dev->cmd_complete, timeout); 726 } else { 727 timeout += jiffies; 728 do { 729 ret = try_wait_for_completion(&dev->cmd_complete); 730 if (ret) 731 break; 732 733 stat = i2c_dw_read_clear_intrbits(dev); 734 if (stat) 735 i2c_dw_process_transfer(dev, stat); 736 else 737 /* Try save some power */ 738 usleep_range(3, 25); 739 } while (time_before(jiffies, timeout)); 740 } 741 742 return ret ? 0 : -ETIMEDOUT; 743 } 744 745 /* 746 * Prepare controller for a transaction, start the transfer of the @msgs 747 * and wait for completion, either a STOP or a error. 748 * Return: 0 or a negative error code. 749 */ 750 static int 751 __i2c_dw_xfer_one_part(struct dw_i2c_dev *dev, struct i2c_msg *msgs, size_t num) 752 { 753 int ret; 754 755 reinit_completion(&dev->cmd_complete); 756 dev->msgs = msgs; 757 dev->msgs_num = num; 758 dev->cmd_err = 0; 759 dev->msg_write_idx = 0; 760 dev->msg_read_idx = 0; 761 dev->msg_err = 0; 762 dev->status = 0; 763 dev->abort_source = 0; 764 dev->rx_outstanding = 0; 765 766 ret = i2c_dw_wait_bus_not_busy(dev); 767 if (ret < 0) 768 return ret; 769 770 /* Start the transfers */ 771 i2c_dw_xfer_init(dev); 772 773 /* Wait for tx to complete */ 774 ret = i2c_dw_wait_transfer(dev); 775 if (ret) { 776 dev_err(dev->dev, "controller timed out\n"); 777 /* i2c_dw_init() implicitly disables the adapter */ 778 i2c_recover_bus(&dev->adapter); 779 i2c_dw_init(dev); 780 return ret; 781 } 782 783 /* 784 * This happens rarely (~1:500) and is hard to reproduce. Debug trace 785 * showed that IC_STATUS had value of 0x23 when STOP_DET occurred, 786 * if disable IC_ENABLE.ENABLE immediately that can result in 787 * IC_RAW_INTR_STAT.MASTER_ON_HOLD holding SCL low. Check if 788 * controller is still ACTIVE before disabling I2C. 789 */ 790 if (i2c_dw_is_controller_active(dev)) { 791 /* 792 * If the controller is still active after the timeout, attempt a 793 * bus recovery to clear any potentially locked state. 794 */ 795 dev_err(dev->dev, "controller active after xfer, recovering\n"); 796 i2c_recover_bus(&dev->adapter); 797 i2c_dw_init(dev); 798 } else { 799 /* 800 * We must disable the adapter before returning and signaling the end 801 * of the current transfer. Otherwise the hardware might continue 802 * generating interrupts which in turn causes a race condition with 803 * the following transfer. Needs some more investigation if the 804 * additional interrupts are a hardware bug or this driver doesn't 805 * handle them correctly yet. 806 */ 807 __i2c_dw_disable_nowait(dev); 808 } 809 810 if (dev->msg_err) 811 return dev->msg_err; 812 813 /* No error */ 814 if (likely(!dev->cmd_err && !dev->status)) 815 return 0; 816 817 /* We have an error */ 818 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) 819 return i2c_dw_handle_tx_abort(dev); 820 821 if (dev->status) 822 dev_err(dev->dev, 823 "transfer terminated early - interrupt latency too high?\n"); 824 825 return -EIO; 826 } 827 828 /* 829 * Verify that the message at index @idx can be processed as part 830 * of a single transaction. The @msgs array contains the messages 831 * of the transaction. The message is checked against its predecessor 832 * to ensure that it respects the limitation of the controller. 833 * Return: true if the message can be processed, false otherwise. 834 */ 835 static bool 836 i2c_dw_msg_is_valid(struct dw_i2c_dev *dev, const struct i2c_msg *msgs, size_t idx) 837 { 838 /* 839 * The first message of a transaction is valid, 840 * no constraints from a previous message. 841 */ 842 if (!idx) 843 return true; 844 845 /* 846 * We cannot change the target address during a transaction, so make 847 * sure the address is identical to the one of the previous message. 848 */ 849 if (msgs[idx - 1].addr != msgs[idx].addr) { 850 dev_err(dev->dev, "invalid target address\n"); 851 return false; 852 } 853 854 /* 855 * Make sure we don't need explicit RESTART between two messages 856 * in the same direction for controllers that cannot emit them. 857 */ 858 if (!dev->emptyfifo_hold_master && 859 (msgs[idx - 1].flags & I2C_M_RD) == (msgs[idx].flags & I2C_M_RD)) { 860 dev_err(dev->dev, "cannot emit RESTART\n"); 861 return false; 862 } 863 864 return true; 865 } 866 867 static int 868 i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_msg msgs[], int num) 869 { 870 struct i2c_msg *msgs_part; 871 size_t cnt; 872 int ret; 873 874 dev_dbg(dev->dev, "msgs: %d\n", num); 875 876 PM_RUNTIME_ACQUIRE_AUTOSUSPEND(dev->dev, pm); 877 if (PM_RUNTIME_ACQUIRE_ERR(&pm)) 878 return -ENXIO; 879 880 ret = i2c_dw_acquire_lock(dev); 881 if (ret) 882 return ret; 883 884 /* 885 * If the I2C_M_STOP is present in some the messages, 886 * we do one transaction for each part up to the STOP. 887 */ 888 for (msgs_part = msgs; msgs_part < msgs + num; msgs_part += cnt) { 889 /* 890 * Count the messages in a transaction, up to a STOP or 891 * the end of the msgs. The last if below guarantees that 892 * we check all messages and that msg_parts and cnt are 893 * in-bounds of msgs and num. 894 */ 895 for (cnt = 1; ; cnt++) { 896 if (!i2c_dw_msg_is_valid(dev, msgs_part, cnt - 1)) { 897 ret = -EINVAL; 898 break; 899 } 900 901 if ((msgs_part[cnt - 1].flags & I2C_M_STOP) || 902 (msgs_part + cnt == msgs + num)) 903 break; 904 } 905 if (ret < 0) 906 break; 907 908 /* transfer one part up to a STOP */ 909 ret = __i2c_dw_xfer_one_part(dev, msgs_part, cnt); 910 if (ret < 0) 911 break; 912 } 913 914 i2c_dw_set_mode(dev, DW_IC_SLAVE); 915 916 i2c_dw_release_lock(dev); 917 918 if (ret < 0) 919 return ret; 920 return num; 921 } 922 923 int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 924 { 925 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 926 927 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) 928 return amd_i2c_dw_xfer_quirk(dev, msgs, num); 929 930 return i2c_dw_xfer_common(dev, msgs, num); 931 } 932 933 void i2c_dw_configure_master(struct dw_i2c_dev *dev) 934 { 935 struct i2c_timings *t = &dev->timings; 936 937 dev->functionality |= I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; 938 939 /* amd_i2c_dw_xfer_quirk() does not implement protocol mangling */ 940 if ((dev->flags & MODEL_MASK) != MODEL_AMD_NAVI_GPU) 941 dev->functionality |= I2C_FUNC_PROTOCOL_MANGLING; 942 943 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | 944 DW_IC_CON_RESTART_EN; 945 946 dev->mode = DW_IC_MASTER; 947 948 switch (t->bus_freq_hz) { 949 case I2C_MAX_STANDARD_MODE_FREQ: 950 dev->master_cfg |= DW_IC_CON_SPEED_STD; 951 break; 952 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 953 dev->master_cfg |= DW_IC_CON_SPEED_HIGH; 954 break; 955 default: 956 dev->master_cfg |= DW_IC_CON_SPEED_FAST; 957 } 958 } 959 EXPORT_SYMBOL_GPL(i2c_dw_configure_master); 960 961 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap) 962 { 963 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 964 965 i2c_dw_disable(dev); 966 reset_control_assert(dev->rst); 967 i2c_dw_prepare_clk(dev, false); 968 } 969 970 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap) 971 { 972 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 973 974 i2c_dw_prepare_clk(dev, true); 975 reset_control_deassert(dev->rst); 976 i2c_dw_init(dev); 977 } 978 979 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev) 980 { 981 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; 982 struct i2c_adapter *adap = &dev->adapter; 983 struct gpio_desc *gpio; 984 985 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH); 986 if (IS_ERR_OR_NULL(gpio)) 987 return PTR_ERR_OR_ZERO(gpio); 988 989 rinfo->scl_gpiod = gpio; 990 991 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); 992 if (IS_ERR(gpio)) 993 return PTR_ERR(gpio); 994 rinfo->sda_gpiod = gpio; 995 996 rinfo->pinctrl = devm_pinctrl_get(dev->dev); 997 if (IS_ERR(rinfo->pinctrl)) { 998 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER) 999 return PTR_ERR(rinfo->pinctrl); 1000 1001 rinfo->pinctrl = NULL; 1002 dev_err(dev->dev, "getting pinctrl info failed: bus recovery might not work\n"); 1003 } else if (!rinfo->pinctrl) { 1004 dev_dbg(dev->dev, "pinctrl is disabled, bus recovery might not work\n"); 1005 } 1006 1007 rinfo->recover_bus = i2c_generic_scl_recovery; 1008 rinfo->prepare_recovery = i2c_dw_prepare_recovery; 1009 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; 1010 adap->bus_recovery_info = rinfo; 1011 1012 dev_info(dev->dev, "running with GPIO recovery mode! scl%s", 1013 rinfo->sda_gpiod ? ",sda" : ""); 1014 1015 return 0; 1016 } 1017 1018 int i2c_dw_probe_master(struct dw_i2c_dev *dev) 1019 { 1020 unsigned int ic_con; 1021 int ret; 1022 1023 init_completion(&dev->cmd_complete); 1024 1025 ret = i2c_dw_set_timings_master(dev); 1026 if (ret) 1027 return ret; 1028 1029 /* Lock the bus for accessing DW_IC_CON */ 1030 ret = i2c_dw_acquire_lock(dev); 1031 if (ret) 1032 return ret; 1033 1034 /* 1035 * On AMD platforms BIOS advertises the bus clear feature 1036 * and enables the SCL/SDA stuck low. SMU FW does the 1037 * bus recovery process. Driver should not ignore this BIOS 1038 * advertisement of bus clear feature. 1039 */ 1040 ret = regmap_read(dev->map, DW_IC_CON, &ic_con); 1041 i2c_dw_release_lock(dev); 1042 if (ret) 1043 return ret; 1044 1045 if (ic_con & DW_IC_CON_BUS_CLEAR_CTRL) 1046 dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL; 1047 1048 return i2c_dw_init_recovery_info(dev); 1049 } 1050 1051 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter"); 1052 MODULE_LICENSE("GPL"); 1053 MODULE_IMPORT_NS("I2C_DW_COMMON"); 1054