1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Synopsys DesignWare I2C adapter driver. 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 12 #include <linux/bits.h> 13 #include <linux/completion.h> 14 #include <linux/errno.h> 15 #include <linux/i2c.h> 16 #include <linux/pm.h> 17 #include <linux/regmap.h> 18 #include <linux/types.h> 19 20 #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ 21 I2C_FUNC_SMBUS_BYTE | \ 22 I2C_FUNC_SMBUS_BYTE_DATA | \ 23 I2C_FUNC_SMBUS_WORD_DATA | \ 24 I2C_FUNC_SMBUS_BLOCK_DATA | \ 25 I2C_FUNC_SMBUS_I2C_BLOCK) 26 27 #define DW_IC_CON_MASTER BIT(0) 28 #define DW_IC_CON_SPEED_STD (1 << 1) 29 #define DW_IC_CON_SPEED_FAST (2 << 1) 30 #define DW_IC_CON_SPEED_HIGH (3 << 1) 31 #define DW_IC_CON_SPEED_MASK GENMASK(2, 1) 32 #define DW_IC_CON_10BITADDR_SLAVE BIT(3) 33 #define DW_IC_CON_10BITADDR_MASTER BIT(4) 34 #define DW_IC_CON_RESTART_EN BIT(5) 35 #define DW_IC_CON_SLAVE_DISABLE BIT(6) 36 #define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7) 37 #define DW_IC_CON_TX_EMPTY_CTRL BIT(8) 38 #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9) 39 #define DW_IC_CON_BUS_CLEAR_CTRL BIT(11) 40 41 #define DW_IC_DATA_CMD_DAT GENMASK(7, 0) 42 #define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11) 43 44 /* 45 * Registers offset 46 */ 47 #define DW_IC_CON 0x00 48 #define DW_IC_TAR 0x04 49 #define DW_IC_SAR 0x08 50 #define DW_IC_DATA_CMD 0x10 51 #define DW_IC_SS_SCL_HCNT 0x14 52 #define DW_IC_SS_SCL_LCNT 0x18 53 #define DW_IC_FS_SCL_HCNT 0x1c 54 #define DW_IC_FS_SCL_LCNT 0x20 55 #define DW_IC_HS_SCL_HCNT 0x24 56 #define DW_IC_HS_SCL_LCNT 0x28 57 #define DW_IC_INTR_STAT 0x2c 58 #define DW_IC_INTR_MASK 0x30 59 #define DW_IC_RAW_INTR_STAT 0x34 60 #define DW_IC_RX_TL 0x38 61 #define DW_IC_TX_TL 0x3c 62 #define DW_IC_CLR_INTR 0x40 63 #define DW_IC_CLR_RX_UNDER 0x44 64 #define DW_IC_CLR_RX_OVER 0x48 65 #define DW_IC_CLR_TX_OVER 0x4c 66 #define DW_IC_CLR_RD_REQ 0x50 67 #define DW_IC_CLR_TX_ABRT 0x54 68 #define DW_IC_CLR_RX_DONE 0x58 69 #define DW_IC_CLR_ACTIVITY 0x5c 70 #define DW_IC_CLR_STOP_DET 0x60 71 #define DW_IC_CLR_START_DET 0x64 72 #define DW_IC_CLR_GEN_CALL 0x68 73 #define DW_IC_ENABLE 0x6c 74 #define DW_IC_STATUS 0x70 75 #define DW_IC_TXFLR 0x74 76 #define DW_IC_RXFLR 0x78 77 #define DW_IC_SDA_HOLD 0x7c 78 #define DW_IC_TX_ABRT_SOURCE 0x80 79 #define DW_IC_ENABLE_STATUS 0x9c 80 #define DW_IC_CLR_RESTART_DET 0xa8 81 #define DW_IC_COMP_PARAM_1 0xf4 82 #define DW_IC_COMP_VERSION 0xf8 83 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A /* "111*" == v1.11* */ 84 #define DW_IC_COMP_TYPE 0xfc 85 #define DW_IC_COMP_TYPE_VALUE 0x44570140 /* "DW" + 0x0140 */ 86 87 #define DW_IC_INTR_RX_UNDER BIT(0) 88 #define DW_IC_INTR_RX_OVER BIT(1) 89 #define DW_IC_INTR_RX_FULL BIT(2) 90 #define DW_IC_INTR_TX_OVER BIT(3) 91 #define DW_IC_INTR_TX_EMPTY BIT(4) 92 #define DW_IC_INTR_RD_REQ BIT(5) 93 #define DW_IC_INTR_TX_ABRT BIT(6) 94 #define DW_IC_INTR_RX_DONE BIT(7) 95 #define DW_IC_INTR_ACTIVITY BIT(8) 96 #define DW_IC_INTR_STOP_DET BIT(9) 97 #define DW_IC_INTR_START_DET BIT(10) 98 #define DW_IC_INTR_GEN_CALL BIT(11) 99 #define DW_IC_INTR_RESTART_DET BIT(12) 100 #define DW_IC_INTR_MST_ON_HOLD BIT(13) 101 102 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ 103 DW_IC_INTR_TX_ABRT | \ 104 DW_IC_INTR_STOP_DET) 105 #define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \ 106 DW_IC_INTR_TX_EMPTY) 107 #define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \ 108 DW_IC_INTR_RX_UNDER | \ 109 DW_IC_INTR_RD_REQ) 110 111 #define DW_IC_ENABLE_ENABLE BIT(0) 112 #define DW_IC_ENABLE_ABORT BIT(1) 113 114 #define DW_IC_STATUS_ACTIVITY BIT(0) 115 #define DW_IC_STATUS_TFE BIT(2) 116 #define DW_IC_STATUS_RFNE BIT(3) 117 #define DW_IC_STATUS_MASTER_ACTIVITY BIT(5) 118 #define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6) 119 120 #define DW_IC_SDA_HOLD_RX_SHIFT 16 121 #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16) 122 123 #define DW_IC_ERR_TX_ABRT 0x1 124 125 #define DW_IC_TAR_10BITADDR_MASTER BIT(12) 126 127 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3)) 128 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2) 129 130 /* 131 * Sofware status flags 132 */ 133 #define STATUS_ACTIVE BIT(0) 134 #define STATUS_WRITE_IN_PROGRESS BIT(1) 135 #define STATUS_READ_IN_PROGRESS BIT(2) 136 #define STATUS_MASK GENMASK(2, 0) 137 138 /* 139 * operation modes 140 */ 141 #define DW_IC_MASTER 0 142 #define DW_IC_SLAVE 1 143 144 /* 145 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register 146 * 147 * Only expected abort codes are listed here 148 * refer to the datasheet for the full list 149 */ 150 #define ABRT_7B_ADDR_NOACK 0 151 #define ABRT_10ADDR1_NOACK 1 152 #define ABRT_10ADDR2_NOACK 2 153 #define ABRT_TXDATA_NOACK 3 154 #define ABRT_GCALL_NOACK 4 155 #define ABRT_GCALL_READ 5 156 #define ABRT_SBYTE_ACKDET 7 157 #define ABRT_SBYTE_NORSTRT 9 158 #define ABRT_10B_RD_NORSTRT 10 159 #define ABRT_MASTER_DIS 11 160 #define ARB_LOST 12 161 #define ABRT_SLAVE_FLUSH_TXFIFO 13 162 #define ABRT_SLAVE_ARBLOST 14 163 #define ABRT_SLAVE_RD_INTX 15 164 165 #define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK) 166 #define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK) 167 #define DW_IC_TX_ABRT_10ADDR2_NOACK BIT(ABRT_10ADDR2_NOACK) 168 #define DW_IC_TX_ABRT_TXDATA_NOACK BIT(ABRT_TXDATA_NOACK) 169 #define DW_IC_TX_ABRT_GCALL_NOACK BIT(ABRT_GCALL_NOACK) 170 #define DW_IC_TX_ABRT_GCALL_READ BIT(ABRT_GCALL_READ) 171 #define DW_IC_TX_ABRT_SBYTE_ACKDET BIT(ABRT_SBYTE_ACKDET) 172 #define DW_IC_TX_ABRT_SBYTE_NORSTRT BIT(ABRT_SBYTE_NORSTRT) 173 #define DW_IC_TX_ABRT_10B_RD_NORSTRT BIT(ABRT_10B_RD_NORSTRT) 174 #define DW_IC_TX_ABRT_MASTER_DIS BIT(ABRT_MASTER_DIS) 175 #define DW_IC_TX_ARB_LOST BIT(ARB_LOST) 176 #define DW_IC_RX_ABRT_SLAVE_RD_INTX BIT(ABRT_SLAVE_RD_INTX) 177 #define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST) 178 #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO) 179 180 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ 181 DW_IC_TX_ABRT_10ADDR1_NOACK | \ 182 DW_IC_TX_ABRT_10ADDR2_NOACK | \ 183 DW_IC_TX_ABRT_TXDATA_NOACK | \ 184 DW_IC_TX_ABRT_GCALL_NOACK) 185 186 struct clk; 187 struct device; 188 struct reset_control; 189 190 /** 191 * struct dw_i2c_dev - private i2c-designware data 192 * @dev: driver model device node 193 * @map: IO registers map 194 * @sysmap: System controller registers map 195 * @base: IO registers pointer 196 * @ext: Extended IO registers pointer 197 * @cmd_complete: tx completion indicator 198 * @clk: input reference clock 199 * @pclk: clock required to access the registers 200 * @rst: optional reset for the controller 201 * @slave: represent an I2C slave device 202 * @get_clk_rate_khz: callback to retrieve IP specific bus speed 203 * @cmd_err: run time hadware error code 204 * @msgs: points to an array of messages currently being transferred 205 * @msgs_num: the number of elements in msgs 206 * @msg_write_idx: the element index of the current tx message in the msgs array 207 * @tx_buf_len: the length of the current tx buffer 208 * @tx_buf: the current tx buffer 209 * @msg_read_idx: the element index of the current rx message in the msgs array 210 * @rx_buf_len: the length of the current rx buffer 211 * @rx_buf: the current rx buffer 212 * @msg_err: error status of the current transfer 213 * @status: i2c master status, one of STATUS_* 214 * @abort_source: copy of the TX_ABRT_SOURCE register 215 * @sw_mask: SW mask of DW_IC_INTR_MASK used in polling mode 216 * @irq: interrupt number for the i2c master 217 * @flags: platform specific flags like type of IO accessors or model 218 * @adapter: i2c subsystem adapter node 219 * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support 220 * @master_cfg: configuration for the master device 221 * @slave_cfg: configuration for the slave device 222 * @tx_fifo_depth: depth of the hardware tx fifo 223 * @rx_fifo_depth: depth of the hardware rx fifo 224 * @rx_outstanding: current master-rx elements in tx fifo 225 * @timings: bus clock frequency, SDA hold and other timings 226 * @sda_hold_time: SDA hold value 227 * @ss_hcnt: standard speed HCNT value 228 * @ss_lcnt: standard speed LCNT value 229 * @fs_hcnt: fast speed HCNT value 230 * @fs_lcnt: fast speed LCNT value 231 * @fp_hcnt: fast plus HCNT value 232 * @fp_lcnt: fast plus LCNT value 233 * @hs_hcnt: high speed HCNT value 234 * @hs_lcnt: high speed LCNT value 235 * @acquire_lock: function to acquire a hardware lock on the bus 236 * @release_lock: function to release a hardware lock on the bus 237 * @semaphore_idx: Index of table with semaphore type attached to the bus. It's 238 * -1 if there is no semaphore. 239 * @shared_with_punit: true if this bus is shared with the SoCs PUNIT 240 * @init: function to initialize the I2C hardware 241 * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing 242 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE 243 * @rinfo: I²C GPIO recovery information 244 * 245 * HCNT and LCNT parameters can be used if the platform knows more accurate 246 * values than the one computed based only on the input clock frequency. 247 * Leave them to be %0 if not used. 248 */ 249 struct dw_i2c_dev { 250 struct device *dev; 251 struct regmap *map; 252 struct regmap *sysmap; 253 void __iomem *base; 254 void __iomem *ext; 255 struct completion cmd_complete; 256 struct clk *clk; 257 struct clk *pclk; 258 struct reset_control *rst; 259 struct i2c_client *slave; 260 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev); 261 int cmd_err; 262 struct i2c_msg *msgs; 263 int msgs_num; 264 int msg_write_idx; 265 u32 tx_buf_len; 266 u8 *tx_buf; 267 int msg_read_idx; 268 u32 rx_buf_len; 269 u8 *rx_buf; 270 int msg_err; 271 unsigned int status; 272 unsigned int abort_source; 273 unsigned int sw_mask; 274 int irq; 275 u32 flags; 276 struct i2c_adapter adapter; 277 u32 functionality; 278 u32 master_cfg; 279 u32 slave_cfg; 280 unsigned int tx_fifo_depth; 281 unsigned int rx_fifo_depth; 282 int rx_outstanding; 283 struct i2c_timings timings; 284 u32 sda_hold_time; 285 u16 ss_hcnt; 286 u16 ss_lcnt; 287 u16 fs_hcnt; 288 u16 fs_lcnt; 289 u16 fp_hcnt; 290 u16 fp_lcnt; 291 u16 hs_hcnt; 292 u16 hs_lcnt; 293 int (*acquire_lock)(void); 294 void (*release_lock)(void); 295 int semaphore_idx; 296 bool shared_with_punit; 297 int (*init)(struct dw_i2c_dev *dev); 298 int (*set_sda_hold_time)(struct dw_i2c_dev *dev); 299 int mode; 300 struct i2c_bus_recovery_info rinfo; 301 }; 302 303 #define ACCESS_INTR_MASK BIT(0) 304 #define ACCESS_NO_IRQ_SUSPEND BIT(1) 305 #define ARBITRATION_SEMAPHORE BIT(2) 306 #define ACCESS_POLLING BIT(3) 307 308 #define MODEL_MSCC_OCELOT BIT(8) 309 #define MODEL_BAIKAL_BT1 BIT(9) 310 #define MODEL_AMD_NAVI_GPU BIT(10) 311 #define MODEL_WANGXUN_SP BIT(11) 312 #define MODEL_MASK GENMASK(11, 8) 313 314 /* 315 * Enable UCSI interrupt by writing 0xd at register 316 * offset 0x474 specified in hardware specification. 317 */ 318 #define AMD_UCSI_INTR_REG 0x474 319 #define AMD_UCSI_INTR_EN 0xd 320 321 #define TXGBE_TX_FIFO_DEPTH 4 322 #define TXGBE_RX_FIFO_DEPTH 1 323 324 struct i2c_dw_semaphore_callbacks { 325 int (*probe)(struct dw_i2c_dev *dev); 326 void (*remove)(struct dw_i2c_dev *dev); 327 }; 328 329 int i2c_dw_init_regmap(struct dw_i2c_dev *dev); 330 u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 331 u32 tSYMBOL, u32 tf, int cond, int offset); 332 u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 333 u32 tLOW, u32 tf, int offset); 334 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev); 335 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev); 336 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare); 337 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev); 338 void i2c_dw_release_lock(struct dw_i2c_dev *dev); 339 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev); 340 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev); 341 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev); 342 u32 i2c_dw_func(struct i2c_adapter *adap); 343 344 extern const struct dev_pm_ops i2c_dw_dev_pm_ops; 345 346 static inline void __i2c_dw_enable(struct dw_i2c_dev *dev) 347 { 348 dev->status |= STATUS_ACTIVE; 349 regmap_write(dev->map, DW_IC_ENABLE, 1); 350 } 351 352 static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev) 353 { 354 regmap_write(dev->map, DW_IC_ENABLE, 0); 355 dev->status &= ~STATUS_ACTIVE; 356 } 357 358 static inline void __i2c_dw_write_intr_mask(struct dw_i2c_dev *dev, 359 unsigned int intr_mask) 360 { 361 unsigned int val = dev->flags & ACCESS_POLLING ? 0 : intr_mask; 362 363 regmap_write(dev->map, DW_IC_INTR_MASK, val); 364 dev->sw_mask = intr_mask; 365 } 366 367 static inline void __i2c_dw_read_intr_mask(struct dw_i2c_dev *dev, 368 unsigned int *intr_mask) 369 { 370 if (!(dev->flags & ACCESS_POLLING)) 371 regmap_read(dev->map, DW_IC_INTR_MASK, intr_mask); 372 else 373 *intr_mask = dev->sw_mask; 374 } 375 376 void __i2c_dw_disable(struct dw_i2c_dev *dev); 377 void i2c_dw_disable(struct dw_i2c_dev *dev); 378 379 extern void i2c_dw_configure_master(struct dw_i2c_dev *dev); 380 extern int i2c_dw_probe_master(struct dw_i2c_dev *dev); 381 382 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE) 383 extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); 384 extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); 385 #else 386 static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { } 387 static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; } 388 #endif 389 390 static inline void i2c_dw_configure(struct dw_i2c_dev *dev) 391 { 392 if (i2c_detect_slave_mode(dev->dev)) 393 i2c_dw_configure_slave(dev); 394 else 395 i2c_dw_configure_master(dev); 396 } 397 398 int i2c_dw_probe(struct dw_i2c_dev *dev); 399 400 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) 401 int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev); 402 #endif 403 404 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP) 405 int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev); 406 #endif 407 408 int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev); 409