1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Synopsys DesignWare I2C adapter driver. 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 12 #include <linux/bits.h> 13 #include <linux/completion.h> 14 #include <linux/errno.h> 15 #include <linux/i2c.h> 16 #include <linux/irqreturn.h> 17 #include <linux/pm.h> 18 #include <linux/regmap.h> 19 #include <linux/types.h> 20 21 #include <linux/designware_i2c.h> 22 23 #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ 24 I2C_FUNC_SMBUS_BYTE | \ 25 I2C_FUNC_SMBUS_BYTE_DATA | \ 26 I2C_FUNC_SMBUS_WORD_DATA | \ 27 I2C_FUNC_SMBUS_BLOCK_DATA | \ 28 I2C_FUNC_SMBUS_I2C_BLOCK) 29 30 /* 31 * Register access parameters 32 */ 33 #define DW_IC_REG_STEP_BYTES 2 34 #define DW_IC_REG_WORD_SHIFT 16 35 36 /* 37 * FIFO depth configuration 38 */ 39 #define DW_IC_FIFO_TX_FIELD GENMASK(23, 16) 40 #define DW_IC_FIFO_RX_FIELD GENMASK(15, 8) 41 #define DW_IC_FIFO_MIN_DEPTH 2 42 43 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A /* "111*" == v1.11* */ 44 #define DW_IC_COMP_TYPE_VALUE 0x44570140 /* "DW" + 0x0140 */ 45 46 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ 47 DW_IC_INTR_TX_ABRT | \ 48 DW_IC_INTR_STOP_DET) 49 #define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \ 50 DW_IC_INTR_TX_EMPTY) 51 #define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \ 52 DW_IC_INTR_RX_UNDER | \ 53 DW_IC_INTR_RD_REQ) 54 55 #define DW_IC_SDA_HOLD_RX_SHIFT 16 56 #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16) 57 58 #define DW_IC_ERR_TX_ABRT 0x1 59 60 #define DW_IC_TAR_10BITADDR_MASTER BIT(12) 61 62 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3)) 63 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2) 64 65 /* 66 * Sofware status flags 67 */ 68 #define STATUS_ACTIVE BIT(0) 69 #define STATUS_WRITE_IN_PROGRESS BIT(1) 70 #define STATUS_READ_IN_PROGRESS BIT(2) 71 #define STATUS_MASK GENMASK(2, 0) 72 73 /* 74 * operation modes 75 */ 76 #define DW_IC_MASTER 0 77 #define DW_IC_SLAVE 1 78 79 /* 80 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register. 81 * 82 * Only expected abort codes are listed here, 83 * refer to the datasheet for the full list. 84 */ 85 #define ABRT_7B_ADDR_NOACK 0 86 #define ABRT_10ADDR1_NOACK 1 87 #define ABRT_10ADDR2_NOACK 2 88 #define ABRT_TXDATA_NOACK 3 89 #define ABRT_GCALL_NOACK 4 90 #define ABRT_GCALL_READ 5 91 #define ABRT_SBYTE_ACKDET 7 92 #define ABRT_SBYTE_NORSTRT 9 93 #define ABRT_10B_RD_NORSTRT 10 94 #define ABRT_MASTER_DIS 11 95 #define ARB_LOST 12 96 #define ABRT_SLAVE_FLUSH_TXFIFO 13 97 #define ABRT_SLAVE_ARBLOST 14 98 #define ABRT_SLAVE_RD_INTX 15 99 100 #define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK) 101 #define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK) 102 #define DW_IC_TX_ABRT_10ADDR2_NOACK BIT(ABRT_10ADDR2_NOACK) 103 #define DW_IC_TX_ABRT_TXDATA_NOACK BIT(ABRT_TXDATA_NOACK) 104 #define DW_IC_TX_ABRT_GCALL_NOACK BIT(ABRT_GCALL_NOACK) 105 #define DW_IC_TX_ABRT_GCALL_READ BIT(ABRT_GCALL_READ) 106 #define DW_IC_TX_ABRT_SBYTE_ACKDET BIT(ABRT_SBYTE_ACKDET) 107 #define DW_IC_TX_ABRT_SBYTE_NORSTRT BIT(ABRT_SBYTE_NORSTRT) 108 #define DW_IC_TX_ABRT_10B_RD_NORSTRT BIT(ABRT_10B_RD_NORSTRT) 109 #define DW_IC_TX_ABRT_MASTER_DIS BIT(ABRT_MASTER_DIS) 110 #define DW_IC_TX_ARB_LOST BIT(ARB_LOST) 111 #define DW_IC_RX_ABRT_SLAVE_RD_INTX BIT(ABRT_SLAVE_RD_INTX) 112 #define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST) 113 #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO) 114 115 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ 116 DW_IC_TX_ABRT_10ADDR1_NOACK | \ 117 DW_IC_TX_ABRT_10ADDR2_NOACK | \ 118 DW_IC_TX_ABRT_TXDATA_NOACK | \ 119 DW_IC_TX_ABRT_GCALL_NOACK) 120 121 struct clk; 122 struct device; 123 struct reset_control; 124 125 /** 126 * struct dw_i2c_dev - private i2c-designware data 127 * @dev: driver model device node 128 * @map: IO registers map 129 * @sysmap: System controller registers map 130 * @base: IO registers pointer 131 * @ext: Extended IO registers pointer 132 * @cmd_complete: tx completion indicator 133 * @clk: input reference clock 134 * @pclk: clock required to access the registers 135 * @rst: optional reset for the controller 136 * @slave: represent an I2C slave device 137 * @get_clk_rate_khz: callback to retrieve IP specific bus speed 138 * @cmd_err: run time hardware error code 139 * @msgs: points to an array of messages currently being transferred 140 * @msgs_num: the number of elements in msgs 141 * @msg_write_idx: the element index of the current tx message in the msgs array 142 * @tx_buf_len: the length of the current tx buffer 143 * @tx_buf: the current tx buffer 144 * @msg_read_idx: the element index of the current rx message in the msgs array 145 * @rx_buf_len: the length of the current rx buffer 146 * @rx_buf: the current rx buffer 147 * @msg_err: error status of the current transfer 148 * @status: i2c master status, one of STATUS_* 149 * @abort_source: copy of the TX_ABRT_SOURCE register 150 * @sw_mask: SW mask of DW_IC_INTR_MASK used in polling mode 151 * @irq: interrupt number for the i2c master 152 * @flags: platform specific flags like type of IO accessors or model 153 * @adapter: i2c subsystem adapter node 154 * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support 155 * @master_cfg: configuration for the master device 156 * @slave_cfg: configuration for the slave device 157 * @tx_fifo_depth: depth of the hardware tx fifo 158 * @rx_fifo_depth: depth of the hardware rx fifo 159 * @rx_outstanding: current master-rx elements in tx fifo 160 * @timings: bus clock frequency, SDA hold and other timings 161 * @sda_hold_time: SDA hold value 162 * @ss_hcnt: standard speed HCNT value 163 * @ss_lcnt: standard speed LCNT value 164 * @fs_hcnt: fast speed HCNT value 165 * @fs_lcnt: fast speed LCNT value 166 * @fp_hcnt: fast plus HCNT value 167 * @fp_lcnt: fast plus LCNT value 168 * @hs_hcnt: high speed HCNT value 169 * @hs_lcnt: high speed LCNT value 170 * @acquire_lock: function to acquire a hardware lock on the bus 171 * @release_lock: function to release a hardware lock on the bus 172 * @semaphore_idx: Index of table with semaphore type attached to the bus. It's 173 * -1 if there is no semaphore. 174 * @shared_with_punit: true if this bus is shared with the SoC's PUNIT 175 * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing 176 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE 177 * @rinfo: I²C GPIO recovery information 178 * @bus_capacitance_pF: bus capacitance in picofarads 179 * @clk_freq_optimized: if this value is true, it means the hardware reduces 180 * its internal clock frequency by reducing the internal latency required 181 * to generate the high period and low period of SCL line. 182 * @emptyfifo_hold_master: true if the controller acting as master holds 183 * the clock when the Tx FIFO is empty instead of emitting a stop. 184 * 185 * HCNT and LCNT parameters can be used if the platform knows more accurate 186 * values than the one computed based only on the input clock frequency. 187 * Leave them to be %0 if not used. 188 */ 189 struct dw_i2c_dev { 190 struct device *dev; 191 struct regmap *map; 192 struct regmap *sysmap; 193 void __iomem *base; 194 void __iomem *ext; 195 struct completion cmd_complete; 196 struct clk *clk; 197 struct clk *pclk; 198 struct reset_control *rst; 199 struct i2c_client *slave; 200 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev); 201 int cmd_err; 202 struct i2c_msg *msgs; 203 int msgs_num; 204 int msg_write_idx; 205 u32 tx_buf_len; 206 u8 *tx_buf; 207 int msg_read_idx; 208 u32 rx_buf_len; 209 u8 *rx_buf; 210 int msg_err; 211 unsigned int status; 212 unsigned int abort_source; 213 unsigned int sw_mask; 214 int irq; 215 u32 flags; 216 struct i2c_adapter adapter; 217 u32 functionality; 218 u32 master_cfg; 219 u32 slave_cfg; 220 unsigned int tx_fifo_depth; 221 unsigned int rx_fifo_depth; 222 int rx_outstanding; 223 struct i2c_timings timings; 224 u32 sda_hold_time; 225 u16 ss_hcnt; 226 u16 ss_lcnt; 227 u16 fs_hcnt; 228 u16 fs_lcnt; 229 u16 fp_hcnt; 230 u16 fp_lcnt; 231 u16 hs_hcnt; 232 u16 hs_lcnt; 233 int (*acquire_lock)(void); 234 void (*release_lock)(void); 235 int semaphore_idx; 236 bool shared_with_punit; 237 int (*set_sda_hold_time)(struct dw_i2c_dev *dev); 238 int mode; 239 struct i2c_bus_recovery_info rinfo; 240 u32 bus_capacitance_pF; 241 bool clk_freq_optimized; 242 bool emptyfifo_hold_master; 243 }; 244 245 #define ACCESS_INTR_MASK BIT(0) 246 #define ACCESS_NO_IRQ_SUSPEND BIT(1) 247 #define ARBITRATION_SEMAPHORE BIT(2) 248 #define ACCESS_POLLING BIT(3) 249 250 #define MODEL_AMD_NAVI_GPU BIT(10) 251 #define MODEL_WANGXUN_SP BIT(11) 252 #define MODEL_MASK GENMASK(11, 8) 253 254 /* 255 * Enable UCSI interrupt by writing 0xd at register 256 * offset 0x474 specified in hardware specification. 257 */ 258 #define AMD_UCSI_INTR_REG 0x474 259 #define AMD_UCSI_INTR_EN 0xd 260 261 #define TXGBE_TX_FIFO_DEPTH 4 262 #define TXGBE_RX_FIFO_DEPTH 1 263 264 struct i2c_dw_semaphore_callbacks { 265 int (*probe)(struct dw_i2c_dev *dev); 266 }; 267 268 u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 269 u32 tSYMBOL, u32 tf, int offset); 270 u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 271 u32 tLOW, u32 tf, int offset); 272 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev); 273 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare); 274 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev); 275 void i2c_dw_release_lock(struct dw_i2c_dev *dev); 276 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev); 277 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev); 278 u32 i2c_dw_func(struct i2c_adapter *adap); 279 irqreturn_t i2c_dw_isr_master(struct dw_i2c_dev *dev); 280 281 extern const struct dev_pm_ops i2c_dw_dev_pm_ops; 282 283 static inline void __i2c_dw_enable(struct dw_i2c_dev *dev) 284 { 285 dev->status |= STATUS_ACTIVE; 286 regmap_write(dev->map, DW_IC_ENABLE, 1); 287 } 288 289 static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev) 290 { 291 regmap_write(dev->map, DW_IC_ENABLE, 0); 292 dev->status &= ~STATUS_ACTIVE; 293 } 294 295 static inline void __i2c_dw_write_intr_mask(struct dw_i2c_dev *dev, 296 unsigned int intr_mask) 297 { 298 unsigned int val = dev->flags & ACCESS_POLLING ? 0 : intr_mask; 299 300 regmap_write(dev->map, DW_IC_INTR_MASK, val); 301 dev->sw_mask = intr_mask; 302 } 303 304 static inline void __i2c_dw_read_intr_mask(struct dw_i2c_dev *dev, 305 unsigned int *intr_mask) 306 { 307 if (!(dev->flags & ACCESS_POLLING)) 308 regmap_read(dev->map, DW_IC_INTR_MASK, intr_mask); 309 else 310 *intr_mask = dev->sw_mask; 311 } 312 313 void __i2c_dw_disable(struct dw_i2c_dev *dev); 314 void i2c_dw_disable(struct dw_i2c_dev *dev); 315 316 extern void i2c_dw_configure_master(struct dw_i2c_dev *dev); 317 extern int i2c_dw_probe_master(struct dw_i2c_dev *dev); 318 319 int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); 320 321 #if IS_ENABLED(CONFIG_I2C_SLAVE) 322 extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); 323 irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev); 324 int i2c_dw_reg_slave(struct i2c_client *client); 325 int i2c_dw_unreg_slave(struct i2c_client *client); 326 #else 327 static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { } 328 static inline irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) { return IRQ_NONE; } 329 #endif 330 331 static inline void i2c_dw_configure(struct dw_i2c_dev *dev) 332 { 333 i2c_dw_configure_slave(dev); 334 i2c_dw_configure_master(dev); 335 } 336 337 int i2c_dw_probe(struct dw_i2c_dev *dev); 338 int i2c_dw_init(struct dw_i2c_dev *dev); 339 void i2c_dw_shutdown(struct dw_i2c_dev *dev); 340 void i2c_dw_set_mode(struct dw_i2c_dev *dev, int mode); 341 342 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) 343 int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev); 344 #endif 345 346 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP) 347 int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev); 348 #endif 349 350 int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev); 351