1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Synopsys DesignWare I2C adapter driver. 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 #include <linux/acpi.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/errno.h> 17 #include <linux/export.h> 18 #include <linux/i2c.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/pm.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/property.h> 27 #include <linux/regmap.h> 28 #include <linux/swab.h> 29 #include <linux/types.h> 30 #include <linux/units.h> 31 32 #define DEFAULT_SYMBOL_NAMESPACE I2C_DW_COMMON 33 34 #include "i2c-designware-core.h" 35 36 static const char *const abort_sources[] = { 37 [ABRT_7B_ADDR_NOACK] = 38 "slave address not acknowledged (7bit mode)", 39 [ABRT_10ADDR1_NOACK] = 40 "first address byte not acknowledged (10bit mode)", 41 [ABRT_10ADDR2_NOACK] = 42 "second address byte not acknowledged (10bit mode)", 43 [ABRT_TXDATA_NOACK] = 44 "data not acknowledged", 45 [ABRT_GCALL_NOACK] = 46 "no acknowledgement for a general call", 47 [ABRT_GCALL_READ] = 48 "read after general call", 49 [ABRT_SBYTE_ACKDET] = 50 "start byte acknowledged", 51 [ABRT_SBYTE_NORSTRT] = 52 "trying to send start byte when restart is disabled", 53 [ABRT_10B_RD_NORSTRT] = 54 "trying to read when restart is disabled (10bit mode)", 55 [ABRT_MASTER_DIS] = 56 "trying to use disabled adapter", 57 [ARB_LOST] = 58 "lost arbitration", 59 [ABRT_SLAVE_FLUSH_TXFIFO] = 60 "read command so flush old data in the TX FIFO", 61 [ABRT_SLAVE_ARBLOST] = 62 "slave lost the bus while transmitting data to a remote master", 63 [ABRT_SLAVE_RD_INTX] = 64 "incorrect slave-transmitter mode configuration", 65 }; 66 67 static int dw_reg_read(void *context, unsigned int reg, unsigned int *val) 68 { 69 struct dw_i2c_dev *dev = context; 70 71 *val = readl(dev->base + reg); 72 73 return 0; 74 } 75 76 static int dw_reg_write(void *context, unsigned int reg, unsigned int val) 77 { 78 struct dw_i2c_dev *dev = context; 79 80 writel(val, dev->base + reg); 81 82 return 0; 83 } 84 85 static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val) 86 { 87 struct dw_i2c_dev *dev = context; 88 89 *val = swab32(readl(dev->base + reg)); 90 91 return 0; 92 } 93 94 static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val) 95 { 96 struct dw_i2c_dev *dev = context; 97 98 writel(swab32(val), dev->base + reg); 99 100 return 0; 101 } 102 103 static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val) 104 { 105 struct dw_i2c_dev *dev = context; 106 107 *val = readw(dev->base + reg) | 108 (readw(dev->base + reg + 2) << 16); 109 110 return 0; 111 } 112 113 static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val) 114 { 115 struct dw_i2c_dev *dev = context; 116 117 writew(val, dev->base + reg); 118 writew(val >> 16, dev->base + reg + 2); 119 120 return 0; 121 } 122 123 /** 124 * i2c_dw_init_regmap() - Initialize registers map 125 * @dev: device private data 126 * 127 * Autodetects needed register access mode and creates the regmap with 128 * corresponding read/write callbacks. This must be called before doing any 129 * other register access. 130 * 131 * Return: 0 on success, or negative errno otherwise. 132 */ 133 int i2c_dw_init_regmap(struct dw_i2c_dev *dev) 134 { 135 struct regmap_config map_cfg = { 136 .reg_bits = 32, 137 .val_bits = 32, 138 .reg_stride = 4, 139 .disable_locking = true, 140 .reg_read = dw_reg_read, 141 .reg_write = dw_reg_write, 142 .max_register = DW_IC_COMP_TYPE, 143 }; 144 u32 reg; 145 int ret; 146 147 /* 148 * Skip detecting the registers map configuration if the regmap has 149 * already been provided by a higher code. 150 */ 151 if (dev->map) 152 return 0; 153 154 ret = i2c_dw_acquire_lock(dev); 155 if (ret) 156 return ret; 157 158 reg = readl(dev->base + DW_IC_COMP_TYPE); 159 i2c_dw_release_lock(dev); 160 161 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) 162 map_cfg.max_register = AMD_UCSI_INTR_REG; 163 164 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) { 165 map_cfg.reg_read = dw_reg_read_swab; 166 map_cfg.reg_write = dw_reg_write_swab; 167 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { 168 map_cfg.reg_read = dw_reg_read_word; 169 map_cfg.reg_write = dw_reg_write_word; 170 } else if (reg != DW_IC_COMP_TYPE_VALUE) { 171 dev_err(dev->dev, 172 "Unknown Synopsys component type: 0x%08x\n", reg); 173 return -ENODEV; 174 } 175 176 /* 177 * Note we'll check the return value of the regmap IO accessors only 178 * at the probe stage. The rest of the code won't do this because 179 * basically we have MMIO-based regmap, so none of the read/write methods 180 * can fail. 181 */ 182 dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg); 183 if (IS_ERR(dev->map)) { 184 dev_err(dev->dev, "Failed to init the registers map\n"); 185 return PTR_ERR(dev->map); 186 } 187 188 return 0; 189 } 190 191 static const u32 supported_speeds[] = { 192 I2C_MAX_HIGH_SPEED_MODE_FREQ, 193 I2C_MAX_FAST_MODE_PLUS_FREQ, 194 I2C_MAX_FAST_MODE_FREQ, 195 I2C_MAX_STANDARD_MODE_FREQ, 196 }; 197 198 static int i2c_dw_validate_speed(struct dw_i2c_dev *dev) 199 { 200 struct i2c_timings *t = &dev->timings; 201 unsigned int i; 202 203 /* 204 * Only standard mode at 100kHz, fast mode at 400kHz, 205 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported. 206 */ 207 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) { 208 if (t->bus_freq_hz == supported_speeds[i]) 209 return 0; 210 } 211 212 dev_err(dev->dev, 213 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n", 214 t->bus_freq_hz); 215 216 return -EINVAL; 217 } 218 219 #ifdef CONFIG_OF 220 221 #include <linux/platform_device.h> 222 223 #define MSCC_ICPU_CFG_TWI_DELAY 0x0 224 #define MSCC_ICPU_CFG_TWI_DELAY_ENABLE BIT(0) 225 #define MSCC_ICPU_CFG_TWI_SPIKE_FILTER 0x4 226 227 static int mscc_twi_set_sda_hold_time(struct dw_i2c_dev *dev) 228 { 229 writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE, 230 dev->ext + MSCC_ICPU_CFG_TWI_DELAY); 231 232 return 0; 233 } 234 235 static void i2c_dw_of_configure(struct device *device) 236 { 237 struct platform_device *pdev = to_platform_device(device); 238 struct dw_i2c_dev *dev = dev_get_drvdata(device); 239 240 switch (dev->flags & MODEL_MASK) { 241 case MODEL_MSCC_OCELOT: 242 dev->ext = devm_platform_ioremap_resource(pdev, 1); 243 if (!IS_ERR(dev->ext)) 244 dev->set_sda_hold_time = mscc_twi_set_sda_hold_time; 245 break; 246 default: 247 break; 248 } 249 } 250 251 #else /* CONFIG_OF */ 252 253 static inline void i2c_dw_of_configure(struct device *device) { } 254 255 #endif /* CONFIG_OF */ 256 257 #ifdef CONFIG_ACPI 258 259 #include <linux/dmi.h> 260 261 /* 262 * The HCNT/LCNT information coming from ACPI should be the most accurate 263 * for given platform. However, some systems get it wrong. On such systems 264 * we get better results by calculating those based on the input clock. 265 */ 266 static const struct dmi_system_id i2c_dw_no_acpi_params[] = { 267 { 268 .ident = "Dell Inspiron 7348", 269 .matches = { 270 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 271 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"), 272 }, 273 }, 274 {} 275 }; 276 277 static void i2c_dw_acpi_params(struct device *device, char method[], 278 u16 *hcnt, u16 *lcnt, u32 *sda_hold) 279 { 280 struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER }; 281 acpi_handle handle = ACPI_HANDLE(device); 282 union acpi_object *obj; 283 284 if (dmi_check_system(i2c_dw_no_acpi_params)) 285 return; 286 287 if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf))) 288 return; 289 290 obj = (union acpi_object *)buf.pointer; 291 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) { 292 const union acpi_object *objs = obj->package.elements; 293 294 *hcnt = (u16)objs[0].integer.value; 295 *lcnt = (u16)objs[1].integer.value; 296 *sda_hold = (u32)objs[2].integer.value; 297 } 298 299 kfree(buf.pointer); 300 } 301 302 static void i2c_dw_acpi_configure(struct device *device) 303 { 304 struct dw_i2c_dev *dev = dev_get_drvdata(device); 305 struct i2c_timings *t = &dev->timings; 306 u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0; 307 308 /* 309 * Try to get SDA hold time and *CNT values from an ACPI method for 310 * selected speed modes. 311 */ 312 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht); 313 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht); 314 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht); 315 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht); 316 317 switch (t->bus_freq_hz) { 318 case I2C_MAX_STANDARD_MODE_FREQ: 319 dev->sda_hold_time = ss_ht; 320 break; 321 case I2C_MAX_FAST_MODE_PLUS_FREQ: 322 dev->sda_hold_time = fp_ht; 323 break; 324 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 325 dev->sda_hold_time = hs_ht; 326 break; 327 case I2C_MAX_FAST_MODE_FREQ: 328 default: 329 dev->sda_hold_time = fs_ht; 330 break; 331 } 332 } 333 334 static u32 i2c_dw_acpi_round_bus_speed(struct device *device) 335 { 336 u32 acpi_speed; 337 int i; 338 339 acpi_speed = i2c_acpi_find_bus_speed(device); 340 /* 341 * Some DSDTs use a non standard speed, round down to the lowest 342 * standard speed. 343 */ 344 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) { 345 if (acpi_speed >= supported_speeds[i]) 346 return supported_speeds[i]; 347 } 348 349 return 0; 350 } 351 352 #else /* CONFIG_ACPI */ 353 354 static inline void i2c_dw_acpi_configure(struct device *device) { } 355 356 static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; } 357 358 #endif /* CONFIG_ACPI */ 359 360 static void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev) 361 { 362 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev); 363 struct i2c_timings *t = &dev->timings; 364 365 /* 366 * Find bus speed from the "clock-frequency" device property, ACPI 367 * or by using fast mode if neither is set. 368 */ 369 if (acpi_speed && t->bus_freq_hz) 370 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed); 371 else if (acpi_speed || t->bus_freq_hz) 372 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed); 373 else 374 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; 375 } 376 377 int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev) 378 { 379 struct i2c_timings *t = &dev->timings; 380 struct device *device = dev->dev; 381 struct fwnode_handle *fwnode = dev_fwnode(device); 382 383 i2c_parse_fw_timings(device, t, false); 384 385 i2c_dw_adjust_bus_speed(dev); 386 387 if (is_of_node(fwnode)) 388 i2c_dw_of_configure(device); 389 else if (is_acpi_node(fwnode)) 390 i2c_dw_acpi_configure(device); 391 392 return i2c_dw_validate_speed(dev); 393 } 394 EXPORT_SYMBOL_GPL(i2c_dw_fw_parse_and_configure); 395 396 static u32 i2c_dw_read_scl_reg(struct dw_i2c_dev *dev, u32 reg) 397 { 398 u32 val; 399 int ret; 400 401 ret = i2c_dw_acquire_lock(dev); 402 if (ret) 403 return 0; 404 405 ret = regmap_read(dev->map, reg, &val); 406 i2c_dw_release_lock(dev); 407 408 return ret ? 0 : val; 409 } 410 411 u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 412 u32 tSYMBOL, u32 tf, int offset) 413 { 414 if (!ic_clk) 415 return i2c_dw_read_scl_reg(dev, reg); 416 417 /* 418 * Conditional expression: 419 * 420 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) 421 * 422 * This is just experimental rule; the tHD;STA period turned 423 * out to be proportinal to (_HCNT + 3). With this setting, 424 * we could meet both tHIGH and tHD;STA timing specs. 425 * 426 * If unsure, you'd better to take this alternative. 427 * 428 * The reason why we need to take into account "tf" here, 429 * is the same as described in i2c_dw_scl_lcnt(). 430 */ 431 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) - 3 + offset; 432 } 433 434 u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 435 u32 tLOW, u32 tf, int offset) 436 { 437 if (!ic_clk) 438 return i2c_dw_read_scl_reg(dev, reg); 439 440 /* 441 * Conditional expression: 442 * 443 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) 444 * 445 * DW I2C core starts counting the SCL CNTs for the LOW period 446 * of the SCL clock (tLOW) as soon as it pulls the SCL line. 447 * In order to meet the tLOW timing spec, we need to take into 448 * account the fall time of SCL signal (tf). Default tf value 449 * should be 0.3 us, for safety. 450 */ 451 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - 1 + offset; 452 } 453 454 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) 455 { 456 unsigned int reg; 457 int ret; 458 459 ret = i2c_dw_acquire_lock(dev); 460 if (ret) 461 return ret; 462 463 /* Configure SDA Hold Time if required */ 464 ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®); 465 if (ret) 466 goto err_release_lock; 467 468 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { 469 if (!dev->sda_hold_time) { 470 /* Keep previous hold time setting if no one set it */ 471 ret = regmap_read(dev->map, DW_IC_SDA_HOLD, 472 &dev->sda_hold_time); 473 if (ret) 474 goto err_release_lock; 475 } 476 477 /* 478 * Workaround for avoiding TX arbitration lost in case I2C 479 * slave pulls SDA down "too quickly" after falling edge of 480 * SCL by enabling non-zero SDA RX hold. Specification says it 481 * extends incoming SDA low to high transition while SCL is 482 * high but it appears to help also above issue. 483 */ 484 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) 485 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; 486 487 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n", 488 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK, 489 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT); 490 } else if (dev->set_sda_hold_time) { 491 dev->set_sda_hold_time(dev); 492 } else if (dev->sda_hold_time) { 493 dev_warn(dev->dev, 494 "Hardware too old to adjust SDA hold time.\n"); 495 dev->sda_hold_time = 0; 496 } 497 498 err_release_lock: 499 i2c_dw_release_lock(dev); 500 501 return ret; 502 } 503 504 void __i2c_dw_disable(struct dw_i2c_dev *dev) 505 { 506 struct i2c_timings *t = &dev->timings; 507 unsigned int raw_intr_stats, ic_stats; 508 unsigned int enable; 509 int timeout = 100; 510 bool abort_needed; 511 unsigned int status; 512 int ret; 513 514 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_intr_stats); 515 regmap_read(dev->map, DW_IC_STATUS, &ic_stats); 516 regmap_read(dev->map, DW_IC_ENABLE, &enable); 517 518 abort_needed = (raw_intr_stats & DW_IC_INTR_MST_ON_HOLD) || 519 (ic_stats & DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY); 520 if (abort_needed) { 521 if (!(enable & DW_IC_ENABLE_ENABLE)) { 522 regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE); 523 /* 524 * Wait 10 times the signaling period of the highest I2C 525 * transfer supported by the driver (for 400KHz this is 526 * 25us) to ensure the I2C ENABLE bit is already set 527 * as described in the DesignWare I2C databook. 528 */ 529 fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz)); 530 /* Set ENABLE bit before setting ABORT */ 531 enable |= DW_IC_ENABLE_ENABLE; 532 } 533 534 regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT); 535 ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable, 536 !(enable & DW_IC_ENABLE_ABORT), 10, 537 100); 538 if (ret) 539 dev_err(dev->dev, "timeout while trying to abort current transfer\n"); 540 } 541 542 do { 543 __i2c_dw_disable_nowait(dev); 544 /* 545 * The enable status register may be unimplemented, but 546 * in that case this test reads zero and exits the loop. 547 */ 548 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status); 549 if ((status & 1) == 0) 550 return; 551 552 /* 553 * Wait 10 times the signaling period of the highest I2C 554 * transfer supported by the driver (for 400kHz this is 555 * 25us) as described in the DesignWare I2C databook. 556 */ 557 usleep_range(25, 250); 558 } while (timeout--); 559 560 dev_warn(dev->dev, "timeout in disabling adapter\n"); 561 } 562 563 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev) 564 { 565 /* 566 * Clock is not necessary if we got LCNT/HCNT values directly from 567 * the platform code. 568 */ 569 if (WARN_ON_ONCE(!dev->get_clk_rate_khz)) 570 return 0; 571 return dev->get_clk_rate_khz(dev); 572 } 573 574 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare) 575 { 576 int ret; 577 578 if (prepare) { 579 /* Optional interface clock */ 580 ret = clk_prepare_enable(dev->pclk); 581 if (ret) 582 return ret; 583 584 ret = clk_prepare_enable(dev->clk); 585 if (ret) 586 clk_disable_unprepare(dev->pclk); 587 588 return ret; 589 } 590 591 clk_disable_unprepare(dev->clk); 592 clk_disable_unprepare(dev->pclk); 593 594 return 0; 595 } 596 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk); 597 598 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev) 599 { 600 int ret; 601 602 if (!dev->acquire_lock) 603 return 0; 604 605 ret = dev->acquire_lock(); 606 if (!ret) 607 return 0; 608 609 dev_err(dev->dev, "couldn't acquire bus ownership\n"); 610 611 return ret; 612 } 613 614 void i2c_dw_release_lock(struct dw_i2c_dev *dev) 615 { 616 if (dev->release_lock) 617 dev->release_lock(); 618 } 619 620 /* 621 * Waiting for bus not busy 622 */ 623 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) 624 { 625 unsigned int status; 626 int ret; 627 628 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, 629 !(status & DW_IC_STATUS_ACTIVITY), 630 1100, 20000); 631 if (ret) { 632 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 633 634 i2c_recover_bus(&dev->adapter); 635 636 regmap_read(dev->map, DW_IC_STATUS, &status); 637 if (!(status & DW_IC_STATUS_ACTIVITY)) 638 ret = 0; 639 } 640 641 return ret; 642 } 643 644 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) 645 { 646 unsigned long abort_source = dev->abort_source; 647 int i; 648 649 if (abort_source & DW_IC_TX_ABRT_NOACK) { 650 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 651 dev_dbg(dev->dev, 652 "%s: %s\n", __func__, abort_sources[i]); 653 return -EREMOTEIO; 654 } 655 656 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 657 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); 658 659 if (abort_source & DW_IC_TX_ARB_LOST) 660 return -EAGAIN; 661 if (abort_source & DW_IC_TX_ABRT_GCALL_READ) 662 return -EINVAL; /* wrong msgs[] data */ 663 664 return -EIO; 665 } 666 667 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) 668 { 669 u32 tx_fifo_depth, rx_fifo_depth; 670 unsigned int param; 671 int ret; 672 673 /* DW_IC_COMP_PARAM_1 not implement for IP issue */ 674 if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) { 675 dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH; 676 dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH; 677 678 return 0; 679 } 680 681 /* 682 * Try to detect the FIFO depth if not set by interface driver, 683 * the depth could be from 2 to 256 from HW spec. 684 */ 685 ret = i2c_dw_acquire_lock(dev); 686 if (ret) 687 return ret; 688 689 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m); 690 i2c_dw_release_lock(dev); 691 if (ret) 692 return ret; 693 694 tx_fifo_depth = ((param >> 16) & 0xff) + 1; 695 rx_fifo_depth = ((param >> 8) & 0xff) + 1; 696 if (!dev->tx_fifo_depth) { 697 dev->tx_fifo_depth = tx_fifo_depth; 698 dev->rx_fifo_depth = rx_fifo_depth; 699 } else if (tx_fifo_depth >= 2) { 700 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth, 701 tx_fifo_depth); 702 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth, 703 rx_fifo_depth); 704 } 705 706 return 0; 707 } 708 709 u32 i2c_dw_func(struct i2c_adapter *adap) 710 { 711 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 712 713 return dev->functionality; 714 } 715 716 void i2c_dw_disable(struct dw_i2c_dev *dev) 717 { 718 unsigned int dummy; 719 int ret; 720 721 ret = i2c_dw_acquire_lock(dev); 722 if (ret) 723 return; 724 725 /* Disable controller */ 726 __i2c_dw_disable(dev); 727 728 /* Disable all interrupts */ 729 __i2c_dw_write_intr_mask(dev, 0); 730 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); 731 732 i2c_dw_release_lock(dev); 733 } 734 EXPORT_SYMBOL_GPL(i2c_dw_disable); 735 736 int i2c_dw_probe(struct dw_i2c_dev *dev) 737 { 738 device_set_node(&dev->adapter.dev, dev_fwnode(dev->dev)); 739 740 switch (dev->mode) { 741 case DW_IC_SLAVE: 742 return i2c_dw_probe_slave(dev); 743 case DW_IC_MASTER: 744 return i2c_dw_probe_master(dev); 745 default: 746 dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode); 747 return -EINVAL; 748 } 749 } 750 EXPORT_SYMBOL_GPL(i2c_dw_probe); 751 752 static int i2c_dw_prepare(struct device *device) 753 { 754 /* 755 * If the ACPI companion device object is present for this device, 756 * it may be accessed during suspend and resume of other devices via 757 * I2C operation regions, so tell the PM core and middle layers to 758 * avoid skipping system suspend/resume callbacks for it in that case. 759 */ 760 return !has_acpi_companion(device); 761 } 762 763 static int i2c_dw_runtime_suspend(struct device *device) 764 { 765 struct dw_i2c_dev *dev = dev_get_drvdata(device); 766 767 if (dev->shared_with_punit) 768 return 0; 769 770 i2c_dw_disable(dev); 771 i2c_dw_prepare_clk(dev, false); 772 773 return 0; 774 } 775 776 static int i2c_dw_suspend(struct device *device) 777 { 778 struct dw_i2c_dev *dev = dev_get_drvdata(device); 779 780 i2c_mark_adapter_suspended(&dev->adapter); 781 782 return i2c_dw_runtime_suspend(device); 783 } 784 785 static int i2c_dw_runtime_resume(struct device *device) 786 { 787 struct dw_i2c_dev *dev = dev_get_drvdata(device); 788 789 if (!dev->shared_with_punit) 790 i2c_dw_prepare_clk(dev, true); 791 792 dev->init(dev); 793 794 return 0; 795 } 796 797 static int i2c_dw_resume(struct device *device) 798 { 799 struct dw_i2c_dev *dev = dev_get_drvdata(device); 800 801 i2c_dw_runtime_resume(device); 802 i2c_mark_adapter_resumed(&dev->adapter); 803 804 return 0; 805 } 806 807 EXPORT_GPL_DEV_PM_OPS(i2c_dw_dev_pm_ops) = { 808 .prepare = pm_sleep_ptr(i2c_dw_prepare), 809 LATE_SYSTEM_SLEEP_PM_OPS(i2c_dw_suspend, i2c_dw_resume) 810 RUNTIME_PM_OPS(i2c_dw_runtime_suspend, i2c_dw_runtime_resume, NULL) 811 }; 812 813 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); 814 MODULE_LICENSE("GPL"); 815