1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Synopsys DesignWare I2C adapter driver. 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 12 #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW_COMMON" 13 14 #include <linux/acpi.h> 15 #include <linux/bitfield.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/err.h> 20 #include <linux/errno.h> 21 #include <linux/export.h> 22 #include <linux/i2c.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/pm.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/property.h> 31 #include <linux/regmap.h> 32 #include <linux/swab.h> 33 #include <linux/types.h> 34 #include <linux/units.h> 35 36 #include "i2c-designware-core.h" 37 38 #define DW_IC_DEFAULT_BUS_CAPACITANCE_pF 100 39 #define DW_IC_ABORT_TIMEOUT_US 10 40 #define DW_IC_BUSY_POLL_TIMEOUT_US (1 * USEC_PER_MSEC) 41 42 static const char *const abort_sources[] = { 43 [ABRT_7B_ADDR_NOACK] = 44 "slave address not acknowledged (7bit mode)", 45 [ABRT_10ADDR1_NOACK] = 46 "first address byte not acknowledged (10bit mode)", 47 [ABRT_10ADDR2_NOACK] = 48 "second address byte not acknowledged (10bit mode)", 49 [ABRT_TXDATA_NOACK] = 50 "data not acknowledged", 51 [ABRT_GCALL_NOACK] = 52 "no acknowledgement for a general call", 53 [ABRT_GCALL_READ] = 54 "read after general call", 55 [ABRT_SBYTE_ACKDET] = 56 "start byte acknowledged", 57 [ABRT_SBYTE_NORSTRT] = 58 "trying to send start byte when restart is disabled", 59 [ABRT_10B_RD_NORSTRT] = 60 "trying to read when restart is disabled (10bit mode)", 61 [ABRT_MASTER_DIS] = 62 "trying to use disabled adapter", 63 [ARB_LOST] = 64 "lost arbitration", 65 [ABRT_SLAVE_FLUSH_TXFIFO] = 66 "read command so flush old data in the TX FIFO", 67 [ABRT_SLAVE_ARBLOST] = 68 "slave lost the bus while transmitting data to a remote master", 69 [ABRT_SLAVE_RD_INTX] = 70 "incorrect slave-transmitter mode configuration", 71 }; 72 73 static int dw_reg_read(void *context, unsigned int reg, unsigned int *val) 74 { 75 struct dw_i2c_dev *dev = context; 76 77 *val = readl(dev->base + reg); 78 79 return 0; 80 } 81 82 static int dw_reg_write(void *context, unsigned int reg, unsigned int val) 83 { 84 struct dw_i2c_dev *dev = context; 85 86 writel(val, dev->base + reg); 87 88 return 0; 89 } 90 91 static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val) 92 { 93 struct dw_i2c_dev *dev = context; 94 95 *val = swab32(readl(dev->base + reg)); 96 97 return 0; 98 } 99 100 static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val) 101 { 102 struct dw_i2c_dev *dev = context; 103 104 writel(swab32(val), dev->base + reg); 105 106 return 0; 107 } 108 109 static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val) 110 { 111 struct dw_i2c_dev *dev = context; 112 113 *val = readw(dev->base + reg) | 114 (readw(dev->base + reg + DW_IC_REG_STEP_BYTES) << DW_IC_REG_WORD_SHIFT); 115 116 return 0; 117 } 118 119 static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val) 120 { 121 struct dw_i2c_dev *dev = context; 122 123 writew(val, dev->base + reg); 124 writew(val >> DW_IC_REG_WORD_SHIFT, dev->base + reg + DW_IC_REG_STEP_BYTES); 125 126 return 0; 127 } 128 129 /** 130 * i2c_dw_init_regmap() - Initialize registers map 131 * @dev: device private data 132 * 133 * Autodetects needed register access mode and creates the regmap with 134 * corresponding read/write callbacks. This must be called before doing any 135 * other register access. 136 * 137 * Return: 0 on success, or negative errno otherwise. 138 */ 139 static int i2c_dw_init_regmap(struct dw_i2c_dev *dev) 140 { 141 struct regmap_config map_cfg = { 142 .reg_bits = 32, 143 .val_bits = 32, 144 .reg_stride = 4, 145 .disable_locking = true, 146 .reg_read = dw_reg_read, 147 .reg_write = dw_reg_write, 148 .max_register = DW_IC_COMP_TYPE, 149 }; 150 u32 reg; 151 int ret; 152 153 /* 154 * Skip detecting the registers map configuration if the regmap has 155 * already been provided by a higher code. 156 */ 157 if (dev->map) 158 return 0; 159 160 ret = i2c_dw_acquire_lock(dev); 161 if (ret) 162 return ret; 163 164 reg = readl(dev->base + DW_IC_COMP_TYPE); 165 i2c_dw_release_lock(dev); 166 167 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) 168 map_cfg.max_register = AMD_UCSI_INTR_REG; 169 170 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) { 171 map_cfg.reg_read = dw_reg_read_swab; 172 map_cfg.reg_write = dw_reg_write_swab; 173 } else if (reg == lower_16_bits(DW_IC_COMP_TYPE_VALUE)) { 174 map_cfg.reg_read = dw_reg_read_word; 175 map_cfg.reg_write = dw_reg_write_word; 176 } else if (reg != DW_IC_COMP_TYPE_VALUE) { 177 dev_err(dev->dev, 178 "Unknown Synopsys component type: 0x%08x\n", reg); 179 return -ENODEV; 180 } 181 182 /* 183 * Note we'll check the return value of the regmap IO accessors only 184 * at the probe stage. The rest of the code won't do this because 185 * basically we have MMIO-based regmap, so none of the read/write methods 186 * can fail. 187 */ 188 dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg); 189 if (IS_ERR(dev->map)) { 190 dev_err(dev->dev, "Failed to init the registers map\n"); 191 return PTR_ERR(dev->map); 192 } 193 194 return 0; 195 } 196 197 static const u32 supported_speeds[] = { 198 I2C_MAX_HIGH_SPEED_MODE_FREQ, 199 I2C_MAX_FAST_MODE_PLUS_FREQ, 200 I2C_MAX_FAST_MODE_FREQ, 201 I2C_MAX_STANDARD_MODE_FREQ, 202 }; 203 204 static int i2c_dw_validate_speed(struct dw_i2c_dev *dev) 205 { 206 struct i2c_timings *t = &dev->timings; 207 unsigned int i; 208 209 /* 210 * Only standard mode at 100kHz, fast mode at 400kHz, 211 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported. 212 */ 213 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) { 214 if (t->bus_freq_hz == supported_speeds[i]) 215 return 0; 216 } 217 218 dev_err(dev->dev, 219 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n", 220 t->bus_freq_hz); 221 222 return -EINVAL; 223 } 224 225 #ifdef CONFIG_OF 226 227 #include <linux/platform_device.h> 228 229 #define MSCC_ICPU_CFG_TWI_DELAY 0x0 230 #define MSCC_ICPU_CFG_TWI_DELAY_ENABLE BIT(0) 231 #define MSCC_ICPU_CFG_TWI_SPIKE_FILTER 0x4 232 233 static int mscc_twi_set_sda_hold_time(struct dw_i2c_dev *dev) 234 { 235 writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE, 236 dev->ext + MSCC_ICPU_CFG_TWI_DELAY); 237 238 return 0; 239 } 240 241 static void i2c_dw_of_configure(struct device *device) 242 { 243 struct platform_device *pdev = to_platform_device(device); 244 struct dw_i2c_dev *dev = dev_get_drvdata(device); 245 246 if (device_is_compatible(dev->dev, "mscc,ocelot-i2c")) { 247 dev->ext = devm_platform_ioremap_resource(pdev, 1); 248 if (!IS_ERR(dev->ext)) 249 dev->set_sda_hold_time = mscc_twi_set_sda_hold_time; 250 } 251 } 252 253 #else /* CONFIG_OF */ 254 255 static inline void i2c_dw_of_configure(struct device *device) { } 256 257 #endif /* CONFIG_OF */ 258 259 #ifdef CONFIG_ACPI 260 261 #include <linux/dmi.h> 262 263 /* 264 * The HCNT/LCNT information coming from ACPI should be the most accurate 265 * for given platform. However, some systems get it wrong. On such systems 266 * we get better results by calculating those based on the input clock. 267 */ 268 static const struct dmi_system_id i2c_dw_no_acpi_params[] = { 269 { 270 .ident = "Dell Inspiron 7348", 271 .matches = { 272 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 273 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"), 274 }, 275 }, 276 {} 277 }; 278 279 static void i2c_dw_acpi_params(struct device *device, char method[], 280 u16 *hcnt, u16 *lcnt, u32 *sda_hold) 281 { 282 struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER }; 283 acpi_handle handle = ACPI_HANDLE(device); 284 union acpi_object *obj; 285 286 if (dmi_check_system(i2c_dw_no_acpi_params)) 287 return; 288 289 if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf))) 290 return; 291 292 obj = (union acpi_object *)buf.pointer; 293 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) { 294 const union acpi_object *objs = obj->package.elements; 295 296 *hcnt = (u16)objs[0].integer.value; 297 *lcnt = (u16)objs[1].integer.value; 298 *sda_hold = (u32)objs[2].integer.value; 299 } 300 301 kfree(buf.pointer); 302 } 303 304 static void i2c_dw_acpi_configure(struct device *device) 305 { 306 struct dw_i2c_dev *dev = dev_get_drvdata(device); 307 struct i2c_timings *t = &dev->timings; 308 u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0; 309 310 /* 311 * Try to get SDA hold time and *CNT values from an ACPI method for 312 * selected speed modes. 313 */ 314 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht); 315 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht); 316 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht); 317 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht); 318 319 switch (t->bus_freq_hz) { 320 case I2C_MAX_STANDARD_MODE_FREQ: 321 dev->sda_hold_time = ss_ht; 322 break; 323 case I2C_MAX_FAST_MODE_PLUS_FREQ: 324 dev->sda_hold_time = fp_ht; 325 break; 326 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 327 dev->sda_hold_time = hs_ht; 328 break; 329 case I2C_MAX_FAST_MODE_FREQ: 330 default: 331 dev->sda_hold_time = fs_ht; 332 break; 333 } 334 } 335 336 static u32 i2c_dw_acpi_round_bus_speed(struct device *device) 337 { 338 u32 acpi_speed; 339 int i; 340 341 acpi_speed = i2c_acpi_find_bus_speed(device); 342 /* 343 * Some DSDTs use a non standard speed, round down to the lowest 344 * standard speed. 345 */ 346 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) { 347 if (acpi_speed >= supported_speeds[i]) 348 return supported_speeds[i]; 349 } 350 351 return 0; 352 } 353 354 #else /* CONFIG_ACPI */ 355 356 static inline void i2c_dw_acpi_configure(struct device *device) { } 357 358 static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; } 359 360 #endif /* CONFIG_ACPI */ 361 362 static void i2c_dw_configure_mode(struct dw_i2c_dev *dev, int mode) 363 { 364 switch (mode) { 365 case DW_IC_MASTER: 366 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); 367 regmap_write(dev->map, DW_IC_RX_TL, 0); 368 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); 369 break; 370 case DW_IC_SLAVE: 371 dev->status = 0; 372 regmap_write(dev->map, DW_IC_TX_TL, 0); 373 regmap_write(dev->map, DW_IC_RX_TL, 0); 374 regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); 375 regmap_write(dev->map, DW_IC_SAR, dev->slave->addr); 376 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); 377 __i2c_dw_enable(dev); 378 break; 379 default: 380 WARN(1, "Invalid mode %d\n", mode); 381 return; 382 } 383 } 384 385 static void i2c_dw_write_timings(struct dw_i2c_dev *dev) 386 { 387 /* Write standard speed timing parameters */ 388 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); 389 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); 390 391 /* Write fast mode/fast mode plus timing parameters */ 392 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); 393 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); 394 395 /* Write high speed timing parameters */ 396 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); 397 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); 398 } 399 400 /** 401 * i2c_dw_set_mode() - Select the controller mode of operation - master or slave 402 * @dev: device private data 403 * @mode: I2C mode of operation 404 * 405 * Configures the controller to operate in @mode. This function needs to be 406 * called when ever a mode swap is required. 407 * 408 * Setting the slave mode does not have an effect before a slave device is 409 * registered. So before the slave device is registered, the controller is kept 410 * in master mode regardless of @mode. 411 * 412 * The controller must be disabled before this function is called. 413 */ 414 void i2c_dw_set_mode(struct dw_i2c_dev *dev, int mode) 415 { 416 if (mode == DW_IC_SLAVE && !dev->slave) 417 mode = DW_IC_MASTER; 418 if (dev->mode == mode) 419 return; 420 421 i2c_dw_configure_mode(dev, mode); 422 dev->mode = mode; 423 } 424 425 /** 426 * i2c_dw_init() - Initialize the DesignWare I2C hardware 427 * @dev: device private data 428 * 429 * This functions configures and enables the DesigWare I2C hardware. 430 * 431 * Return: 0 on success, or negative errno otherwise. 432 */ 433 int i2c_dw_init(struct dw_i2c_dev *dev) 434 { 435 int ret; 436 437 ret = i2c_dw_acquire_lock(dev); 438 if (ret) 439 return ret; 440 441 /* Disable the adapter */ 442 __i2c_dw_disable(dev); 443 444 /* 445 * Mask SMBus interrupts to block storms from broken 446 * firmware that leaves IC_SMBUS=1; the handler never 447 * services them. 448 */ 449 regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0); 450 451 i2c_dw_write_timings(dev); 452 453 /* Write SDA hold time if supported */ 454 if (dev->sda_hold_time) 455 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); 456 457 i2c_dw_configure_mode(dev, dev->mode); 458 459 i2c_dw_release_lock(dev); 460 461 return 0; 462 } 463 EXPORT_SYMBOL_GPL(i2c_dw_init); 464 465 static void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev) 466 { 467 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev); 468 struct i2c_timings *t = &dev->timings; 469 470 /* 471 * Find bus speed from the "clock-frequency" device property, ACPI 472 * or by using fast mode if neither is set. 473 */ 474 if (acpi_speed && t->bus_freq_hz) 475 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed); 476 else if (acpi_speed || t->bus_freq_hz) 477 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed); 478 else 479 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; 480 } 481 482 int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev) 483 { 484 struct i2c_timings *t = &dev->timings; 485 struct device *device = dev->dev; 486 struct fwnode_handle *fwnode = dev_fwnode(device); 487 488 i2c_parse_fw_timings(device, t, false); 489 490 if (device_property_read_u32(device, "snps,bus-capacitance-pf", &dev->bus_capacitance_pF)) 491 dev->bus_capacitance_pF = DW_IC_DEFAULT_BUS_CAPACITANCE_pF; 492 493 dev->clk_freq_optimized = device_property_read_bool(device, "snps,clk-freq-optimized"); 494 495 /* Mobileye controllers do not hold the clock on empty FIFO */ 496 if (device_is_compatible(device, "mobileye,eyeq6lplus-i2c")) 497 dev->emptyfifo_hold_master = false; 498 else 499 dev->emptyfifo_hold_master = true; 500 501 i2c_dw_adjust_bus_speed(dev); 502 503 if (is_of_node(fwnode)) 504 i2c_dw_of_configure(device); 505 else if (is_acpi_node(fwnode)) 506 i2c_dw_acpi_configure(device); 507 508 return i2c_dw_validate_speed(dev); 509 } 510 EXPORT_SYMBOL_GPL(i2c_dw_fw_parse_and_configure); 511 512 static u32 i2c_dw_read_scl_reg(struct dw_i2c_dev *dev, u32 reg) 513 { 514 u32 val; 515 int ret; 516 517 ret = i2c_dw_acquire_lock(dev); 518 if (ret) 519 return 0; 520 521 ret = regmap_read(dev->map, reg, &val); 522 i2c_dw_release_lock(dev); 523 524 return ret ? 0 : val; 525 } 526 527 u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 528 u32 tSYMBOL, u32 tf, int offset) 529 { 530 if (!ic_clk) 531 return i2c_dw_read_scl_reg(dev, reg); 532 533 /* 534 * Conditional expression: 535 * 536 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) 537 * 538 * This is just experimental rule; the tHD;STA period turned 539 * out to be proportinal to (_HCNT + 3). With this setting, 540 * we could meet both tHIGH and tHD;STA timing specs. 541 * 542 * If unsure, you'd better to take this alternative. 543 * 544 * The reason why we need to take into account "tf" here, 545 * is the same as described in i2c_dw_scl_lcnt(). 546 */ 547 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) - 3 + offset; 548 } 549 550 u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 551 u32 tLOW, u32 tf, int offset) 552 { 553 if (!ic_clk) 554 return i2c_dw_read_scl_reg(dev, reg); 555 556 /* 557 * Conditional expression: 558 * 559 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) 560 * 561 * DW I2C core starts counting the SCL CNTs for the LOW period 562 * of the SCL clock (tLOW) as soon as it pulls the SCL line. 563 * In order to meet the tLOW timing spec, we need to take into 564 * account the fall time of SCL signal (tf). Default tf value 565 * should be 0.3 us, for safety. 566 */ 567 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - 1 + offset; 568 } 569 570 static int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) 571 { 572 unsigned int reg; 573 int ret; 574 575 ret = i2c_dw_acquire_lock(dev); 576 if (ret) 577 return ret; 578 579 /* Configure SDA Hold Time if required */ 580 ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®); 581 if (ret) 582 goto err_release_lock; 583 584 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { 585 if (!dev->sda_hold_time) { 586 /* Keep previous hold time setting if no one set it */ 587 ret = regmap_read(dev->map, DW_IC_SDA_HOLD, 588 &dev->sda_hold_time); 589 if (ret) 590 goto err_release_lock; 591 } 592 593 /* 594 * Workaround for avoiding TX arbitration lost in case I2C 595 * slave pulls SDA down "too quickly" after falling edge of 596 * SCL by enabling non-zero SDA RX hold. Specification says it 597 * extends incoming SDA low to high transition while SCL is 598 * high but it appears to help also above issue. 599 */ 600 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) 601 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; 602 603 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n", 604 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK, 605 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT); 606 } else if (dev->set_sda_hold_time) { 607 dev->set_sda_hold_time(dev); 608 } else if (dev->sda_hold_time) { 609 dev_warn(dev->dev, 610 "Hardware too old to adjust SDA hold time.\n"); 611 dev->sda_hold_time = 0; 612 } 613 614 err_release_lock: 615 i2c_dw_release_lock(dev); 616 617 return ret; 618 } 619 620 void __i2c_dw_disable(struct dw_i2c_dev *dev) 621 { 622 struct i2c_timings *t = &dev->timings; 623 unsigned int raw_intr_stats, ic_stats; 624 unsigned int enable; 625 int timeout = 100; 626 bool abort_needed; 627 unsigned int status; 628 int ret; 629 630 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_intr_stats); 631 regmap_read(dev->map, DW_IC_STATUS, &ic_stats); 632 regmap_read(dev->map, DW_IC_ENABLE, &enable); 633 634 abort_needed = (raw_intr_stats & DW_IC_INTR_MST_ON_HOLD) || 635 (ic_stats & DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY); 636 if (abort_needed) { 637 if (!(enable & DW_IC_ENABLE_ENABLE)) { 638 regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE); 639 /* 640 * Wait 10 times the signaling period of the highest I2C 641 * transfer supported by the driver (for 400KHz this is 642 * 25us) to ensure the I2C ENABLE bit is already set 643 * as described in the DesignWare I2C databook. 644 */ 645 fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz)); 646 /* Set ENABLE bit before setting ABORT */ 647 enable |= DW_IC_ENABLE_ENABLE; 648 } 649 650 regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT); 651 ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable, 652 !(enable & DW_IC_ENABLE_ABORT), 653 DW_IC_ABORT_TIMEOUT_US, 654 10 * DW_IC_ABORT_TIMEOUT_US); 655 if (ret) 656 dev_err(dev->dev, "timeout while trying to abort current transfer\n"); 657 } 658 659 do { 660 __i2c_dw_disable_nowait(dev); 661 /* 662 * The enable status register may be unimplemented, but 663 * in that case this test reads zero and exits the loop. 664 */ 665 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status); 666 if (!(status & 1)) 667 return; 668 669 /* 670 * Wait 10 times the signaling period of the highest I2C 671 * transfer supported by the driver (for 400kHz this is 672 * 25us) as described in the DesignWare I2C databook. 673 */ 674 usleep_range(25, 250); 675 } while (timeout--); 676 677 dev_warn(dev->dev, "timeout in disabling adapter\n"); 678 } 679 680 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev) 681 { 682 /* 683 * Clock is not necessary if we got LCNT/HCNT values directly from 684 * the platform code. 685 */ 686 if (!dev->get_clk_rate_khz) { 687 dev_dbg_once(dev->dev, "Callback get_clk_rate_khz() is not defined\n"); 688 return 0; 689 } 690 return dev->get_clk_rate_khz(dev); 691 } 692 693 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare) 694 { 695 int ret; 696 697 if (prepare) { 698 /* Optional interface clock */ 699 ret = clk_prepare_enable(dev->pclk); 700 if (ret) 701 return ret; 702 703 ret = clk_prepare_enable(dev->clk); 704 if (ret) 705 clk_disable_unprepare(dev->pclk); 706 707 return ret; 708 } 709 710 clk_disable_unprepare(dev->clk); 711 clk_disable_unprepare(dev->pclk); 712 713 return 0; 714 } 715 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk); 716 717 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev) 718 { 719 int ret; 720 721 if (!dev->acquire_lock) 722 return 0; 723 724 ret = dev->acquire_lock(); 725 if (!ret) 726 return 0; 727 728 dev_err(dev->dev, "couldn't acquire bus ownership\n"); 729 730 return ret; 731 } 732 733 void i2c_dw_release_lock(struct dw_i2c_dev *dev) 734 { 735 if (dev->release_lock) 736 dev->release_lock(); 737 } 738 739 /* 740 * Waiting for bus not busy 741 */ 742 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) 743 { 744 unsigned int status; 745 int ret; 746 747 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, 748 !(status & DW_IC_STATUS_ACTIVITY), 749 DW_IC_BUSY_POLL_TIMEOUT_US, 750 20 * DW_IC_BUSY_POLL_TIMEOUT_US); 751 if (ret) { 752 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 753 754 i2c_recover_bus(&dev->adapter); 755 756 regmap_read(dev->map, DW_IC_STATUS, &status); 757 if (!(status & DW_IC_STATUS_ACTIVITY)) 758 ret = 0; 759 } 760 761 return ret; 762 } 763 764 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) 765 { 766 unsigned long abort_source = dev->abort_source; 767 int i; 768 769 if (abort_source & DW_IC_TX_ABRT_NOACK) { 770 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 771 dev_dbg(dev->dev, 772 "%s: %s\n", __func__, abort_sources[i]); 773 return -EREMOTEIO; 774 } 775 776 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 777 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); 778 779 if (abort_source & DW_IC_TX_ARB_LOST) 780 return -EAGAIN; 781 if (abort_source & DW_IC_TX_ABRT_GCALL_READ) 782 return -EINVAL; /* wrong msgs[] data */ 783 784 return -EIO; 785 } 786 787 static int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) 788 { 789 u32 tx_fifo_depth, rx_fifo_depth; 790 unsigned int param; 791 int ret; 792 793 /* DW_IC_COMP_PARAM_1 not implement for IP issue */ 794 if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) { 795 dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH; 796 dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH; 797 798 return 0; 799 } 800 801 /* 802 * Try to detect the FIFO depth if not set by interface driver, 803 * the depth could be from 2 to 256 from HW spec. 804 */ 805 ret = i2c_dw_acquire_lock(dev); 806 if (ret) 807 return ret; 808 809 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m); 810 i2c_dw_release_lock(dev); 811 if (ret) 812 return ret; 813 814 tx_fifo_depth = FIELD_GET(DW_IC_FIFO_TX_FIELD, param) + 1; 815 rx_fifo_depth = FIELD_GET(DW_IC_FIFO_RX_FIELD, param) + 1; 816 if (!dev->tx_fifo_depth) { 817 dev->tx_fifo_depth = tx_fifo_depth; 818 dev->rx_fifo_depth = rx_fifo_depth; 819 } else if (tx_fifo_depth >= DW_IC_FIFO_MIN_DEPTH) { 820 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth, 821 tx_fifo_depth); 822 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth, 823 rx_fifo_depth); 824 } 825 826 return 0; 827 } 828 829 u32 i2c_dw_func(struct i2c_adapter *adap) 830 { 831 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 832 833 return dev->functionality; 834 } 835 836 void i2c_dw_disable(struct dw_i2c_dev *dev) 837 { 838 unsigned int dummy; 839 int ret; 840 841 ret = i2c_dw_acquire_lock(dev); 842 if (ret) 843 return; 844 845 /* Disable controller */ 846 __i2c_dw_disable(dev); 847 848 /* Disable all interrupts */ 849 __i2c_dw_write_intr_mask(dev, 0); 850 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); 851 852 i2c_dw_release_lock(dev); 853 } 854 EXPORT_SYMBOL_GPL(i2c_dw_disable); 855 856 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) 857 { 858 struct dw_i2c_dev *dev = dev_id; 859 860 if (dev->mode == DW_IC_SLAVE) 861 return i2c_dw_isr_slave(dev); 862 863 return i2c_dw_isr_master(dev); 864 } 865 866 static const struct i2c_algorithm i2c_dw_algo = { 867 .xfer = i2c_dw_xfer, 868 .functionality = i2c_dw_func, 869 #if IS_ENABLED(CONFIG_I2C_SLAVE) 870 .reg_slave = i2c_dw_reg_slave, 871 .unreg_slave = i2c_dw_unreg_slave, 872 #endif 873 }; 874 875 static const struct i2c_adapter_quirks i2c_dw_quirks = { 876 .flags = I2C_AQ_NO_ZERO_LEN, 877 }; 878 879 int i2c_dw_probe(struct dw_i2c_dev *dev) 880 { 881 struct i2c_adapter *adap = &dev->adapter; 882 unsigned long irq_flags; 883 int ret; 884 885 device_set_node(&dev->adapter.dev, dev_fwnode(dev->dev)); 886 887 ret = i2c_dw_init_regmap(dev); 888 if (ret) 889 return ret; 890 891 ret = i2c_dw_set_sda_hold(dev); 892 if (ret) 893 return ret; 894 895 ret = i2c_dw_set_fifo_size(dev); 896 if (ret) 897 return ret; 898 899 ret = i2c_dw_probe_master(dev); 900 if (ret) 901 return ret; 902 903 ret = i2c_dw_init(dev); 904 if (ret) 905 return ret; 906 907 if (!adap->name[0]) 908 strscpy(adap->name, "Synopsys DesignWare I2C adapter"); 909 910 adap->retries = 3; 911 adap->algo = &i2c_dw_algo; 912 adap->quirks = &i2c_dw_quirks; 913 adap->dev.parent = dev->dev; 914 i2c_set_adapdata(adap, dev); 915 916 /* 917 * REVISIT: The mode check may not be necessary. 918 * For now keeping the flags as they were originally. 919 */ 920 if (dev->mode == DW_IC_SLAVE) 921 irq_flags = IRQF_SHARED; 922 else if (dev->flags & ACCESS_NO_IRQ_SUSPEND) 923 irq_flags = IRQF_NO_SUSPEND; 924 else 925 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND; 926 927 /* 928 * The first writing to TX FIFO buffer causes transmission start. 929 * If IC_EMPTYFIFO_HOLD_MASTER_EN is not set, when TX FIFO gets 930 * empty, I2C controller finishes the transaction. If writing to 931 * FIFO is interrupted, FIFO can get empty and the transaction will 932 * be finished prematurely. FIFO buffer is filled in IRQ handler, 933 * but in PREEMPT_RT kernel IRQ handler by default is executed 934 * in thread that can be preempted with another higher priority 935 * thread or an interrupt. So, IRQF_NO_THREAD flag is required in 936 * order to prevent any preemption when filling the FIFO. 937 */ 938 if (!dev->emptyfifo_hold_master) 939 irq_flags |= IRQF_NO_THREAD; 940 941 ret = i2c_dw_acquire_lock(dev); 942 if (ret) 943 return ret; 944 945 __i2c_dw_write_intr_mask(dev, 0); 946 i2c_dw_release_lock(dev); 947 948 if (!(dev->flags & ACCESS_POLLING)) { 949 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, 950 irq_flags, dev_name(dev->dev), dev); 951 if (ret) 952 return ret; 953 } 954 955 /* 956 * Increment PM usage count during adapter registration in order to 957 * avoid possible spurious runtime suspend when adapter device is 958 * registered to the device core and immediate resume in case bus has 959 * registered I2C slaves that do I2C transfers in their probe. 960 */ 961 ACQUIRE(pm_runtime_noresume, pm)(dev->dev); 962 ret = ACQUIRE_ERR(pm_runtime_noresume, &pm); 963 if (ret) 964 return ret; 965 966 return i2c_add_numbered_adapter(adap); 967 } 968 EXPORT_SYMBOL_GPL(i2c_dw_probe); 969 970 static int i2c_dw_prepare(struct device *device) 971 { 972 /* 973 * If the ACPI companion device object is present for this device, 974 * it may be accessed during suspend and resume of other devices via 975 * I2C operation regions, so tell the PM core and middle layers to 976 * avoid skipping system suspend/resume callbacks for it in that case. 977 */ 978 return !has_acpi_companion(device); 979 } 980 981 static int i2c_dw_runtime_suspend(struct device *device) 982 { 983 struct dw_i2c_dev *dev = dev_get_drvdata(device); 984 985 if (dev->shared_with_punit) 986 return 0; 987 988 i2c_dw_disable(dev); 989 i2c_dw_prepare_clk(dev, false); 990 991 return 0; 992 } 993 994 static int i2c_dw_suspend(struct device *device) 995 { 996 struct dw_i2c_dev *dev = dev_get_drvdata(device); 997 998 i2c_mark_adapter_suspended(&dev->adapter); 999 1000 return i2c_dw_runtime_suspend(device); 1001 } 1002 1003 static int i2c_dw_runtime_resume(struct device *device) 1004 { 1005 struct dw_i2c_dev *dev = dev_get_drvdata(device); 1006 1007 if (!dev->shared_with_punit) 1008 i2c_dw_prepare_clk(dev, true); 1009 1010 i2c_dw_init(dev); 1011 1012 return 0; 1013 } 1014 1015 static int i2c_dw_resume(struct device *device) 1016 { 1017 struct dw_i2c_dev *dev = dev_get_drvdata(device); 1018 1019 i2c_dw_runtime_resume(device); 1020 i2c_mark_adapter_resumed(&dev->adapter); 1021 1022 return 0; 1023 } 1024 1025 EXPORT_GPL_DEV_PM_OPS(i2c_dw_dev_pm_ops) = { 1026 .prepare = pm_sleep_ptr(i2c_dw_prepare), 1027 LATE_SYSTEM_SLEEP_PM_OPS(i2c_dw_suspend, i2c_dw_resume) 1028 RUNTIME_PM_OPS(i2c_dw_runtime_suspend, i2c_dw_runtime_resume, NULL) 1029 }; 1030 1031 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); 1032 MODULE_LICENSE("GPL"); 1033