1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Synopsys DesignWare I2C adapter driver. 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 #include <linux/acpi.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/errno.h> 17 #include <linux/export.h> 18 #include <linux/i2c.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/pm.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/property.h> 27 #include <linux/regmap.h> 28 #include <linux/swab.h> 29 #include <linux/types.h> 30 #include <linux/units.h> 31 32 #define DEFAULT_SYMBOL_NAMESPACE I2C_DW_COMMON 33 34 #include "i2c-designware-core.h" 35 36 static char *abort_sources[] = { 37 [ABRT_7B_ADDR_NOACK] = 38 "slave address not acknowledged (7bit mode)", 39 [ABRT_10ADDR1_NOACK] = 40 "first address byte not acknowledged (10bit mode)", 41 [ABRT_10ADDR2_NOACK] = 42 "second address byte not acknowledged (10bit mode)", 43 [ABRT_TXDATA_NOACK] = 44 "data not acknowledged", 45 [ABRT_GCALL_NOACK] = 46 "no acknowledgement for a general call", 47 [ABRT_GCALL_READ] = 48 "read after general call", 49 [ABRT_SBYTE_ACKDET] = 50 "start byte acknowledged", 51 [ABRT_SBYTE_NORSTRT] = 52 "trying to send start byte when restart is disabled", 53 [ABRT_10B_RD_NORSTRT] = 54 "trying to read when restart is disabled (10bit mode)", 55 [ABRT_MASTER_DIS] = 56 "trying to use disabled adapter", 57 [ARB_LOST] = 58 "lost arbitration", 59 [ABRT_SLAVE_FLUSH_TXFIFO] = 60 "read command so flush old data in the TX FIFO", 61 [ABRT_SLAVE_ARBLOST] = 62 "slave lost the bus while transmitting data to a remote master", 63 [ABRT_SLAVE_RD_INTX] = 64 "incorrect slave-transmitter mode configuration", 65 }; 66 67 static int dw_reg_read(void *context, unsigned int reg, unsigned int *val) 68 { 69 struct dw_i2c_dev *dev = context; 70 71 *val = readl(dev->base + reg); 72 73 return 0; 74 } 75 76 static int dw_reg_write(void *context, unsigned int reg, unsigned int val) 77 { 78 struct dw_i2c_dev *dev = context; 79 80 writel(val, dev->base + reg); 81 82 return 0; 83 } 84 85 static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val) 86 { 87 struct dw_i2c_dev *dev = context; 88 89 *val = swab32(readl(dev->base + reg)); 90 91 return 0; 92 } 93 94 static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val) 95 { 96 struct dw_i2c_dev *dev = context; 97 98 writel(swab32(val), dev->base + reg); 99 100 return 0; 101 } 102 103 static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val) 104 { 105 struct dw_i2c_dev *dev = context; 106 107 *val = readw(dev->base + reg) | 108 (readw(dev->base + reg + 2) << 16); 109 110 return 0; 111 } 112 113 static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val) 114 { 115 struct dw_i2c_dev *dev = context; 116 117 writew(val, dev->base + reg); 118 writew(val >> 16, dev->base + reg + 2); 119 120 return 0; 121 } 122 123 /** 124 * i2c_dw_init_regmap() - Initialize registers map 125 * @dev: device private data 126 * 127 * Autodetects needed register access mode and creates the regmap with 128 * corresponding read/write callbacks. This must be called before doing any 129 * other register access. 130 */ 131 int i2c_dw_init_regmap(struct dw_i2c_dev *dev) 132 { 133 struct regmap_config map_cfg = { 134 .reg_bits = 32, 135 .val_bits = 32, 136 .reg_stride = 4, 137 .disable_locking = true, 138 .reg_read = dw_reg_read, 139 .reg_write = dw_reg_write, 140 .max_register = DW_IC_COMP_TYPE, 141 }; 142 u32 reg; 143 int ret; 144 145 /* 146 * Skip detecting the registers map configuration if the regmap has 147 * already been provided by a higher code. 148 */ 149 if (dev->map) 150 return 0; 151 152 ret = i2c_dw_acquire_lock(dev); 153 if (ret) 154 return ret; 155 156 reg = readl(dev->base + DW_IC_COMP_TYPE); 157 i2c_dw_release_lock(dev); 158 159 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) 160 map_cfg.max_register = AMD_UCSI_INTR_REG; 161 162 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) { 163 map_cfg.reg_read = dw_reg_read_swab; 164 map_cfg.reg_write = dw_reg_write_swab; 165 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { 166 map_cfg.reg_read = dw_reg_read_word; 167 map_cfg.reg_write = dw_reg_write_word; 168 } else if (reg != DW_IC_COMP_TYPE_VALUE) { 169 dev_err(dev->dev, 170 "Unknown Synopsys component type: 0x%08x\n", reg); 171 return -ENODEV; 172 } 173 174 /* 175 * Note we'll check the return value of the regmap IO accessors only 176 * at the probe stage. The rest of the code won't do this because 177 * basically we have MMIO-based regmap so non of the read/write methods 178 * can fail. 179 */ 180 dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg); 181 if (IS_ERR(dev->map)) { 182 dev_err(dev->dev, "Failed to init the registers map\n"); 183 return PTR_ERR(dev->map); 184 } 185 186 return 0; 187 } 188 189 static const u32 supported_speeds[] = { 190 I2C_MAX_HIGH_SPEED_MODE_FREQ, 191 I2C_MAX_FAST_MODE_PLUS_FREQ, 192 I2C_MAX_FAST_MODE_FREQ, 193 I2C_MAX_STANDARD_MODE_FREQ, 194 }; 195 196 static int i2c_dw_validate_speed(struct dw_i2c_dev *dev) 197 { 198 struct i2c_timings *t = &dev->timings; 199 unsigned int i; 200 201 /* 202 * Only standard mode at 100kHz, fast mode at 400kHz, 203 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported. 204 */ 205 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) { 206 if (t->bus_freq_hz == supported_speeds[i]) 207 return 0; 208 } 209 210 dev_err(dev->dev, 211 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n", 212 t->bus_freq_hz); 213 214 return -EINVAL; 215 } 216 217 #ifdef CONFIG_OF 218 219 #include <linux/platform_device.h> 220 221 #define MSCC_ICPU_CFG_TWI_DELAY 0x0 222 #define MSCC_ICPU_CFG_TWI_DELAY_ENABLE BIT(0) 223 #define MSCC_ICPU_CFG_TWI_SPIKE_FILTER 0x4 224 225 static int mscc_twi_set_sda_hold_time(struct dw_i2c_dev *dev) 226 { 227 writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE, 228 dev->ext + MSCC_ICPU_CFG_TWI_DELAY); 229 230 return 0; 231 } 232 233 static void i2c_dw_of_configure(struct device *device) 234 { 235 struct platform_device *pdev = to_platform_device(device); 236 struct dw_i2c_dev *dev = dev_get_drvdata(device); 237 238 switch (dev->flags & MODEL_MASK) { 239 case MODEL_MSCC_OCELOT: 240 dev->ext = devm_platform_ioremap_resource(pdev, 1); 241 if (!IS_ERR(dev->ext)) 242 dev->set_sda_hold_time = mscc_twi_set_sda_hold_time; 243 break; 244 default: 245 break; 246 } 247 } 248 249 #else /* CONFIG_OF */ 250 251 static inline void i2c_dw_of_configure(struct device *device) { } 252 253 #endif /* CONFIG_OF */ 254 255 #ifdef CONFIG_ACPI 256 257 #include <linux/dmi.h> 258 259 /* 260 * The HCNT/LCNT information coming from ACPI should be the most accurate 261 * for given platform. However, some systems get it wrong. On such systems 262 * we get better results by calculating those based on the input clock. 263 */ 264 static const struct dmi_system_id i2c_dw_no_acpi_params[] = { 265 { 266 .ident = "Dell Inspiron 7348", 267 .matches = { 268 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 269 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"), 270 }, 271 }, 272 {} 273 }; 274 275 static void i2c_dw_acpi_params(struct device *device, char method[], 276 u16 *hcnt, u16 *lcnt, u32 *sda_hold) 277 { 278 struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER }; 279 acpi_handle handle = ACPI_HANDLE(device); 280 union acpi_object *obj; 281 282 if (dmi_check_system(i2c_dw_no_acpi_params)) 283 return; 284 285 if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf))) 286 return; 287 288 obj = (union acpi_object *)buf.pointer; 289 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) { 290 const union acpi_object *objs = obj->package.elements; 291 292 *hcnt = (u16)objs[0].integer.value; 293 *lcnt = (u16)objs[1].integer.value; 294 *sda_hold = (u32)objs[2].integer.value; 295 } 296 297 kfree(buf.pointer); 298 } 299 300 static void i2c_dw_acpi_configure(struct device *device) 301 { 302 struct dw_i2c_dev *dev = dev_get_drvdata(device); 303 struct i2c_timings *t = &dev->timings; 304 u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0; 305 306 /* 307 * Try to get SDA hold time and *CNT values from an ACPI method for 308 * selected speed modes. 309 */ 310 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht); 311 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht); 312 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht); 313 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht); 314 315 switch (t->bus_freq_hz) { 316 case I2C_MAX_STANDARD_MODE_FREQ: 317 dev->sda_hold_time = ss_ht; 318 break; 319 case I2C_MAX_FAST_MODE_PLUS_FREQ: 320 dev->sda_hold_time = fp_ht; 321 break; 322 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 323 dev->sda_hold_time = hs_ht; 324 break; 325 case I2C_MAX_FAST_MODE_FREQ: 326 default: 327 dev->sda_hold_time = fs_ht; 328 break; 329 } 330 } 331 332 static u32 i2c_dw_acpi_round_bus_speed(struct device *device) 333 { 334 u32 acpi_speed; 335 int i; 336 337 acpi_speed = i2c_acpi_find_bus_speed(device); 338 /* 339 * Some DSTDs use a non standard speed, round down to the lowest 340 * standard speed. 341 */ 342 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) { 343 if (acpi_speed >= supported_speeds[i]) 344 return supported_speeds[i]; 345 } 346 347 return 0; 348 } 349 350 #else /* CONFIG_ACPI */ 351 352 static inline void i2c_dw_acpi_configure(struct device *device) { } 353 354 static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; } 355 356 #endif /* CONFIG_ACPI */ 357 358 static void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev) 359 { 360 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev); 361 struct i2c_timings *t = &dev->timings; 362 363 /* 364 * Find bus speed from the "clock-frequency" device property, ACPI 365 * or by using fast mode if neither is set. 366 */ 367 if (acpi_speed && t->bus_freq_hz) 368 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed); 369 else if (acpi_speed || t->bus_freq_hz) 370 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed); 371 else 372 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; 373 } 374 375 int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev) 376 { 377 struct i2c_timings *t = &dev->timings; 378 struct device *device = dev->dev; 379 struct fwnode_handle *fwnode = dev_fwnode(device); 380 381 i2c_parse_fw_timings(device, t, false); 382 383 i2c_dw_adjust_bus_speed(dev); 384 385 if (is_of_node(fwnode)) 386 i2c_dw_of_configure(device); 387 else if (is_acpi_node(fwnode)) 388 i2c_dw_acpi_configure(device); 389 390 return i2c_dw_validate_speed(dev); 391 } 392 EXPORT_SYMBOL_GPL(i2c_dw_fw_parse_and_configure); 393 394 static u32 i2c_dw_read_scl_reg(struct dw_i2c_dev *dev, u32 reg) 395 { 396 u32 val; 397 int ret; 398 399 ret = i2c_dw_acquire_lock(dev); 400 if (ret) 401 return 0; 402 403 ret = regmap_read(dev->map, reg, &val); 404 i2c_dw_release_lock(dev); 405 406 return ret ? 0 : val; 407 } 408 409 u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 410 u32 tSYMBOL, u32 tf, int cond, int offset) 411 { 412 if (!ic_clk) 413 return i2c_dw_read_scl_reg(dev, reg); 414 415 /* 416 * DesignWare I2C core doesn't seem to have solid strategy to meet 417 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec 418 * will result in violation of the tHD;STA spec. 419 */ 420 if (cond) 421 /* 422 * Conditional expression: 423 * 424 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH 425 * 426 * This is based on the DW manuals, and represents an ideal 427 * configuration. The resulting I2C bus speed will be 428 * faster than any of the others. 429 * 430 * If your hardware is free from tHD;STA issue, try this one. 431 */ 432 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * tSYMBOL, MICRO) - 433 8 + offset; 434 else 435 /* 436 * Conditional expression: 437 * 438 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) 439 * 440 * This is just experimental rule; the tHD;STA period turned 441 * out to be proportinal to (_HCNT + 3). With this setting, 442 * we could meet both tHIGH and tHD;STA timing specs. 443 * 444 * If unsure, you'd better to take this alternative. 445 * 446 * The reason why we need to take into account "tf" here, 447 * is the same as described in i2c_dw_scl_lcnt(). 448 */ 449 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) - 450 3 + offset; 451 } 452 453 u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 454 u32 tLOW, u32 tf, int offset) 455 { 456 if (!ic_clk) 457 return i2c_dw_read_scl_reg(dev, reg); 458 459 /* 460 * Conditional expression: 461 * 462 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) 463 * 464 * DW I2C core starts counting the SCL CNTs for the LOW period 465 * of the SCL clock (tLOW) as soon as it pulls the SCL line. 466 * In order to meet the tLOW timing spec, we need to take into 467 * account the fall time of SCL signal (tf). Default tf value 468 * should be 0.3 us, for safety. 469 */ 470 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - 471 1 + offset; 472 } 473 474 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) 475 { 476 unsigned int reg; 477 int ret; 478 479 ret = i2c_dw_acquire_lock(dev); 480 if (ret) 481 return ret; 482 483 /* Configure SDA Hold Time if required */ 484 ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®); 485 if (ret) 486 goto err_release_lock; 487 488 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { 489 if (!dev->sda_hold_time) { 490 /* Keep previous hold time setting if no one set it */ 491 ret = regmap_read(dev->map, DW_IC_SDA_HOLD, 492 &dev->sda_hold_time); 493 if (ret) 494 goto err_release_lock; 495 } 496 497 /* 498 * Workaround for avoiding TX arbitration lost in case I2C 499 * slave pulls SDA down "too quickly" after falling edge of 500 * SCL by enabling non-zero SDA RX hold. Specification says it 501 * extends incoming SDA low to high transition while SCL is 502 * high but it appears to help also above issue. 503 */ 504 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) 505 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; 506 507 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n", 508 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK, 509 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT); 510 } else if (dev->set_sda_hold_time) { 511 dev->set_sda_hold_time(dev); 512 } else if (dev->sda_hold_time) { 513 dev_warn(dev->dev, 514 "Hardware too old to adjust SDA hold time.\n"); 515 dev->sda_hold_time = 0; 516 } 517 518 err_release_lock: 519 i2c_dw_release_lock(dev); 520 521 return ret; 522 } 523 524 void __i2c_dw_disable(struct dw_i2c_dev *dev) 525 { 526 struct i2c_timings *t = &dev->timings; 527 unsigned int raw_intr_stats; 528 unsigned int enable; 529 int timeout = 100; 530 bool abort_needed; 531 unsigned int status; 532 int ret; 533 534 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_intr_stats); 535 regmap_read(dev->map, DW_IC_ENABLE, &enable); 536 537 abort_needed = raw_intr_stats & DW_IC_INTR_MST_ON_HOLD; 538 if (abort_needed) { 539 if (!(enable & DW_IC_ENABLE_ENABLE)) { 540 regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE); 541 /* 542 * Wait 10 times the signaling period of the highest I2C 543 * transfer supported by the driver (for 400KHz this is 544 * 25us) to ensure the I2C ENABLE bit is already set 545 * as described in the DesignWare I2C databook. 546 */ 547 fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz)); 548 /* Set ENABLE bit before setting ABORT */ 549 enable |= DW_IC_ENABLE_ENABLE; 550 } 551 552 regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT); 553 ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable, 554 !(enable & DW_IC_ENABLE_ABORT), 10, 555 100); 556 if (ret) 557 dev_err(dev->dev, "timeout while trying to abort current transfer\n"); 558 } 559 560 do { 561 __i2c_dw_disable_nowait(dev); 562 /* 563 * The enable status register may be unimplemented, but 564 * in that case this test reads zero and exits the loop. 565 */ 566 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status); 567 if ((status & 1) == 0) 568 return; 569 570 /* 571 * Wait 10 times the signaling period of the highest I2C 572 * transfer supported by the driver (for 400KHz this is 573 * 25us) as described in the DesignWare I2C databook. 574 */ 575 usleep_range(25, 250); 576 } while (timeout--); 577 578 dev_warn(dev->dev, "timeout in disabling adapter\n"); 579 } 580 581 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev) 582 { 583 /* 584 * Clock is not necessary if we got LCNT/HCNT values directly from 585 * the platform code. 586 */ 587 if (WARN_ON_ONCE(!dev->get_clk_rate_khz)) 588 return 0; 589 return dev->get_clk_rate_khz(dev); 590 } 591 592 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare) 593 { 594 int ret; 595 596 if (prepare) { 597 /* Optional interface clock */ 598 ret = clk_prepare_enable(dev->pclk); 599 if (ret) 600 return ret; 601 602 ret = clk_prepare_enable(dev->clk); 603 if (ret) 604 clk_disable_unprepare(dev->pclk); 605 606 return ret; 607 } 608 609 clk_disable_unprepare(dev->clk); 610 clk_disable_unprepare(dev->pclk); 611 612 return 0; 613 } 614 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk); 615 616 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev) 617 { 618 int ret; 619 620 if (!dev->acquire_lock) 621 return 0; 622 623 ret = dev->acquire_lock(); 624 if (!ret) 625 return 0; 626 627 dev_err(dev->dev, "couldn't acquire bus ownership\n"); 628 629 return ret; 630 } 631 632 void i2c_dw_release_lock(struct dw_i2c_dev *dev) 633 { 634 if (dev->release_lock) 635 dev->release_lock(); 636 } 637 638 /* 639 * Waiting for bus not busy 640 */ 641 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) 642 { 643 unsigned int status; 644 int ret; 645 646 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, 647 !(status & DW_IC_STATUS_ACTIVITY), 648 1100, 20000); 649 if (ret) { 650 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 651 652 i2c_recover_bus(&dev->adapter); 653 654 regmap_read(dev->map, DW_IC_STATUS, &status); 655 if (!(status & DW_IC_STATUS_ACTIVITY)) 656 ret = 0; 657 } 658 659 return ret; 660 } 661 662 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) 663 { 664 unsigned long abort_source = dev->abort_source; 665 int i; 666 667 if (abort_source & DW_IC_TX_ABRT_NOACK) { 668 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 669 dev_dbg(dev->dev, 670 "%s: %s\n", __func__, abort_sources[i]); 671 return -EREMOTEIO; 672 } 673 674 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 675 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); 676 677 if (abort_source & DW_IC_TX_ARB_LOST) 678 return -EAGAIN; 679 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) 680 return -EINVAL; /* wrong msgs[] data */ 681 else 682 return -EIO; 683 } 684 685 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) 686 { 687 u32 tx_fifo_depth, rx_fifo_depth; 688 unsigned int param; 689 int ret; 690 691 /* DW_IC_COMP_PARAM_1 not implement for IP issue */ 692 if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) { 693 dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH; 694 dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH; 695 696 return 0; 697 } 698 699 /* 700 * Try to detect the FIFO depth if not set by interface driver, 701 * the depth could be from 2 to 256 from HW spec. 702 */ 703 ret = i2c_dw_acquire_lock(dev); 704 if (ret) 705 return ret; 706 707 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m); 708 i2c_dw_release_lock(dev); 709 if (ret) 710 return ret; 711 712 tx_fifo_depth = ((param >> 16) & 0xff) + 1; 713 rx_fifo_depth = ((param >> 8) & 0xff) + 1; 714 if (!dev->tx_fifo_depth) { 715 dev->tx_fifo_depth = tx_fifo_depth; 716 dev->rx_fifo_depth = rx_fifo_depth; 717 } else if (tx_fifo_depth >= 2) { 718 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth, 719 tx_fifo_depth); 720 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth, 721 rx_fifo_depth); 722 } 723 724 return 0; 725 } 726 727 u32 i2c_dw_func(struct i2c_adapter *adap) 728 { 729 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 730 731 return dev->functionality; 732 } 733 734 void i2c_dw_disable(struct dw_i2c_dev *dev) 735 { 736 unsigned int dummy; 737 int ret; 738 739 ret = i2c_dw_acquire_lock(dev); 740 if (ret) 741 return; 742 743 /* Disable controller */ 744 __i2c_dw_disable(dev); 745 746 /* Disable all interrupts */ 747 __i2c_dw_write_intr_mask(dev, 0); 748 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); 749 750 i2c_dw_release_lock(dev); 751 } 752 EXPORT_SYMBOL_GPL(i2c_dw_disable); 753 754 int i2c_dw_probe(struct dw_i2c_dev *dev) 755 { 756 device_set_node(&dev->adapter.dev, dev_fwnode(dev->dev)); 757 758 switch (dev->mode) { 759 case DW_IC_SLAVE: 760 return i2c_dw_probe_slave(dev); 761 case DW_IC_MASTER: 762 return i2c_dw_probe_master(dev); 763 default: 764 dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode); 765 return -EINVAL; 766 } 767 } 768 EXPORT_SYMBOL_GPL(i2c_dw_probe); 769 770 static int i2c_dw_prepare(struct device *device) 771 { 772 /* 773 * If the ACPI companion device object is present for this device, 774 * it may be accessed during suspend and resume of other devices via 775 * I2C operation regions, so tell the PM core and middle layers to 776 * avoid skipping system suspend/resume callbacks for it in that case. 777 */ 778 return !has_acpi_companion(device); 779 } 780 781 static int i2c_dw_runtime_suspend(struct device *device) 782 { 783 struct dw_i2c_dev *dev = dev_get_drvdata(device); 784 785 if (dev->shared_with_punit) 786 return 0; 787 788 i2c_dw_disable(dev); 789 i2c_dw_prepare_clk(dev, false); 790 791 return 0; 792 } 793 794 static int i2c_dw_suspend(struct device *device) 795 { 796 struct dw_i2c_dev *dev = dev_get_drvdata(device); 797 798 i2c_mark_adapter_suspended(&dev->adapter); 799 800 return i2c_dw_runtime_suspend(device); 801 } 802 803 static int i2c_dw_runtime_resume(struct device *device) 804 { 805 struct dw_i2c_dev *dev = dev_get_drvdata(device); 806 807 if (!dev->shared_with_punit) 808 i2c_dw_prepare_clk(dev, true); 809 810 dev->init(dev); 811 812 return 0; 813 } 814 815 static int i2c_dw_resume(struct device *device) 816 { 817 struct dw_i2c_dev *dev = dev_get_drvdata(device); 818 819 i2c_dw_runtime_resume(device); 820 i2c_mark_adapter_resumed(&dev->adapter); 821 822 return 0; 823 } 824 825 EXPORT_GPL_DEV_PM_OPS(i2c_dw_dev_pm_ops) = { 826 .prepare = pm_sleep_ptr(i2c_dw_prepare), 827 LATE_SYSTEM_SLEEP_PM_OPS(i2c_dw_suspend, i2c_dw_resume) 828 RUNTIME_PM_OPS(i2c_dw_runtime_suspend, i2c_dw_runtime_resume, NULL) 829 }; 830 831 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); 832 MODULE_LICENSE("GPL"); 833