1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * TI DAVINCI I2C adapter driver. 4 * 5 * Copyright (C) 2006 Texas Instruments. 6 * Copyright (C) 2007 MontaVista Software Inc. 7 * 8 * Updated by Vinod & Sudhakar Feb 2005 9 * 10 * ---------------------------------------------------------------------------- 11 * 12 * ---------------------------------------------------------------------------- 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/cpufreq.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/errno.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/i2c.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/property.h> 29 #include <linux/sched.h> 30 #include <linux/slab.h> 31 32 /* ----- global defines ----------------------------------------------- */ 33 34 #define DAVINCI_I2C_TIMEOUT (1*HZ) 35 #define DAVINCI_I2C_MAX_TRIES 2 36 #define DAVINCI_I2C_OWN_ADDRESS 0x08 37 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \ 38 DAVINCI_I2C_IMR_ARDY | \ 39 DAVINCI_I2C_IMR_NACK | \ 40 DAVINCI_I2C_IMR_AL) 41 42 #define DAVINCI_I2C_OAR_REG 0x00 43 #define DAVINCI_I2C_IMR_REG 0x04 44 #define DAVINCI_I2C_STR_REG 0x08 45 #define DAVINCI_I2C_CLKL_REG 0x0c 46 #define DAVINCI_I2C_CLKH_REG 0x10 47 #define DAVINCI_I2C_CNT_REG 0x14 48 #define DAVINCI_I2C_DRR_REG 0x18 49 #define DAVINCI_I2C_SAR_REG 0x1c 50 #define DAVINCI_I2C_DXR_REG 0x20 51 #define DAVINCI_I2C_MDR_REG 0x24 52 #define DAVINCI_I2C_IVR_REG 0x28 53 #define DAVINCI_I2C_EMDR_REG 0x2c 54 #define DAVINCI_I2C_PSC_REG 0x30 55 #define DAVINCI_I2C_FUNC_REG 0x48 56 #define DAVINCI_I2C_DIR_REG 0x4c 57 #define DAVINCI_I2C_DIN_REG 0x50 58 #define DAVINCI_I2C_DOUT_REG 0x54 59 #define DAVINCI_I2C_DSET_REG 0x58 60 #define DAVINCI_I2C_DCLR_REG 0x5c 61 62 #define DAVINCI_I2C_IVR_AAS 0x07 63 #define DAVINCI_I2C_IVR_SCD 0x06 64 #define DAVINCI_I2C_IVR_XRDY 0x05 65 #define DAVINCI_I2C_IVR_RDR 0x04 66 #define DAVINCI_I2C_IVR_ARDY 0x03 67 #define DAVINCI_I2C_IVR_NACK 0x02 68 #define DAVINCI_I2C_IVR_AL 0x01 69 70 #define DAVINCI_I2C_STR_BB BIT(12) 71 #define DAVINCI_I2C_STR_RSFULL BIT(11) 72 #define DAVINCI_I2C_STR_SCD BIT(5) 73 #define DAVINCI_I2C_STR_ARDY BIT(2) 74 #define DAVINCI_I2C_STR_NACK BIT(1) 75 #define DAVINCI_I2C_STR_AL BIT(0) 76 77 #define DAVINCI_I2C_MDR_NACK BIT(15) 78 #define DAVINCI_I2C_MDR_STT BIT(13) 79 #define DAVINCI_I2C_MDR_STP BIT(11) 80 #define DAVINCI_I2C_MDR_MST BIT(10) 81 #define DAVINCI_I2C_MDR_TRX BIT(9) 82 #define DAVINCI_I2C_MDR_XA BIT(8) 83 #define DAVINCI_I2C_MDR_RM BIT(7) 84 #define DAVINCI_I2C_MDR_IRS BIT(5) 85 86 #define DAVINCI_I2C_IMR_AAS BIT(6) 87 #define DAVINCI_I2C_IMR_SCD BIT(5) 88 #define DAVINCI_I2C_IMR_XRDY BIT(4) 89 #define DAVINCI_I2C_IMR_RRDY BIT(3) 90 #define DAVINCI_I2C_IMR_ARDY BIT(2) 91 #define DAVINCI_I2C_IMR_NACK BIT(1) 92 #define DAVINCI_I2C_IMR_AL BIT(0) 93 94 /* set SDA and SCL as GPIO */ 95 #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0) 96 97 /* set SCL as output when used as GPIO*/ 98 #define DAVINCI_I2C_DIR_PDIR0 BIT(0) 99 /* set SDA as output when used as GPIO*/ 100 #define DAVINCI_I2C_DIR_PDIR1 BIT(1) 101 102 /* read SCL GPIO level */ 103 #define DAVINCI_I2C_DIN_PDIN0 BIT(0) 104 /* read SDA GPIO level */ 105 #define DAVINCI_I2C_DIN_PDIN1 BIT(1) 106 107 /*set the SCL GPIO high */ 108 #define DAVINCI_I2C_DSET_PDSET0 BIT(0) 109 /*set the SDA GPIO high */ 110 #define DAVINCI_I2C_DSET_PDSET1 BIT(1) 111 112 /* set the SCL GPIO low */ 113 #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0) 114 /* set the SDA GPIO low */ 115 #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1) 116 117 /* timeout for pm runtime autosuspend */ 118 #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */ 119 120 struct davinci_i2c_dev { 121 struct device *dev; 122 void __iomem *base; 123 struct completion cmd_complete; 124 struct clk *clk; 125 int cmd_err; 126 u8 *buf; 127 size_t buf_len; 128 int irq; 129 int stop; 130 u8 terminate; 131 struct i2c_adapter adapter; 132 #ifdef CONFIG_CPU_FREQ 133 struct notifier_block freq_transition; 134 #endif 135 /* standard bus frequency (kHz) */ 136 unsigned int bus_freq; 137 /* Chip has a ICPFUNC register */ 138 bool has_pfunc; 139 }; 140 141 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, 142 int reg, u16 val) 143 { 144 writew_relaxed(val, i2c_dev->base + reg); 145 } 146 147 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) 148 { 149 return readw_relaxed(i2c_dev->base + reg); 150 } 151 152 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, 153 int val) 154 { 155 u16 w; 156 157 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); 158 if (!val) /* put I2C into reset */ 159 w &= ~DAVINCI_I2C_MDR_IRS; 160 else /* take I2C out of reset */ 161 w |= DAVINCI_I2C_MDR_IRS; 162 163 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); 164 } 165 166 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) 167 { 168 u16 psc; 169 u32 clk; 170 u32 d; 171 u32 clkh; 172 u32 clkl; 173 u32 input_clock = clk_get_rate(dev->clk); 174 175 /* NOTE: I2C Clock divider programming info 176 * As per I2C specs the following formulas provide prescaler 177 * and low/high divider values 178 * input clk --> PSC Div -----------> ICCL/H Div --> output clock 179 * module clk 180 * 181 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] 182 * 183 * Thus, 184 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; 185 * 186 * where if PSC == 0, d = 7, 187 * if PSC == 1, d = 6 188 * if PSC > 1 , d = 5 189 * 190 * Note: 191 * d is always 6 on Keystone I2C controller 192 */ 193 194 /* 195 * Both Davinci and current Keystone User Guides recommend a value 196 * between 7MHz and 12MHz. In reality 7MHz module clock doesn't 197 * always produce enough margin between SDA and SCL transitions. 198 * Measurements show that the higher the module clock is, the 199 * bigger is the margin, providing more reliable communication. 200 * So we better target for 12MHz. 201 */ 202 psc = (input_clock / 12000000) - 1; 203 if ((input_clock / (psc + 1)) > 12000000) 204 psc++; /* better to run under spec than over */ 205 d = (psc >= 2) ? 5 : 7 - psc; 206 207 if (device_is_compatible(dev->dev, "ti,keystone-i2c")) 208 d = 6; 209 210 clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)); 211 /* Avoid driving the bus too fast because of rounding errors above */ 212 if (input_clock / (psc + 1) / clk > dev->bus_freq * 1000) 213 clk++; 214 /* 215 * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at 216 * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH 217 * to LOW ratio as 1 to 2 is more safe. 218 */ 219 if (dev->bus_freq > 100) 220 clkl = (clk << 1) / 3; 221 else 222 clkl = (clk >> 1); 223 /* 224 * It's not always possible to have 1 to 2 ratio when d=7, so fall back 225 * to minimal possible clkh in this case. 226 * 227 * Note: 228 * CLKH is not allowed to be 0, in this case I2C clock is not generated 229 * at all 230 */ 231 if (clk > clkl + d) { 232 clkh = clk - clkl - d; 233 clkl -= d; 234 } else { 235 clkh = 1; 236 clkl = clk - (d << 1); 237 } 238 239 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); 240 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); 241 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); 242 243 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk); 244 } 245 246 /* 247 * This function configures I2C and brings I2C out of reset. 248 * This function is called during I2C init function. This function 249 * also gets called if I2C encounters any errors. 250 */ 251 static int i2c_davinci_init(struct davinci_i2c_dev *dev) 252 { 253 /* put I2C into reset */ 254 davinci_i2c_reset_ctrl(dev, 0); 255 256 /* compute clock dividers */ 257 i2c_davinci_calc_clk_dividers(dev); 258 259 /* Respond at reserved "SMBus Host" target address" (and zero); 260 * we seem to have no option to not respond... 261 */ 262 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS); 263 264 dev_dbg(dev->dev, "PSC = %d\n", 265 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); 266 dev_dbg(dev->dev, "CLKL = %d\n", 267 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); 268 dev_dbg(dev->dev, "CLKH = %d\n", 269 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); 270 dev_dbg(dev->dev, "bus_freq = %dkHz\n", dev->bus_freq); 271 272 273 /* Take the I2C module out of reset: */ 274 davinci_i2c_reset_ctrl(dev, 1); 275 276 /* Enable interrupts */ 277 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); 278 279 return 0; 280 } 281 282 /* 283 * This routine does i2c bus recovery by using i2c_generic_scl_recovery 284 * which is provided by I2C Bus recovery infrastructure. 285 */ 286 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap) 287 { 288 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 289 290 /* Disable interrupts */ 291 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0); 292 293 /* put I2C into reset */ 294 davinci_i2c_reset_ctrl(dev, 0); 295 } 296 297 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap) 298 { 299 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 300 301 i2c_davinci_init(dev); 302 } 303 304 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val) 305 { 306 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 307 308 if (val) 309 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG, 310 DAVINCI_I2C_DSET_PDSET0); 311 else 312 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG, 313 DAVINCI_I2C_DCLR_PDCLR0); 314 } 315 316 static int davinci_i2c_get_scl(struct i2c_adapter *adap) 317 { 318 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 319 int val; 320 321 /* read the state of SCL */ 322 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG); 323 return val & DAVINCI_I2C_DIN_PDIN0; 324 } 325 326 static int davinci_i2c_get_sda(struct i2c_adapter *adap) 327 { 328 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 329 int val; 330 331 /* read the state of SDA */ 332 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG); 333 return val & DAVINCI_I2C_DIN_PDIN1; 334 } 335 336 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap) 337 { 338 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 339 340 davinci_i2c_prepare_recovery(adap); 341 342 /* SCL output, SDA input */ 343 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0); 344 345 /* change to GPIO mode */ 346 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 347 DAVINCI_I2C_FUNC_PFUNC0); 348 } 349 350 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap) 351 { 352 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 353 354 /* change back to I2C mode */ 355 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0); 356 357 davinci_i2c_unprepare_recovery(adap); 358 } 359 360 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = { 361 .recover_bus = i2c_generic_scl_recovery, 362 .set_scl = davinci_i2c_set_scl, 363 .get_scl = davinci_i2c_get_scl, 364 .get_sda = davinci_i2c_get_sda, 365 .prepare_recovery = davinci_i2c_scl_prepare_recovery, 366 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery, 367 }; 368 369 /* 370 * Waiting for bus not busy 371 */ 372 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev) 373 { 374 unsigned long timeout = jiffies + dev->adapter.timeout; 375 376 do { 377 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)) 378 return 0; 379 schedule_timeout_uninterruptible(1); 380 } while (time_before_eq(jiffies, timeout)); 381 382 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 383 i2c_recover_bus(&dev->adapter); 384 385 /* 386 * if bus is still "busy" here, it's most probably a HW problem like 387 * short-circuit 388 */ 389 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB) 390 return -EIO; 391 392 return 0; 393 } 394 395 /* 396 * Low level read/write transaction. This function is called from 397 * i2c_davinci_xfer. 398 */ 399 static int 400 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) 401 { 402 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 403 u32 flag; 404 u16 w; 405 unsigned long time_left; 406 407 if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) { 408 dev_warn(dev->dev, "transfer to own address aborted\n"); 409 return -EADDRNOTAVAIL; 410 } 411 412 /* set the target address */ 413 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); 414 415 dev->buf = msg->buf; 416 dev->buf_len = msg->len; 417 dev->stop = stop; 418 419 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); 420 421 reinit_completion(&dev->cmd_complete); 422 dev->cmd_err = 0; 423 424 /* Take I2C out of reset and configure it as controller */ 425 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; 426 427 if (msg->flags & I2C_M_TEN) 428 flag |= DAVINCI_I2C_MDR_XA; 429 if (!(msg->flags & I2C_M_RD)) 430 flag |= DAVINCI_I2C_MDR_TRX; 431 if (msg->len == 0) 432 flag |= DAVINCI_I2C_MDR_RM; 433 434 /* Enable receive or transmit interrupts */ 435 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); 436 if (msg->flags & I2C_M_RD) 437 w |= DAVINCI_I2C_IMR_RRDY; 438 else 439 w |= DAVINCI_I2C_IMR_XRDY; 440 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); 441 442 dev->terminate = 0; 443 444 /* 445 * Write mode register first as needed for correct behaviour 446 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY 447 * occurring before we have loaded DXR 448 */ 449 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 450 451 /* 452 * First byte should be set here, not after interrupt, 453 * because transmit-data-ready interrupt can come before 454 * NACK-interrupt during sending of previous message and 455 * ICDXR may have wrong data 456 * It also saves us one interrupt, slightly faster 457 */ 458 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) { 459 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); 460 dev->buf_len--; 461 } 462 463 /* Set STT to begin transmit now DXR is loaded */ 464 flag |= DAVINCI_I2C_MDR_STT; 465 if (stop && msg->len != 0) 466 flag |= DAVINCI_I2C_MDR_STP; 467 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 468 469 time_left = wait_for_completion_timeout(&dev->cmd_complete, 470 dev->adapter.timeout); 471 if (!time_left) { 472 i2c_recover_bus(adap); 473 dev->buf_len = 0; 474 return -ETIMEDOUT; 475 } 476 if (dev->buf_len) { 477 /* This should be 0 if all bytes were transferred 478 * or dev->cmd_err denotes an error. 479 */ 480 dev_err(dev->dev, "abnormal termination buf_len=%zu\n", 481 dev->buf_len); 482 dev->terminate = 1; 483 wmb(); 484 dev->buf_len = 0; 485 return -EREMOTEIO; 486 } 487 488 /* no error */ 489 if (likely(!dev->cmd_err)) 490 return msg->len; 491 492 /* We have an error */ 493 if (dev->cmd_err & DAVINCI_I2C_STR_AL) { 494 i2c_davinci_init(dev); 495 return -EIO; 496 } 497 498 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) { 499 if (msg->flags & I2C_M_IGNORE_NAK) 500 return msg->len; 501 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 502 w |= DAVINCI_I2C_MDR_STP; 503 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 504 return -EREMOTEIO; 505 } 506 return -EIO; 507 } 508 509 /* 510 * Prepare controller for a transaction and call i2c_davinci_xfer_msg 511 */ 512 static int 513 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 514 { 515 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 516 int i; 517 int ret; 518 519 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 520 521 ret = pm_runtime_resume_and_get(dev->dev); 522 if (ret < 0) { 523 dev_err(dev->dev, "Failed to runtime_get device: %d\n", ret); 524 return ret; 525 } 526 527 ret = i2c_davinci_wait_bus_not_busy(dev); 528 if (ret < 0) { 529 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 530 goto out; 531 } 532 533 for (i = 0; i < num; i++) { 534 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1))); 535 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num, 536 ret); 537 if (ret < 0) 538 goto out; 539 } 540 541 ret = num; 542 543 out: 544 pm_runtime_put_autosuspend(dev->dev); 545 546 return ret; 547 } 548 549 static u32 i2c_davinci_func(struct i2c_adapter *adap) 550 { 551 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 552 I2C_FUNC_PROTOCOL_MANGLING; 553 } 554 555 static void terminate_read(struct davinci_i2c_dev *dev) 556 { 557 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 558 w |= DAVINCI_I2C_MDR_NACK; 559 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 560 561 /* Throw away data */ 562 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); 563 if (!dev->terminate) 564 dev_err(dev->dev, "RDR IRQ while no data requested\n"); 565 } 566 static void terminate_write(struct davinci_i2c_dev *dev) 567 { 568 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 569 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; 570 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 571 572 if (!dev->terminate) 573 dev_dbg(dev->dev, "TDR IRQ while no data to send\n"); 574 } 575 576 /* 577 * Interrupt service routine. This gets called whenever an I2C interrupt 578 * occurs. 579 */ 580 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id) 581 { 582 struct davinci_i2c_dev *dev = dev_id; 583 u32 stat; 584 int count = 0; 585 u16 w; 586 587 if (pm_runtime_suspended(dev->dev)) 588 return IRQ_NONE; 589 590 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { 591 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); 592 if (count++ == 100) { 593 dev_warn(dev->dev, "Too much work in one IRQ\n"); 594 break; 595 } 596 597 switch (stat) { 598 case DAVINCI_I2C_IVR_AL: 599 /* Arbitration lost, must retry */ 600 dev->cmd_err |= DAVINCI_I2C_STR_AL; 601 dev->buf_len = 0; 602 complete(&dev->cmd_complete); 603 break; 604 605 case DAVINCI_I2C_IVR_NACK: 606 dev->cmd_err |= DAVINCI_I2C_STR_NACK; 607 dev->buf_len = 0; 608 complete(&dev->cmd_complete); 609 break; 610 611 case DAVINCI_I2C_IVR_ARDY: 612 davinci_i2c_write_reg(dev, 613 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); 614 if (((dev->buf_len == 0) && (dev->stop != 0)) || 615 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { 616 w = davinci_i2c_read_reg(dev, 617 DAVINCI_I2C_MDR_REG); 618 w |= DAVINCI_I2C_MDR_STP; 619 davinci_i2c_write_reg(dev, 620 DAVINCI_I2C_MDR_REG, w); 621 } 622 complete(&dev->cmd_complete); 623 break; 624 625 case DAVINCI_I2C_IVR_RDR: 626 if (dev->buf_len) { 627 *dev->buf++ = 628 davinci_i2c_read_reg(dev, 629 DAVINCI_I2C_DRR_REG); 630 dev->buf_len--; 631 if (dev->buf_len) 632 continue; 633 634 davinci_i2c_write_reg(dev, 635 DAVINCI_I2C_STR_REG, 636 DAVINCI_I2C_IMR_RRDY); 637 } else { 638 /* signal can terminate transfer */ 639 terminate_read(dev); 640 } 641 break; 642 643 case DAVINCI_I2C_IVR_XRDY: 644 if (dev->buf_len) { 645 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, 646 *dev->buf++); 647 dev->buf_len--; 648 if (dev->buf_len) 649 continue; 650 651 w = davinci_i2c_read_reg(dev, 652 DAVINCI_I2C_IMR_REG); 653 w &= ~DAVINCI_I2C_IMR_XRDY; 654 davinci_i2c_write_reg(dev, 655 DAVINCI_I2C_IMR_REG, 656 w); 657 } else { 658 /* signal can terminate transfer */ 659 terminate_write(dev); 660 } 661 break; 662 663 case DAVINCI_I2C_IVR_SCD: 664 davinci_i2c_write_reg(dev, 665 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); 666 complete(&dev->cmd_complete); 667 break; 668 669 case DAVINCI_I2C_IVR_AAS: 670 dev_dbg(dev->dev, "Address as target interrupt\n"); 671 break; 672 673 default: 674 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat); 675 break; 676 } 677 } 678 679 return count ? IRQ_HANDLED : IRQ_NONE; 680 } 681 682 #ifdef CONFIG_CPU_FREQ 683 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb, 684 unsigned long val, void *data) 685 { 686 struct davinci_i2c_dev *dev; 687 688 dev = container_of(nb, struct davinci_i2c_dev, freq_transition); 689 690 i2c_lock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER); 691 if (val == CPUFREQ_PRECHANGE) { 692 davinci_i2c_reset_ctrl(dev, 0); 693 } else if (val == CPUFREQ_POSTCHANGE) { 694 i2c_davinci_calc_clk_dividers(dev); 695 davinci_i2c_reset_ctrl(dev, 1); 696 } 697 i2c_unlock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER); 698 699 return 0; 700 } 701 702 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) 703 { 704 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition; 705 706 return cpufreq_register_notifier(&dev->freq_transition, 707 CPUFREQ_TRANSITION_NOTIFIER); 708 } 709 710 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) 711 { 712 cpufreq_unregister_notifier(&dev->freq_transition, 713 CPUFREQ_TRANSITION_NOTIFIER); 714 } 715 #else 716 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) 717 { 718 return 0; 719 } 720 721 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) 722 { 723 } 724 #endif 725 726 static const struct i2c_algorithm i2c_davinci_algo = { 727 .xfer = i2c_davinci_xfer, 728 .functionality = i2c_davinci_func, 729 }; 730 731 static const struct of_device_id davinci_i2c_of_match[] = { 732 {.compatible = "ti,davinci-i2c", }, 733 {.compatible = "ti,keystone-i2c", }, 734 {}, 735 }; 736 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match); 737 738 static int davinci_i2c_probe(struct platform_device *pdev) 739 { 740 struct davinci_i2c_dev *dev; 741 struct i2c_adapter *adap; 742 int r, irq; 743 u32 prop; 744 745 irq = platform_get_irq(pdev, 0); 746 if (irq < 0) 747 return irq; 748 749 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 750 if (!dev) 751 return -ENOMEM; 752 753 init_completion(&dev->cmd_complete); 754 755 dev->dev = &pdev->dev; 756 dev->irq = irq; 757 platform_set_drvdata(pdev, dev); 758 759 r = device_property_read_u32(&pdev->dev, "clock-frequency", &prop); 760 if (r) 761 prop = I2C_MAX_STANDARD_MODE_FREQ; 762 763 dev->bus_freq = prop / 1000; 764 765 dev->has_pfunc = device_property_present(&pdev->dev, "ti,has-pfunc"); 766 767 dev->clk = devm_clk_get(&pdev->dev, NULL); 768 if (IS_ERR(dev->clk)) 769 return PTR_ERR(dev->clk); 770 771 dev->base = devm_platform_ioremap_resource(pdev, 0); 772 if (IS_ERR(dev->base)) { 773 return PTR_ERR(dev->base); 774 } 775 776 pm_runtime_set_autosuspend_delay(dev->dev, 777 DAVINCI_I2C_PM_TIMEOUT); 778 pm_runtime_use_autosuspend(dev->dev); 779 780 pm_runtime_enable(dev->dev); 781 782 r = pm_runtime_resume_and_get(dev->dev); 783 if (r < 0) { 784 dev_err(dev->dev, "failed to runtime_get device: %d\n", r); 785 goto err_pm; 786 } 787 788 i2c_davinci_init(dev); 789 790 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0, 791 pdev->name, dev); 792 if (r) { 793 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); 794 goto err_unuse_clocks; 795 } 796 797 r = i2c_davinci_cpufreq_register(dev); 798 if (r) { 799 dev_err(&pdev->dev, "failed to register cpufreq\n"); 800 goto err_unuse_clocks; 801 } 802 803 adap = &dev->adapter; 804 i2c_set_adapdata(adap, dev); 805 adap->owner = THIS_MODULE; 806 adap->class = I2C_CLASS_DEPRECATED; 807 strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); 808 adap->algo = &i2c_davinci_algo; 809 adap->dev.parent = &pdev->dev; 810 adap->timeout = DAVINCI_I2C_TIMEOUT; 811 adap->dev.of_node = dev_of_node(&pdev->dev); 812 813 if (dev->has_pfunc) 814 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info; 815 816 adap->nr = pdev->id; 817 r = i2c_add_numbered_adapter(adap); 818 if (r) 819 goto err_cpufreq; 820 821 pm_runtime_put_autosuspend(dev->dev); 822 823 return 0; 824 825 err_cpufreq: 826 i2c_davinci_cpufreq_deregister(dev); 827 err_unuse_clocks: 828 pm_runtime_dont_use_autosuspend(dev->dev); 829 pm_runtime_put_sync(dev->dev); 830 err_pm: 831 pm_runtime_disable(dev->dev); 832 833 return r; 834 } 835 836 static void davinci_i2c_remove(struct platform_device *pdev) 837 { 838 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev); 839 int ret; 840 841 i2c_davinci_cpufreq_deregister(dev); 842 843 i2c_del_adapter(&dev->adapter); 844 845 ret = pm_runtime_get_sync(&pdev->dev); 846 if (ret < 0) 847 dev_err(&pdev->dev, "Failed to resume device\n"); 848 else 849 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0); 850 851 pm_runtime_dont_use_autosuspend(dev->dev); 852 pm_runtime_put_sync(dev->dev); 853 pm_runtime_disable(dev->dev); 854 } 855 856 static int davinci_i2c_suspend(struct device *dev) 857 { 858 struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev); 859 860 /* put I2C into reset */ 861 davinci_i2c_reset_ctrl(i2c_dev, 0); 862 863 return 0; 864 } 865 866 static int davinci_i2c_resume(struct device *dev) 867 { 868 struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev); 869 870 /* take I2C out of reset */ 871 davinci_i2c_reset_ctrl(i2c_dev, 1); 872 873 return 0; 874 } 875 876 static const struct dev_pm_ops davinci_i2c_pm = { 877 .suspend = davinci_i2c_suspend, 878 .resume = davinci_i2c_resume, 879 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 880 pm_runtime_force_resume) 881 }; 882 883 static const struct platform_device_id davinci_i2c_driver_ids[] = { 884 { .name = "i2c_davinci", }, 885 { /* sentinel */ } 886 }; 887 MODULE_DEVICE_TABLE(platform, davinci_i2c_driver_ids); 888 889 static struct platform_driver davinci_i2c_driver = { 890 .probe = davinci_i2c_probe, 891 .remove = davinci_i2c_remove, 892 .id_table = davinci_i2c_driver_ids, 893 .driver = { 894 .name = "i2c_davinci", 895 .pm = pm_sleep_ptr(&davinci_i2c_pm), 896 .of_match_table = davinci_i2c_of_match, 897 }, 898 }; 899 900 /* I2C may be needed to bring up other drivers */ 901 static int __init davinci_i2c_init_driver(void) 902 { 903 return platform_driver_register(&davinci_i2c_driver); 904 } 905 subsys_initcall(davinci_i2c_init_driver); 906 907 static void __exit davinci_i2c_exit_driver(void) 908 { 909 platform_driver_unregister(&davinci_i2c_driver); 910 } 911 module_exit(davinci_i2c_exit_driver); 912 913 MODULE_AUTHOR("Texas Instruments India"); 914 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter"); 915 MODULE_LICENSE("GPL"); 916