1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Intel CHT Whiskey Cove PMIC I2C Master driver 4 * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com> 5 * 6 * Based on various non upstream patches to support the CHT Whiskey Cove PMIC: 7 * Copyright (C) 2011 - 2014 Intel Corporation. All rights reserved. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/completion.h> 12 #include <linux/delay.h> 13 #include <linux/i2c.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/intel_soc_pmic.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/power/bq24190_charger.h> 21 #include <linux/slab.h> 22 23 #define CHT_WC_I2C_CTRL 0x5e24 24 #define CHT_WC_I2C_CTRL_WR BIT(0) 25 #define CHT_WC_I2C_CTRL_RD BIT(1) 26 #define CHT_WC_I2C_CLIENT_ADDR 0x5e25 27 #define CHT_WC_I2C_REG_OFFSET 0x5e26 28 #define CHT_WC_I2C_WRDATA 0x5e27 29 #define CHT_WC_I2C_RDDATA 0x5e28 30 31 #define CHT_WC_EXTCHGRIRQ 0x6e0a 32 #define CHT_WC_EXTCHGRIRQ_CLIENT_IRQ BIT(0) 33 #define CHT_WC_EXTCHGRIRQ_WRITE_IRQ BIT(1) 34 #define CHT_WC_EXTCHGRIRQ_READ_IRQ BIT(2) 35 #define CHT_WC_EXTCHGRIRQ_NACK_IRQ BIT(3) 36 #define CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK ((u8)GENMASK(3, 1)) 37 #define CHT_WC_EXTCHGRIRQ_MSK 0x6e17 38 39 struct cht_wc_i2c_adap { 40 struct i2c_adapter adapter; 41 wait_queue_head_t wait; 42 struct irq_chip irqchip; 43 struct mutex adap_lock; 44 struct mutex irqchip_lock; 45 struct regmap *regmap; 46 struct irq_domain *irq_domain; 47 struct i2c_client *client; 48 int client_irq; 49 u8 irq_mask; 50 u8 old_irq_mask; 51 int read_data; 52 bool io_error; 53 bool done; 54 }; 55 56 static irqreturn_t cht_wc_i2c_adap_thread_handler(int id, void *data) 57 { 58 struct cht_wc_i2c_adap *adap = data; 59 int ret, reg; 60 61 mutex_lock(&adap->adap_lock); 62 63 /* Read IRQs */ 64 ret = regmap_read(adap->regmap, CHT_WC_EXTCHGRIRQ, ®); 65 if (ret) { 66 dev_err(&adap->adapter.dev, "Error reading extchgrirq reg\n"); 67 mutex_unlock(&adap->adap_lock); 68 return IRQ_NONE; 69 } 70 71 reg &= ~adap->irq_mask; 72 73 /* Reads must be acked after reading the received data. */ 74 ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, &adap->read_data); 75 if (ret) 76 adap->io_error = true; 77 78 /* 79 * Immediately ack IRQs, so that if new IRQs arrives while we're 80 * handling the previous ones our irq will re-trigger when we're done. 81 */ 82 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, reg); 83 if (ret) 84 dev_err(&adap->adapter.dev, "Error writing extchgrirq reg\n"); 85 86 if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) { 87 adap->io_error |= !!(reg & CHT_WC_EXTCHGRIRQ_NACK_IRQ); 88 adap->done = true; 89 } 90 91 mutex_unlock(&adap->adap_lock); 92 93 if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) 94 wake_up(&adap->wait); 95 96 /* 97 * Do NOT use handle_nested_irq here, the client irq handler will 98 * likely want to do i2c transfers and the i2c controller uses this 99 * interrupt handler as well, so running the client irq handler from 100 * this thread will cause things to lock up. 101 */ 102 if (reg & CHT_WC_EXTCHGRIRQ_CLIENT_IRQ) { 103 /* 104 * generic_handle_irq expects local IRQs to be disabled 105 * as normally it is called from interrupt context. 106 */ 107 local_irq_disable(); 108 generic_handle_irq(adap->client_irq); 109 local_irq_enable(); 110 } 111 112 return IRQ_HANDLED; 113 } 114 115 static u32 cht_wc_i2c_adap_master_func(struct i2c_adapter *adap) 116 { 117 /* This i2c adapter only supports SMBUS byte transfers */ 118 return I2C_FUNC_SMBUS_BYTE_DATA; 119 } 120 121 static int cht_wc_i2c_adap_smbus_xfer(struct i2c_adapter *_adap, u16 addr, 122 unsigned short flags, char read_write, 123 u8 command, int size, 124 union i2c_smbus_data *data) 125 { 126 struct cht_wc_i2c_adap *adap = i2c_get_adapdata(_adap); 127 int ret; 128 129 mutex_lock(&adap->adap_lock); 130 adap->io_error = false; 131 adap->done = false; 132 mutex_unlock(&adap->adap_lock); 133 134 ret = regmap_write(adap->regmap, CHT_WC_I2C_CLIENT_ADDR, addr); 135 if (ret) 136 return ret; 137 138 if (read_write == I2C_SMBUS_WRITE) { 139 ret = regmap_write(adap->regmap, CHT_WC_I2C_WRDATA, data->byte); 140 if (ret) 141 return ret; 142 } 143 144 ret = regmap_write(adap->regmap, CHT_WC_I2C_REG_OFFSET, command); 145 if (ret) 146 return ret; 147 148 ret = regmap_write(adap->regmap, CHT_WC_I2C_CTRL, 149 (read_write == I2C_SMBUS_WRITE) ? 150 CHT_WC_I2C_CTRL_WR : CHT_WC_I2C_CTRL_RD); 151 if (ret) 152 return ret; 153 154 ret = wait_event_timeout(adap->wait, adap->done, msecs_to_jiffies(30)); 155 if (ret == 0) { 156 /* 157 * The CHT GPIO controller serializes all IRQs, sometimes 158 * causing significant delays, check status manually. 159 */ 160 cht_wc_i2c_adap_thread_handler(0, adap); 161 if (!adap->done) 162 return -ETIMEDOUT; 163 } 164 165 ret = 0; 166 mutex_lock(&adap->adap_lock); 167 if (adap->io_error) 168 ret = -EIO; 169 else if (read_write == I2C_SMBUS_READ) 170 data->byte = adap->read_data; 171 mutex_unlock(&adap->adap_lock); 172 173 return ret; 174 } 175 176 static const struct i2c_algorithm cht_wc_i2c_adap_algo = { 177 .functionality = cht_wc_i2c_adap_master_func, 178 .smbus_xfer = cht_wc_i2c_adap_smbus_xfer, 179 }; 180 181 /**** irqchip for the client connected to the extchgr i2c adapter ****/ 182 static void cht_wc_i2c_irq_lock(struct irq_data *data) 183 { 184 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 185 186 mutex_lock(&adap->irqchip_lock); 187 } 188 189 static void cht_wc_i2c_irq_sync_unlock(struct irq_data *data) 190 { 191 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 192 int ret; 193 194 if (adap->irq_mask != adap->old_irq_mask) { 195 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, 196 adap->irq_mask); 197 if (ret == 0) 198 adap->old_irq_mask = adap->irq_mask; 199 else 200 dev_err(&adap->adapter.dev, "Error writing EXTCHGRIRQ_MSK\n"); 201 } 202 203 mutex_unlock(&adap->irqchip_lock); 204 } 205 206 static void cht_wc_i2c_irq_enable(struct irq_data *data) 207 { 208 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 209 210 adap->irq_mask &= ~CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; 211 } 212 213 static void cht_wc_i2c_irq_disable(struct irq_data *data) 214 { 215 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 216 217 adap->irq_mask |= CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; 218 } 219 220 static const struct irq_chip cht_wc_i2c_irq_chip = { 221 .irq_bus_lock = cht_wc_i2c_irq_lock, 222 .irq_bus_sync_unlock = cht_wc_i2c_irq_sync_unlock, 223 .irq_disable = cht_wc_i2c_irq_disable, 224 .irq_enable = cht_wc_i2c_irq_enable, 225 .name = "cht_wc_ext_chrg_irq_chip", 226 }; 227 228 static const char * const bq24190_suppliers[] = { 229 "tcpm-source-psy-i2c-fusb302" }; 230 231 static const struct property_entry bq24190_props[] = { 232 PROPERTY_ENTRY_STRING_ARRAY("supplied-from", bq24190_suppliers), 233 PROPERTY_ENTRY_BOOL("omit-battery-class"), 234 PROPERTY_ENTRY_BOOL("disable-reset"), 235 { } 236 }; 237 238 static struct regulator_consumer_supply fusb302_consumer = { 239 .supply = "vbus", 240 /* Must match fusb302 dev_name in intel_cht_int33fe.c */ 241 .dev_name = "i2c-fusb302", 242 }; 243 244 static const struct regulator_init_data bq24190_vbus_init_data = { 245 .constraints = { 246 /* The name is used in intel_cht_int33fe.c do not change. */ 247 .name = "cht_wc_usb_typec_vbus", 248 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 249 }, 250 .consumer_supplies = &fusb302_consumer, 251 .num_consumer_supplies = 1, 252 }; 253 254 static struct bq24190_platform_data bq24190_pdata = { 255 .regulator_init_data = &bq24190_vbus_init_data, 256 }; 257 258 static int cht_wc_i2c_adap_i2c_probe(struct platform_device *pdev) 259 { 260 struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent); 261 struct cht_wc_i2c_adap *adap; 262 struct i2c_board_info board_info = { 263 .type = "bq24190", 264 .addr = 0x6b, 265 .dev_name = "bq24190", 266 .properties = bq24190_props, 267 .platform_data = &bq24190_pdata, 268 }; 269 int ret, reg, irq; 270 271 irq = platform_get_irq(pdev, 0); 272 if (irq < 0) { 273 dev_err(&pdev->dev, "Error missing irq resource\n"); 274 return -EINVAL; 275 } 276 277 adap = devm_kzalloc(&pdev->dev, sizeof(*adap), GFP_KERNEL); 278 if (!adap) 279 return -ENOMEM; 280 281 init_waitqueue_head(&adap->wait); 282 mutex_init(&adap->adap_lock); 283 mutex_init(&adap->irqchip_lock); 284 adap->irqchip = cht_wc_i2c_irq_chip; 285 adap->regmap = pmic->regmap; 286 adap->adapter.owner = THIS_MODULE; 287 adap->adapter.class = I2C_CLASS_HWMON; 288 adap->adapter.algo = &cht_wc_i2c_adap_algo; 289 strlcpy(adap->adapter.name, "PMIC I2C Adapter", 290 sizeof(adap->adapter.name)); 291 adap->adapter.dev.parent = &pdev->dev; 292 293 /* Clear and activate i2c-adapter interrupts, disable client IRQ */ 294 adap->old_irq_mask = adap->irq_mask = ~CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK; 295 296 ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, ®); 297 if (ret) 298 return ret; 299 300 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, ~adap->irq_mask); 301 if (ret) 302 return ret; 303 304 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, adap->irq_mask); 305 if (ret) 306 return ret; 307 308 /* Alloc and register client IRQ */ 309 adap->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 1, 310 &irq_domain_simple_ops, NULL); 311 if (!adap->irq_domain) 312 return -ENOMEM; 313 314 adap->client_irq = irq_create_mapping(adap->irq_domain, 0); 315 if (!adap->client_irq) { 316 ret = -ENOMEM; 317 goto remove_irq_domain; 318 } 319 320 irq_set_chip_data(adap->client_irq, adap); 321 irq_set_chip_and_handler(adap->client_irq, &adap->irqchip, 322 handle_simple_irq); 323 324 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 325 cht_wc_i2c_adap_thread_handler, 326 IRQF_ONESHOT, "PMIC I2C Adapter", adap); 327 if (ret) 328 goto remove_irq_domain; 329 330 i2c_set_adapdata(&adap->adapter, adap); 331 ret = i2c_add_adapter(&adap->adapter); 332 if (ret) 333 goto remove_irq_domain; 334 335 /* 336 * Normally the Whiskey Cove PMIC is paired with a TI bq24292i charger, 337 * connected to this i2c bus, and a max17047 fuel-gauge and a fusb302 338 * USB Type-C controller connected to another i2c bus. In this setup 339 * the max17047 and fusb302 devices are enumerated through an INT33FE 340 * ACPI device. If this device is present register an i2c-client for 341 * the TI bq24292i charger. 342 */ 343 if (acpi_dev_present("INT33FE", NULL, -1)) { 344 board_info.irq = adap->client_irq; 345 adap->client = i2c_new_device(&adap->adapter, &board_info); 346 if (!adap->client) { 347 ret = -ENOMEM; 348 goto del_adapter; 349 } 350 } 351 352 platform_set_drvdata(pdev, adap); 353 return 0; 354 355 del_adapter: 356 i2c_del_adapter(&adap->adapter); 357 remove_irq_domain: 358 irq_domain_remove(adap->irq_domain); 359 return ret; 360 } 361 362 static int cht_wc_i2c_adap_i2c_remove(struct platform_device *pdev) 363 { 364 struct cht_wc_i2c_adap *adap = platform_get_drvdata(pdev); 365 366 if (adap->client) 367 i2c_unregister_device(adap->client); 368 i2c_del_adapter(&adap->adapter); 369 irq_domain_remove(adap->irq_domain); 370 371 return 0; 372 } 373 374 static const struct platform_device_id cht_wc_i2c_adap_id_table[] = { 375 { .name = "cht_wcove_ext_chgr" }, 376 {}, 377 }; 378 MODULE_DEVICE_TABLE(platform, cht_wc_i2c_adap_id_table); 379 380 static struct platform_driver cht_wc_i2c_adap_driver = { 381 .probe = cht_wc_i2c_adap_i2c_probe, 382 .remove = cht_wc_i2c_adap_i2c_remove, 383 .driver = { 384 .name = "cht_wcove_ext_chgr", 385 }, 386 .id_table = cht_wc_i2c_adap_id_table, 387 }; 388 module_platform_driver(cht_wc_i2c_adap_driver); 389 390 MODULE_DESCRIPTION("Intel CHT Whiskey Cove PMIC I2C Master driver"); 391 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 392 MODULE_LICENSE("GPL"); 393