1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * I2C bus driver for the Cadence I2C controller. 4 * 5 * Copyright (C) 2009 - 2014 Xilinx, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/of.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/reset.h> 20 21 /* Register offsets for the I2C device. */ 22 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */ 23 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */ 24 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */ 25 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */ 26 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */ 27 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */ 28 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */ 29 #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */ 30 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */ 31 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */ 32 33 /* Control Register Bit mask definitions */ 34 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */ 35 #define CDNS_I2C_CR_ACK_EN BIT(3) 36 #define CDNS_I2C_CR_NEA BIT(2) 37 #define CDNS_I2C_CR_MS BIT(1) 38 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */ 39 #define CDNS_I2C_CR_RW BIT(0) 40 /* 1 = Auto init FIFO to zeroes */ 41 #define CDNS_I2C_CR_CLR_FIFO BIT(6) 42 #define CDNS_I2C_CR_DIVA_SHIFT 14 43 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT) 44 #define CDNS_I2C_CR_DIVB_SHIFT 8 45 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT) 46 47 #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \ 48 CDNS_I2C_CR_ACK_EN | \ 49 CDNS_I2C_CR_MS) 50 51 #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK 52 53 /* Status Register Bit mask definitions */ 54 #define CDNS_I2C_SR_BA BIT(8) 55 #define CDNS_I2C_SR_TXDV BIT(6) 56 #define CDNS_I2C_SR_RXDV BIT(5) 57 #define CDNS_I2C_SR_RXRW BIT(3) 58 59 /* 60 * I2C Address Register Bit mask definitions 61 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0] 62 * bits. A write access to this register always initiates a transfer if the I2C 63 * is in master mode. 64 */ 65 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */ 66 67 /* 68 * I2C Interrupt Registers Bit mask definitions 69 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 70 * bit definitions. 71 */ 72 #define CDNS_I2C_IXR_ARB_LOST BIT(9) 73 #define CDNS_I2C_IXR_RX_UNF BIT(7) 74 #define CDNS_I2C_IXR_TX_OVF BIT(6) 75 #define CDNS_I2C_IXR_RX_OVF BIT(5) 76 #define CDNS_I2C_IXR_SLV_RDY BIT(4) 77 #define CDNS_I2C_IXR_TO BIT(3) 78 #define CDNS_I2C_IXR_NACK BIT(2) 79 #define CDNS_I2C_IXR_DATA BIT(1) 80 #define CDNS_I2C_IXR_COMP BIT(0) 81 82 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 83 CDNS_I2C_IXR_RX_UNF | \ 84 CDNS_I2C_IXR_TX_OVF | \ 85 CDNS_I2C_IXR_RX_OVF | \ 86 CDNS_I2C_IXR_SLV_RDY | \ 87 CDNS_I2C_IXR_TO | \ 88 CDNS_I2C_IXR_NACK | \ 89 CDNS_I2C_IXR_DATA | \ 90 CDNS_I2C_IXR_COMP) 91 92 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 93 CDNS_I2C_IXR_RX_UNF | \ 94 CDNS_I2C_IXR_TX_OVF | \ 95 CDNS_I2C_IXR_RX_OVF | \ 96 CDNS_I2C_IXR_NACK) 97 98 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 99 CDNS_I2C_IXR_RX_UNF | \ 100 CDNS_I2C_IXR_TX_OVF | \ 101 CDNS_I2C_IXR_RX_OVF | \ 102 CDNS_I2C_IXR_NACK | \ 103 CDNS_I2C_IXR_DATA | \ 104 CDNS_I2C_IXR_COMP) 105 106 #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \ 107 CDNS_I2C_IXR_TX_OVF | \ 108 CDNS_I2C_IXR_RX_OVF | \ 109 CDNS_I2C_IXR_TO | \ 110 CDNS_I2C_IXR_NACK | \ 111 CDNS_I2C_IXR_DATA | \ 112 CDNS_I2C_IXR_COMP) 113 114 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000) 115 /* timeout for pm runtime autosuspend */ 116 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */ 117 118 #define CDNS_I2C_FIFO_DEPTH_DEFAULT 16 119 #define CDNS_I2C_MAX_TRANSFER_SIZE 255 120 /* Transfer size in multiples of data interrupt depth */ 121 #define CDNS_I2C_TRANSFER_SIZE(max) ((max) - 3) 122 123 #define DRIVER_NAME "cdns-i2c" 124 125 #define CDNS_I2C_DIVA_MAX 4 126 #define CDNS_I2C_DIVB_MAX 64 127 128 #define CDNS_I2C_TIMEOUT_MAX 0xFF 129 130 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) 131 #define CDNS_I2C_POLL_US 100000 132 #define CDNS_I2C_POLL_US_ATOMIC 10 133 #define CDNS_I2C_TIMEOUT_US 500000 134 135 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset) 136 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset) 137 138 #if IS_ENABLED(CONFIG_I2C_SLAVE) 139 /** 140 * enum cdns_i2c_mode - I2C Controller current operating mode 141 * 142 * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode 143 * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode 144 */ 145 enum cdns_i2c_mode { 146 CDNS_I2C_MODE_SLAVE, 147 CDNS_I2C_MODE_MASTER, 148 }; 149 150 /** 151 * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode 152 * 153 * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle 154 * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master 155 * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master 156 */ 157 enum cdns_i2c_slave_state { 158 CDNS_I2C_SLAVE_STATE_IDLE, 159 CDNS_I2C_SLAVE_STATE_SEND, 160 CDNS_I2C_SLAVE_STATE_RECV, 161 }; 162 #endif 163 164 /** 165 * struct cdns_i2c - I2C device private data structure 166 * 167 * @dev: Pointer to device structure 168 * @membase: Base address of the I2C device 169 * @adap: I2C adapter instance 170 * @p_msg: Message pointer 171 * @err_status: Error status in Interrupt Status Register 172 * @xfer_done: Transfer complete status 173 * @p_send_buf: Pointer to transmit buffer 174 * @p_recv_buf: Pointer to receive buffer 175 * @send_count: Number of bytes still expected to send 176 * @recv_count: Number of bytes still expected to receive 177 * @curr_recv_count: Number of bytes to be received in current transfer 178 * @input_clk: Input clock to I2C controller 179 * @i2c_clk: Maximum I2C clock speed 180 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit 181 * @clk: Pointer to struct clk 182 * @clk_rate_change_nb: Notifier block for clock rate changes 183 * @reset: Reset control for the device 184 * @quirks: flag for broken hold bit usage in r1p10 185 * @ctrl_reg: Cached value of the control register. 186 * @rinfo: I2C GPIO recovery information 187 * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register 188 * @slave: Registered slave instance. 189 * @dev_mode: I2C operating role(master/slave). 190 * @slave_state: I2C Slave state(idle/read/write). 191 * @fifo_depth: The depth of the transfer FIFO 192 * @transfer_size: The maximum number of bytes in one transfer 193 * @atomic: Mode of transfer 194 * @err_status_atomic: Error status in atomic mode 195 */ 196 struct cdns_i2c { 197 struct device *dev; 198 void __iomem *membase; 199 struct i2c_adapter adap; 200 struct i2c_msg *p_msg; 201 int err_status; 202 struct completion xfer_done; 203 unsigned char *p_send_buf; 204 unsigned char *p_recv_buf; 205 unsigned int send_count; 206 unsigned int recv_count; 207 unsigned int curr_recv_count; 208 unsigned long input_clk; 209 unsigned int i2c_clk; 210 unsigned int bus_hold_flag; 211 struct clk *clk; 212 struct notifier_block clk_rate_change_nb; 213 struct reset_control *reset; 214 u32 quirks; 215 u32 ctrl_reg; 216 struct i2c_bus_recovery_info rinfo; 217 #if IS_ENABLED(CONFIG_I2C_SLAVE) 218 u16 ctrl_reg_diva_divb; 219 struct i2c_client *slave; 220 enum cdns_i2c_mode dev_mode; 221 enum cdns_i2c_slave_state slave_state; 222 #endif 223 u32 fifo_depth; 224 unsigned int transfer_size; 225 bool atomic; 226 int err_status_atomic; 227 }; 228 229 struct cdns_platform_data { 230 u32 quirks; 231 }; 232 233 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \ 234 clk_rate_change_nb) 235 236 /** 237 * cdns_i2c_init - Controller initialisation 238 * @id: Device private data structure 239 * 240 * Initialise the i2c controller. 241 * 242 */ 243 static void cdns_i2c_init(struct cdns_i2c *id) 244 { 245 cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET); 246 /* 247 * Cadence I2C controller has a bug wherein it generates 248 * invalid read transaction after HW timeout in master receiver mode. 249 * HW timeout is not used by this driver and the interrupt is disabled. 250 * But the feature itself cannot be disabled. Hence maximum value 251 * is written to this register to reduce the chances of error. 252 */ 253 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); 254 } 255 256 /** 257 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver 258 * @dev: Address of the platform_device structure 259 * 260 * Put the driver into low power mode. 261 * 262 * Return: 0 always 263 */ 264 static int cdns_i2c_runtime_suspend(struct device *dev) 265 { 266 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 267 268 clk_disable(xi2c->clk); 269 270 return 0; 271 } 272 273 /** 274 * cdns_i2c_runtime_resume - Runtime resume 275 * @dev: Address of the platform_device structure 276 * 277 * Runtime resume callback. 278 * 279 * Return: 0 on success and error value on error 280 */ 281 static int cdns_i2c_runtime_resume(struct device *dev) 282 { 283 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 284 int ret; 285 286 ret = clk_enable(xi2c->clk); 287 if (ret) { 288 dev_err(dev, "Cannot enable clock.\n"); 289 return ret; 290 } 291 cdns_i2c_init(xi2c); 292 293 return 0; 294 } 295 296 /** 297 * cdns_i2c_clear_bus_hold - Clear bus hold bit 298 * @id: Pointer to driver data struct 299 * 300 * Helper to clear the controller's bus hold bit. 301 */ 302 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) 303 { 304 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 305 if (reg & CDNS_I2C_CR_HOLD) 306 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET); 307 } 308 309 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) 310 { 311 return (hold_wrkaround && 312 (id->curr_recv_count == id->fifo_depth + 1)); 313 } 314 315 #if IS_ENABLED(CONFIG_I2C_SLAVE) 316 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) 317 { 318 /* Disable all interrupts */ 319 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 320 321 /* Clear FIFO and transfer size */ 322 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); 323 324 /* Update device mode and state */ 325 id->dev_mode = mode; 326 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 327 328 switch (mode) { 329 case CDNS_I2C_MODE_MASTER: 330 /* Enable i2c master */ 331 cdns_i2c_writereg(id->ctrl_reg_diva_divb | 332 CDNS_I2C_CR_MASTER_EN_MASK, 333 CDNS_I2C_CR_OFFSET); 334 /* 335 * This delay is needed to give the IP some time to switch to 336 * the master mode. With lower values(like 110 us) i2cdetect 337 * will not detect any slave and without this delay, the IP will 338 * trigger a timeout interrupt. 339 */ 340 usleep_range(115, 125); 341 break; 342 case CDNS_I2C_MODE_SLAVE: 343 /* Enable i2c slave */ 344 cdns_i2c_writereg(id->ctrl_reg_diva_divb & 345 CDNS_I2C_CR_SLAVE_EN_MASK, 346 CDNS_I2C_CR_OFFSET); 347 348 /* Setting slave address */ 349 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK, 350 CDNS_I2C_ADDR_OFFSET); 351 352 /* Enable slave send/receive interrupts */ 353 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK, 354 CDNS_I2C_IER_OFFSET); 355 break; 356 } 357 } 358 359 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) 360 { 361 u8 bytes; 362 unsigned char data; 363 364 /* Prepare backend for data reception */ 365 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { 366 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV; 367 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL); 368 } 369 370 /* Fetch number of bytes to receive */ 371 bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 372 373 /* Read data and send to backend */ 374 while (bytes--) { 375 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 376 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data); 377 } 378 } 379 380 static void cdns_i2c_slave_send_data(struct cdns_i2c *id) 381 { 382 u8 data; 383 384 /* Prepare backend for data transmission */ 385 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { 386 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND; 387 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data); 388 } else { 389 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data); 390 } 391 392 /* Send data over bus */ 393 cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET); 394 } 395 396 /** 397 * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role 398 * @ptr: Pointer to I2C device private data 399 * 400 * This function handles the data interrupt and transfer complete interrupt of 401 * the I2C device in slave role. 402 * 403 * Return: IRQ_HANDLED always 404 */ 405 static irqreturn_t cdns_i2c_slave_isr(void *ptr) 406 { 407 struct cdns_i2c *id = ptr; 408 unsigned int isr_status, i2c_status; 409 410 /* Fetch the interrupt status */ 411 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 412 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 413 414 /* Ignore masked interrupts */ 415 isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET); 416 417 /* Fetch transfer mode (send/receive) */ 418 i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 419 420 /* Handle data send/receive */ 421 if (i2c_status & CDNS_I2C_SR_RXRW) { 422 /* Send data to master */ 423 if (isr_status & CDNS_I2C_IXR_DATA) 424 cdns_i2c_slave_send_data(id); 425 426 if (isr_status & CDNS_I2C_IXR_COMP) { 427 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 428 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 429 } 430 } else { 431 /* Receive data from master */ 432 if (isr_status & CDNS_I2C_IXR_DATA) 433 cdns_i2c_slave_rcv_data(id); 434 435 if (isr_status & CDNS_I2C_IXR_COMP) { 436 cdns_i2c_slave_rcv_data(id); 437 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 438 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 439 } 440 } 441 442 /* Master indicated xfer stop or fifo underflow/overflow */ 443 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF | 444 CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) { 445 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 446 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 447 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); 448 } 449 450 return IRQ_HANDLED; 451 } 452 #endif 453 454 /** 455 * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role 456 * @ptr: Pointer to I2C device private data 457 * 458 * This function handles the data interrupt, transfer complete interrupt and 459 * the error interrupts of the I2C device in master role. 460 * 461 * Return: IRQ_HANDLED always 462 */ 463 static irqreturn_t cdns_i2c_master_isr(void *ptr) 464 { 465 unsigned int isr_status, avail_bytes; 466 unsigned int bytes_to_send; 467 bool updatetx; 468 struct cdns_i2c *id = ptr; 469 /* Signal completion only after everything is updated */ 470 int done_flag = 0; 471 irqreturn_t status = IRQ_NONE; 472 473 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 474 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 475 id->err_status = 0; 476 477 /* Handling nack and arbitration lost interrupt */ 478 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) { 479 done_flag = 1; 480 status = IRQ_HANDLED; 481 } 482 483 /* 484 * Check if transfer size register needs to be updated again for a 485 * large data receive operation. 486 */ 487 updatetx = id->recv_count > id->curr_recv_count; 488 489 /* When receiving, handle data interrupt and completion interrupt */ 490 if (id->p_recv_buf && 491 ((isr_status & CDNS_I2C_IXR_COMP) || 492 (isr_status & CDNS_I2C_IXR_DATA))) { 493 /* Read data if receive data valid is set */ 494 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & 495 CDNS_I2C_SR_RXDV) { 496 if (id->recv_count > 0) { 497 *(id->p_recv_buf)++ = 498 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 499 id->recv_count--; 500 id->curr_recv_count--; 501 502 /* 503 * Clear hold bit that was set for FIFO control 504 * if RX data left is less than or equal to 505 * FIFO DEPTH unless repeated start is selected 506 */ 507 if (id->recv_count <= id->fifo_depth && 508 !id->bus_hold_flag) 509 cdns_i2c_clear_bus_hold(id); 510 511 } else { 512 dev_err(id->adap.dev.parent, 513 "xfer_size reg rollover. xfer aborted!\n"); 514 id->err_status |= CDNS_I2C_IXR_TO; 515 break; 516 } 517 518 if (cdns_is_holdquirk(id, updatetx)) 519 break; 520 } 521 522 /* 523 * The controller sends NACK to the slave when transfer size 524 * register reaches zero without considering the HOLD bit. 525 * This workaround is implemented for large data transfers to 526 * maintain transfer size non-zero while performing a large 527 * receive operation. 528 */ 529 if (cdns_is_holdquirk(id, updatetx)) { 530 /* wait while fifo is full */ 531 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) != 532 (id->curr_recv_count - id->fifo_depth)) 533 ; 534 535 /* 536 * Check number of bytes to be received against maximum 537 * transfer size and update register accordingly. 538 */ 539 if (((int)(id->recv_count) - id->fifo_depth) > 540 id->transfer_size) { 541 cdns_i2c_writereg(id->transfer_size, 542 CDNS_I2C_XFER_SIZE_OFFSET); 543 id->curr_recv_count = id->transfer_size + 544 id->fifo_depth; 545 } else { 546 cdns_i2c_writereg(id->recv_count - 547 id->fifo_depth, 548 CDNS_I2C_XFER_SIZE_OFFSET); 549 id->curr_recv_count = id->recv_count; 550 } 551 } 552 553 /* Clear hold (if not repeated start) and signal completion */ 554 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) { 555 if (!id->bus_hold_flag) 556 cdns_i2c_clear_bus_hold(id); 557 done_flag = 1; 558 } 559 560 status = IRQ_HANDLED; 561 } 562 563 /* When sending, handle transfer complete interrupt */ 564 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) { 565 /* 566 * If there is more data to be sent, calculate the 567 * space available in FIFO and fill with that many bytes. 568 */ 569 if (id->send_count) { 570 avail_bytes = id->fifo_depth - 571 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 572 if (id->send_count > avail_bytes) 573 bytes_to_send = avail_bytes; 574 else 575 bytes_to_send = id->send_count; 576 577 while (bytes_to_send--) { 578 cdns_i2c_writereg( 579 (*(id->p_send_buf)++), 580 CDNS_I2C_DATA_OFFSET); 581 id->send_count--; 582 } 583 } else { 584 /* 585 * Signal the completion of transaction and 586 * clear the hold bus bit if there are no 587 * further messages to be processed. 588 */ 589 done_flag = 1; 590 } 591 if (!id->send_count && !id->bus_hold_flag) 592 cdns_i2c_clear_bus_hold(id); 593 594 status = IRQ_HANDLED; 595 } 596 597 /* Update the status for errors */ 598 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; 599 if (id->err_status) 600 status = IRQ_HANDLED; 601 602 if (done_flag) 603 complete(&id->xfer_done); 604 605 return status; 606 } 607 608 /** 609 * cdns_i2c_isr - Interrupt handler for the I2C device 610 * @irq: irq number for the I2C device 611 * @ptr: void pointer to cdns_i2c structure 612 * 613 * This function passes the control to slave/master based on current role of 614 * i2c controller. 615 * 616 * Return: IRQ_HANDLED always 617 */ 618 static irqreturn_t cdns_i2c_isr(int irq, void *ptr) 619 { 620 #if IS_ENABLED(CONFIG_I2C_SLAVE) 621 struct cdns_i2c *id = ptr; 622 623 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) 624 return cdns_i2c_slave_isr(ptr); 625 #endif 626 return cdns_i2c_master_isr(ptr); 627 } 628 629 static bool cdns_i2c_error_check(struct cdns_i2c *id) 630 { 631 unsigned int isr_status; 632 633 id->err_status = 0; 634 635 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 636 cdns_i2c_writereg(isr_status & CDNS_I2C_IXR_ERR_INTR_MASK, CDNS_I2C_ISR_OFFSET); 637 638 id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; 639 640 return !!id->err_status; 641 } 642 643 static void cdns_i2c_mrecv_atomic(struct cdns_i2c *id) 644 { 645 while (id->recv_count > 0) { 646 bool updatetx; 647 648 /* 649 * Check if transfer size register needs to be updated again for a 650 * large data receive operation. 651 */ 652 updatetx = id->recv_count > id->curr_recv_count; 653 654 while (id->curr_recv_count > 0) { 655 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_RXDV) { 656 *id->p_recv_buf = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 657 id->p_recv_buf++; 658 id->recv_count--; 659 id->curr_recv_count--; 660 661 /* 662 * Clear the hold bit that was set for FIFO control, 663 * if the remaining RX data is less than or equal to 664 * the FIFO depth, unless a repeated start is selected. 665 */ 666 if (id->recv_count <= id->fifo_depth && !id->bus_hold_flag) 667 cdns_i2c_clear_bus_hold(id); 668 } 669 if (cdns_i2c_error_check(id)) 670 return; 671 if (cdns_is_holdquirk(id, updatetx)) 672 break; 673 } 674 675 /* 676 * The controller sends NACK to the slave/target when transfer size 677 * register reaches zero without considering the HOLD bit. 678 * This workaround is implemented for large data transfers to 679 * maintain transfer size non-zero while performing a large 680 * receive operation. 681 */ 682 if (cdns_is_holdquirk(id, updatetx)) { 683 /* wait while fifo is full */ 684 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) != 685 (id->curr_recv_count - id->fifo_depth)) 686 ; 687 688 /* 689 * Check number of bytes to be received against maximum 690 * transfer size and update register accordingly. 691 */ 692 if ((id->recv_count - id->fifo_depth) > 693 id->transfer_size) { 694 cdns_i2c_writereg(id->transfer_size, 695 CDNS_I2C_XFER_SIZE_OFFSET); 696 id->curr_recv_count = id->transfer_size + 697 id->fifo_depth; 698 } else { 699 cdns_i2c_writereg(id->recv_count - 700 id->fifo_depth, 701 CDNS_I2C_XFER_SIZE_OFFSET); 702 id->curr_recv_count = id->recv_count; 703 } 704 } 705 } 706 707 /* Clear hold (if not repeated start) */ 708 if (!id->recv_count && !id->bus_hold_flag) 709 cdns_i2c_clear_bus_hold(id); 710 } 711 712 /** 713 * cdns_i2c_mrecv - Prepare and start a master receive operation 714 * @id: pointer to the i2c device structure 715 */ 716 static void cdns_i2c_mrecv(struct cdns_i2c *id) 717 { 718 unsigned int ctrl_reg; 719 unsigned int isr_status; 720 unsigned long flags; 721 bool hold_clear = false; 722 bool irq_save = false; 723 724 u32 addr; 725 726 id->p_recv_buf = id->p_msg->buf; 727 id->recv_count = id->p_msg->len; 728 729 /* Put the controller in master receive mode and clear the FIFO */ 730 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 731 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; 732 733 /* 734 * Receive up to I2C_SMBUS_BLOCK_MAX data bytes, plus one message length 735 * byte, plus one checksum byte if PEC is enabled. p_msg->len will be 2 if 736 * PEC is enabled, otherwise 1. 737 */ 738 if (id->p_msg->flags & I2C_M_RECV_LEN) 739 id->recv_count = I2C_SMBUS_BLOCK_MAX + id->p_msg->len; 740 741 id->curr_recv_count = id->recv_count; 742 743 /* 744 * Check for the message size against FIFO depth and set the 745 * 'hold bus' bit if it is greater than FIFO depth. 746 */ 747 if (id->recv_count > id->fifo_depth) 748 ctrl_reg |= CDNS_I2C_CR_HOLD; 749 750 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 751 752 /* Clear the interrupts in interrupt status register */ 753 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 754 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 755 756 /* 757 * The no. of bytes to receive is checked against the limit of 758 * max transfer size. Set transfer size register with no of bytes 759 * receive if it is less than transfer size and transfer size if 760 * it is more. Enable the interrupts. 761 */ 762 if (id->recv_count > id->transfer_size) { 763 cdns_i2c_writereg(id->transfer_size, 764 CDNS_I2C_XFER_SIZE_OFFSET); 765 id->curr_recv_count = id->transfer_size; 766 } else { 767 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); 768 } 769 770 /* Determine hold_clear based on number of bytes to receive and hold flag */ 771 if (!id->bus_hold_flag && id->recv_count <= id->fifo_depth) { 772 if (ctrl_reg & CDNS_I2C_CR_HOLD) { 773 hold_clear = true; 774 if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) 775 irq_save = true; 776 } 777 } 778 779 addr = id->p_msg->addr; 780 addr &= CDNS_I2C_ADDR_MASK; 781 782 if (hold_clear) { 783 ctrl_reg &= ~CDNS_I2C_CR_HOLD; 784 ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO; 785 /* 786 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size 787 * register reaches '0'. This is an IP bug which causes transfer size 788 * register overflow to 0xFF. To satisfy this timing requirement, 789 * disable the interrupts on current processor core between register 790 * writes to slave address register and control register. 791 */ 792 if (irq_save) 793 local_irq_save(flags); 794 795 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); 796 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 797 /* Read it back to avoid bufferring and make sure write happens */ 798 cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 799 800 if (irq_save) 801 local_irq_restore(flags); 802 } else { 803 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); 804 } 805 806 if (!id->atomic) 807 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 808 else 809 cdns_i2c_mrecv_atomic(id); 810 } 811 812 static void cdns_i2c_msend_rem_atomic(struct cdns_i2c *id) 813 { 814 while (id->send_count) { 815 unsigned int avail_bytes; 816 unsigned int bytes_to_send; 817 818 avail_bytes = id->fifo_depth - cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 819 if (id->send_count > avail_bytes) 820 bytes_to_send = avail_bytes; 821 else 822 bytes_to_send = id->send_count; 823 824 while (bytes_to_send--) { 825 cdns_i2c_writereg((*id->p_send_buf++), CDNS_I2C_DATA_OFFSET); 826 id->send_count--; 827 } 828 if (cdns_i2c_error_check(id)) 829 return; 830 } 831 832 if (!id->send_count && !id->bus_hold_flag) 833 cdns_i2c_clear_bus_hold(id); 834 } 835 836 /** 837 * cdns_i2c_msend - Prepare and start a master send operation 838 * @id: pointer to the i2c device 839 */ 840 static void cdns_i2c_msend(struct cdns_i2c *id) 841 { 842 unsigned int avail_bytes; 843 unsigned int bytes_to_send; 844 unsigned int ctrl_reg; 845 unsigned int isr_status; 846 847 id->p_recv_buf = NULL; 848 id->p_send_buf = id->p_msg->buf; 849 id->send_count = id->p_msg->len; 850 851 /* Set the controller in Master transmit mode and clear the FIFO. */ 852 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 853 ctrl_reg &= ~CDNS_I2C_CR_RW; 854 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; 855 856 /* 857 * Check for the message size against FIFO depth and set the 858 * 'hold bus' bit if it is greater than FIFO depth. 859 */ 860 if (id->send_count > id->fifo_depth) 861 ctrl_reg |= CDNS_I2C_CR_HOLD; 862 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 863 864 /* Clear the interrupts in interrupt status register. */ 865 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 866 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 867 868 /* 869 * Calculate the space available in FIFO. Check the message length 870 * against the space available, and fill the FIFO accordingly. 871 * Enable the interrupts. 872 */ 873 avail_bytes = id->fifo_depth - 874 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 875 876 if (id->send_count > avail_bytes) 877 bytes_to_send = avail_bytes; 878 else 879 bytes_to_send = id->send_count; 880 881 while (bytes_to_send--) { 882 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET); 883 id->send_count--; 884 } 885 886 /* 887 * Clear the bus hold flag if there is no more data 888 * and if it is the last message. 889 */ 890 if (!id->bus_hold_flag && !id->send_count) 891 cdns_i2c_clear_bus_hold(id); 892 /* Set the slave address in address register - triggers operation. */ 893 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 894 CDNS_I2C_ADDR_OFFSET); 895 896 if (!id->atomic) 897 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 898 else if (id->send_count > 0) 899 cdns_i2c_msend_rem_atomic(id); 900 } 901 902 /** 903 * cdns_i2c_master_reset - Reset the interface 904 * @adap: pointer to the i2c adapter driver instance 905 * 906 * This function cleanup the fifos, clear the hold bit and status 907 * and disable the interrupts. 908 */ 909 static void cdns_i2c_master_reset(struct i2c_adapter *adap) 910 { 911 struct cdns_i2c *id = adap->algo_data; 912 u32 regval; 913 914 /* Disable the interrupts */ 915 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 916 /* Clear the hold bit and fifos */ 917 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 918 regval &= ~CDNS_I2C_CR_HOLD; 919 regval |= CDNS_I2C_CR_CLR_FIFO; 920 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET); 921 /* Update the transfercount register to zero */ 922 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET); 923 /* Clear the interrupt status register */ 924 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 925 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET); 926 /* Clear the status register */ 927 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 928 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET); 929 } 930 931 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg, 932 struct i2c_adapter *adap) 933 { 934 unsigned long time_left, msg_timeout; 935 u32 reg; 936 937 id->p_msg = msg; 938 id->err_status = 0; 939 if (!id->atomic) 940 reinit_completion(&id->xfer_done); 941 942 /* Check for the TEN Bit mode on each msg */ 943 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 944 if (msg->flags & I2C_M_TEN) { 945 if (reg & CDNS_I2C_CR_NEA) 946 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA, 947 CDNS_I2C_CR_OFFSET); 948 } else { 949 if (!(reg & CDNS_I2C_CR_NEA)) 950 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA, 951 CDNS_I2C_CR_OFFSET); 952 } 953 954 /* Check for the R/W flag on each msg */ 955 if (msg->flags & I2C_M_RD) 956 cdns_i2c_mrecv(id); 957 else 958 cdns_i2c_msend(id); 959 960 /* Minimal time to execute this message */ 961 msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk); 962 963 /* 964 * Plus some wiggle room. 965 * For non-atomic contexts, 500 ms is added to the timeout. 966 * For atomic contexts, 2000 ms is added because transfers happen in polled 967 * mode, requiring more time to account for the polling overhead. 968 */ 969 if (!id->atomic) 970 msg_timeout += msecs_to_jiffies(500); 971 else 972 msg_timeout += msecs_to_jiffies(2000); 973 974 if (msg_timeout < adap->timeout) 975 msg_timeout = adap->timeout; 976 977 if (!id->atomic) { 978 /* Wait for the signal of completion */ 979 time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout); 980 } else { 981 /* 0 is success, -ETIMEDOUT is error */ 982 time_left = !readl_poll_timeout_atomic(id->membase + CDNS_I2C_ISR_OFFSET, 983 reg, (reg & CDNS_I2C_IXR_COMP), 984 CDNS_I2C_POLL_US_ATOMIC, msg_timeout); 985 } 986 987 if (time_left == 0) { 988 cdns_i2c_master_reset(adap); 989 return -ETIMEDOUT; 990 } 991 992 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, 993 CDNS_I2C_IDR_OFFSET); 994 995 /* If it is bus arbitration error, try again */ 996 if (id->err_status & CDNS_I2C_IXR_ARB_LOST) 997 return -EAGAIN; 998 999 if (msg->flags & I2C_M_RECV_LEN) 1000 msg->len += min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX); 1001 1002 return 0; 1003 } 1004 1005 static int cdns_i2c_master_common_xfer(struct i2c_adapter *adap, 1006 struct i2c_msg *msgs, 1007 int num) 1008 { 1009 int ret, count; 1010 u32 reg; 1011 struct cdns_i2c *id = adap->algo_data; 1012 bool hold_quirk; 1013 1014 /* Check if the bus is free */ 1015 if (!id->atomic) 1016 ret = readl_relaxed_poll_timeout(id->membase + CDNS_I2C_SR_OFFSET, 1017 reg, 1018 !(reg & CDNS_I2C_SR_BA), 1019 CDNS_I2C_POLL_US, CDNS_I2C_TIMEOUT_US); 1020 else 1021 ret = readl_poll_timeout_atomic(id->membase + CDNS_I2C_SR_OFFSET, 1022 reg, 1023 !(reg & CDNS_I2C_SR_BA), 1024 CDNS_I2C_POLL_US_ATOMIC, CDNS_I2C_TIMEOUT_US); 1025 if (ret) { 1026 ret = -EAGAIN; 1027 if (id->adap.bus_recovery_info) 1028 i2c_recover_bus(adap); 1029 return ret; 1030 } 1031 1032 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT); 1033 /* 1034 * Set the flag to one when multiple messages are to be 1035 * processed with a repeated start. 1036 */ 1037 if (num > 1) { 1038 /* 1039 * This controller does not give completion interrupt after a 1040 * master receive message if HOLD bit is set (repeated start), 1041 * resulting in SW timeout. Hence, if a receive message is 1042 * followed by any other message, an error is returned 1043 * indicating that this sequence is not supported. 1044 */ 1045 for (count = 0; (count < num - 1 && hold_quirk); count++) { 1046 if (msgs[count].flags & I2C_M_RD) { 1047 dev_warn(adap->dev.parent, 1048 "Can't do repeated start after a receive message\n"); 1049 return -EOPNOTSUPP; 1050 } 1051 } 1052 id->bus_hold_flag = 1; 1053 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 1054 reg |= CDNS_I2C_CR_HOLD; 1055 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET); 1056 } else { 1057 id->bus_hold_flag = 0; 1058 } 1059 1060 /* Process the msg one by one */ 1061 for (count = 0; count < num; count++, msgs++) { 1062 if (count == (num - 1)) 1063 id->bus_hold_flag = 0; 1064 1065 ret = cdns_i2c_process_msg(id, msgs, adap); 1066 if (ret) 1067 return ret; 1068 1069 /* Report the other error interrupts to application */ 1070 if (id->err_status || id->err_status_atomic) { 1071 cdns_i2c_master_reset(adap); 1072 1073 if (id->err_status & CDNS_I2C_IXR_NACK) 1074 return -ENXIO; 1075 1076 return -EIO; 1077 } 1078 } 1079 return 0; 1080 } 1081 1082 /** 1083 * cdns_i2c_master_xfer - The main i2c transfer function 1084 * @adap: pointer to the i2c adapter driver instance 1085 * @msgs: pointer to the i2c message structure 1086 * @num: the number of messages to transfer 1087 * 1088 * Initiates the send/recv activity based on the transfer message received. 1089 * 1090 * Return: number of msgs processed on success, negative error otherwise 1091 */ 1092 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 1093 int num) 1094 { 1095 int ret; 1096 struct cdns_i2c *id = adap->algo_data; 1097 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1098 bool change_role = false; 1099 #endif 1100 1101 ret = pm_runtime_resume_and_get(id->dev); 1102 if (ret < 0) 1103 return ret; 1104 1105 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1106 /* Check i2c operating mode and switch if possible */ 1107 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) { 1108 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE) { 1109 ret = -EAGAIN; 1110 goto out; 1111 } 1112 1113 /* Set mode to master */ 1114 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); 1115 1116 /* Mark flag to change role once xfer is completed */ 1117 change_role = true; 1118 } 1119 #endif 1120 1121 ret = cdns_i2c_master_common_xfer(adap, msgs, num); 1122 if (!ret) 1123 ret = num; 1124 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1125 out: 1126 /* Switch i2c mode to slave */ 1127 if (change_role) 1128 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); 1129 #endif 1130 1131 pm_runtime_mark_last_busy(id->dev); 1132 pm_runtime_put_autosuspend(id->dev); 1133 return ret; 1134 } 1135 1136 /** 1137 * cdns_i2c_master_xfer_atomic - The i2c transfer function in atomic mode 1138 * @adap: pointer to the i2c adapter driver instance 1139 * @msgs: pointer to the i2c message structure 1140 * @num: the number of messages to transfer 1141 * 1142 * Return: number of msgs processed on success, negative error otherwise 1143 */ 1144 static int cdns_i2c_master_xfer_atomic(struct i2c_adapter *adap, struct i2c_msg *msgs, 1145 int num) 1146 { 1147 int ret; 1148 struct cdns_i2c *id = adap->algo_data; 1149 1150 ret = cdns_i2c_runtime_resume(id->dev); 1151 if (ret) 1152 return ret; 1153 1154 if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) { 1155 dev_warn(id->adap.dev.parent, 1156 "Atomic xfer not supported for version 1.0\n"); 1157 return 0; 1158 } 1159 1160 id->atomic = true; 1161 ret = cdns_i2c_master_common_xfer(adap, msgs, num); 1162 if (!ret) 1163 ret = num; 1164 1165 id->atomic = false; 1166 cdns_i2c_runtime_suspend(id->dev); 1167 1168 return ret; 1169 } 1170 1171 /** 1172 * cdns_i2c_func - Returns the supported features of the I2C driver 1173 * @adap: pointer to the i2c adapter structure 1174 * 1175 * Return: 32 bit value, each bit corresponding to a feature 1176 */ 1177 static u32 cdns_i2c_func(struct i2c_adapter *adap) 1178 { 1179 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 1180 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1181 I2C_FUNC_SMBUS_BLOCK_DATA; 1182 1183 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1184 func |= I2C_FUNC_SLAVE; 1185 #endif 1186 1187 return func; 1188 } 1189 1190 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1191 static int cdns_reg_slave(struct i2c_client *slave) 1192 { 1193 int ret; 1194 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, 1195 adap); 1196 1197 if (id->slave) 1198 return -EBUSY; 1199 1200 if (slave->flags & I2C_CLIENT_TEN) 1201 return -EAFNOSUPPORT; 1202 1203 ret = pm_runtime_resume_and_get(id->dev); 1204 if (ret < 0) 1205 return ret; 1206 1207 /* Store slave information */ 1208 id->slave = slave; 1209 1210 /* Enable I2C slave */ 1211 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); 1212 1213 return 0; 1214 } 1215 1216 static int cdns_unreg_slave(struct i2c_client *slave) 1217 { 1218 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, 1219 adap); 1220 1221 pm_runtime_put(id->dev); 1222 1223 /* Remove slave information */ 1224 id->slave = NULL; 1225 1226 /* Enable I2C master */ 1227 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); 1228 1229 return 0; 1230 } 1231 #endif 1232 1233 static const struct i2c_algorithm cdns_i2c_algo = { 1234 .master_xfer = cdns_i2c_master_xfer, 1235 .master_xfer_atomic = cdns_i2c_master_xfer_atomic, 1236 .functionality = cdns_i2c_func, 1237 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1238 .reg_slave = cdns_reg_slave, 1239 .unreg_slave = cdns_unreg_slave, 1240 #endif 1241 }; 1242 1243 /** 1244 * cdns_i2c_calc_divs - Calculate clock dividers 1245 * @f: I2C clock frequency 1246 * @input_clk: Input clock frequency 1247 * @a: First divider (return value) 1248 * @b: Second divider (return value) 1249 * 1250 * f is used as input and output variable. As input it is used as target I2C 1251 * frequency. On function exit f holds the actually resulting I2C frequency. 1252 * 1253 * Return: 0 on success, negative errno otherwise. 1254 */ 1255 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, 1256 unsigned int *a, unsigned int *b) 1257 { 1258 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; 1259 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; 1260 unsigned int last_error, current_error; 1261 1262 /* calculate (divisor_a+1) x (divisor_b+1) */ 1263 temp = input_clk / (22 * fscl); 1264 1265 /* 1266 * If the calculated value is negative or 0, the fscl input is out of 1267 * range. Return error. 1268 */ 1269 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) 1270 return -EINVAL; 1271 1272 last_error = -1; 1273 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { 1274 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); 1275 1276 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) 1277 continue; 1278 div_b--; 1279 1280 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); 1281 1282 if (actual_fscl > fscl) 1283 continue; 1284 1285 current_error = fscl - actual_fscl; 1286 1287 if (last_error > current_error) { 1288 calc_div_a = div_a; 1289 calc_div_b = div_b; 1290 best_fscl = actual_fscl; 1291 last_error = current_error; 1292 } 1293 } 1294 1295 *a = calc_div_a; 1296 *b = calc_div_b; 1297 *f = best_fscl; 1298 1299 return 0; 1300 } 1301 1302 /** 1303 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device 1304 * @clk_in: I2C clock input frequency in Hz 1305 * @id: Pointer to the I2C device structure 1306 * 1307 * The device must be idle rather than busy transferring data before setting 1308 * these device options. 1309 * The data rate is set by values in the control register. 1310 * The formula for determining the correct register values is 1311 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) 1312 * See the hardware data sheet for a full explanation of setting the serial 1313 * clock rate. The clock can not be faster than the input clock divide by 22. 1314 * The two most common clock rates are 100KHz and 400KHz. 1315 * 1316 * Return: 0 on success, negative error otherwise 1317 */ 1318 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id) 1319 { 1320 unsigned int div_a, div_b; 1321 unsigned int ctrl_reg; 1322 int ret = 0; 1323 unsigned long fscl = id->i2c_clk; 1324 1325 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b); 1326 if (ret) 1327 return ret; 1328 1329 ctrl_reg = id->ctrl_reg; 1330 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK); 1331 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) | 1332 (div_b << CDNS_I2C_CR_DIVB_SHIFT)); 1333 id->ctrl_reg = ctrl_reg; 1334 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 1335 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1336 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK | 1337 CDNS_I2C_CR_DIVB_MASK); 1338 #endif 1339 return 0; 1340 } 1341 1342 /** 1343 * cdns_i2c_clk_notifier_cb - Clock rate change callback 1344 * @nb: Pointer to notifier block 1345 * @event: Notification reason 1346 * @data: Pointer to notification data object 1347 * 1348 * This function is called when the cdns_i2c input clock frequency changes. 1349 * The callback checks whether a valid bus frequency can be generated after the 1350 * change. If so, the change is acknowledged, otherwise the change is aborted. 1351 * New dividers are written to the HW in the pre- or post change notification 1352 * depending on the scaling direction. 1353 * 1354 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 1355 * to acknowledge the change, NOTIFY_DONE if the notification is 1356 * considered irrelevant. 1357 */ 1358 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 1359 event, void *data) 1360 { 1361 struct clk_notifier_data *ndata = data; 1362 struct cdns_i2c *id = to_cdns_i2c(nb); 1363 1364 if (pm_runtime_suspended(id->dev)) 1365 return NOTIFY_OK; 1366 1367 switch (event) { 1368 case PRE_RATE_CHANGE: 1369 { 1370 unsigned long input_clk = ndata->new_rate; 1371 unsigned long fscl = id->i2c_clk; 1372 unsigned int div_a, div_b; 1373 int ret; 1374 1375 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); 1376 if (ret) { 1377 dev_warn(id->adap.dev.parent, 1378 "clock rate change rejected\n"); 1379 return NOTIFY_STOP; 1380 } 1381 1382 /* scale up */ 1383 if (ndata->new_rate > ndata->old_rate) 1384 cdns_i2c_setclk(ndata->new_rate, id); 1385 1386 return NOTIFY_OK; 1387 } 1388 case POST_RATE_CHANGE: 1389 id->input_clk = ndata->new_rate; 1390 /* scale down */ 1391 if (ndata->new_rate < ndata->old_rate) 1392 cdns_i2c_setclk(ndata->new_rate, id); 1393 return NOTIFY_OK; 1394 case ABORT_RATE_CHANGE: 1395 /* scale up */ 1396 if (ndata->new_rate > ndata->old_rate) 1397 cdns_i2c_setclk(ndata->old_rate, id); 1398 return NOTIFY_OK; 1399 default: 1400 return NOTIFY_DONE; 1401 } 1402 } 1403 1404 static int __maybe_unused cdns_i2c_suspend(struct device *dev) 1405 { 1406 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 1407 1408 i2c_mark_adapter_suspended(&xi2c->adap); 1409 1410 if (!pm_runtime_status_suspended(dev)) 1411 return cdns_i2c_runtime_suspend(dev); 1412 1413 return 0; 1414 } 1415 1416 static int __maybe_unused cdns_i2c_resume(struct device *dev) 1417 { 1418 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 1419 int err; 1420 1421 err = cdns_i2c_runtime_resume(dev); 1422 if (err) 1423 return err; 1424 1425 if (pm_runtime_status_suspended(dev)) { 1426 err = cdns_i2c_runtime_suspend(dev); 1427 if (err) 1428 return err; 1429 } 1430 1431 i2c_mark_adapter_resumed(&xi2c->adap); 1432 1433 return 0; 1434 } 1435 1436 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = { 1437 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_i2c_suspend, cdns_i2c_resume) 1438 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend, 1439 cdns_i2c_runtime_resume, NULL) 1440 }; 1441 1442 static const struct cdns_platform_data r1p10_i2c_def = { 1443 .quirks = CDNS_I2C_BROKEN_HOLD_BIT, 1444 }; 1445 1446 static const struct of_device_id cdns_i2c_of_match[] = { 1447 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def }, 1448 { .compatible = "cdns,i2c-r1p14",}, 1449 { /* end of table */ } 1450 }; 1451 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match); 1452 1453 /** 1454 * cdns_i2c_detect_transfer_size - Detect the maximum transfer size supported 1455 * @id: Device private data structure 1456 * 1457 * Detect the maximum transfer size that is supported by this instance of the 1458 * Cadence I2C controller. 1459 */ 1460 static void cdns_i2c_detect_transfer_size(struct cdns_i2c *id) 1461 { 1462 u32 val; 1463 1464 /* 1465 * Writing to the transfer size register is only possible if these two bits 1466 * are set in the control register. 1467 */ 1468 cdns_i2c_writereg(CDNS_I2C_CR_MS | CDNS_I2C_CR_RW, CDNS_I2C_CR_OFFSET); 1469 1470 /* 1471 * The number of writable bits of the transfer size register can be between 1472 * 4 and 8. This is a controlled through a synthesis parameter of the IP 1473 * core and can vary from instance to instance. The unused MSBs always read 1474 * back as 0. Writing 0xff and then reading the value back will report the 1475 * maximum supported transfer size. 1476 */ 1477 cdns_i2c_writereg(CDNS_I2C_MAX_TRANSFER_SIZE, CDNS_I2C_XFER_SIZE_OFFSET); 1478 val = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 1479 id->transfer_size = CDNS_I2C_TRANSFER_SIZE(val); 1480 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET); 1481 cdns_i2c_writereg(0, CDNS_I2C_CR_OFFSET); 1482 } 1483 1484 /** 1485 * cdns_i2c_probe - Platform registration call 1486 * @pdev: Handle to the platform device structure 1487 * 1488 * This function does all the memory allocation and registration for the i2c 1489 * device. User can modify the address mode to 10 bit address mode using the 1490 * ioctl call with option I2C_TENBIT. 1491 * 1492 * Return: 0 on success, negative error otherwise 1493 */ 1494 static int cdns_i2c_probe(struct platform_device *pdev) 1495 { 1496 struct resource *r_mem; 1497 struct cdns_i2c *id; 1498 int ret, irq; 1499 const struct of_device_id *match; 1500 1501 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL); 1502 if (!id) 1503 return -ENOMEM; 1504 1505 id->dev = &pdev->dev; 1506 platform_set_drvdata(pdev, id); 1507 1508 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node); 1509 if (match && match->data) { 1510 const struct cdns_platform_data *data = match->data; 1511 id->quirks = data->quirks; 1512 } 1513 1514 id->rinfo.pinctrl = devm_pinctrl_get(&pdev->dev); 1515 if (IS_ERR(id->rinfo.pinctrl)) { 1516 int err = PTR_ERR(id->rinfo.pinctrl); 1517 1518 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1519 if (err != -ENODEV) 1520 return err; 1521 } else { 1522 id->adap.bus_recovery_info = &id->rinfo; 1523 } 1524 1525 id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem); 1526 if (IS_ERR(id->membase)) 1527 return PTR_ERR(id->membase); 1528 1529 irq = platform_get_irq(pdev, 0); 1530 if (irq < 0) 1531 return irq; 1532 1533 id->adap.owner = THIS_MODULE; 1534 id->adap.dev.of_node = pdev->dev.of_node; 1535 id->adap.algo = &cdns_i2c_algo; 1536 id->adap.timeout = CDNS_I2C_TIMEOUT; 1537 id->adap.retries = 3; /* Default retry value. */ 1538 id->adap.algo_data = id; 1539 id->adap.dev.parent = &pdev->dev; 1540 init_completion(&id->xfer_done); 1541 snprintf(id->adap.name, sizeof(id->adap.name), 1542 "Cadence I2C at %08lx", (unsigned long)r_mem->start); 1543 1544 id->clk = devm_clk_get(&pdev->dev, NULL); 1545 if (IS_ERR(id->clk)) 1546 return dev_err_probe(&pdev->dev, PTR_ERR(id->clk), 1547 "input clock not found.\n"); 1548 1549 id->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL); 1550 if (IS_ERR(id->reset)) 1551 return dev_err_probe(&pdev->dev, PTR_ERR(id->reset), 1552 "Failed to request reset.\n"); 1553 1554 ret = clk_prepare_enable(id->clk); 1555 if (ret) 1556 dev_err(&pdev->dev, "Unable to enable clock.\n"); 1557 1558 ret = reset_control_deassert(id->reset); 1559 if (ret) { 1560 dev_err_probe(&pdev->dev, ret, 1561 "Failed to de-assert reset.\n"); 1562 goto err_clk_dis; 1563 } 1564 1565 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT); 1566 pm_runtime_use_autosuspend(id->dev); 1567 pm_runtime_set_active(id->dev); 1568 pm_runtime_enable(id->dev); 1569 1570 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb; 1571 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb)) 1572 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1573 id->input_clk = clk_get_rate(id->clk); 1574 1575 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1576 &id->i2c_clk); 1577 if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ)) 1578 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ; 1579 1580 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1581 /* Set initial mode to master */ 1582 id->dev_mode = CDNS_I2C_MODE_MASTER; 1583 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 1584 #endif 1585 id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS; 1586 1587 id->fifo_depth = CDNS_I2C_FIFO_DEPTH_DEFAULT; 1588 of_property_read_u32(pdev->dev.of_node, "fifo-depth", &id->fifo_depth); 1589 1590 cdns_i2c_detect_transfer_size(id); 1591 1592 ret = cdns_i2c_setclk(id->input_clk, id); 1593 if (ret) { 1594 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk); 1595 ret = -EINVAL; 1596 goto err_clk_notifier_unregister; 1597 } 1598 1599 ret = devm_request_irq(&pdev->dev, irq, cdns_i2c_isr, 0, 1600 DRIVER_NAME, id); 1601 if (ret) { 1602 dev_err(&pdev->dev, "cannot get irq %d\n", irq); 1603 goto err_clk_notifier_unregister; 1604 } 1605 cdns_i2c_init(id); 1606 1607 ret = i2c_add_adapter(&id->adap); 1608 if (ret < 0) 1609 goto err_clk_notifier_unregister; 1610 1611 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n", 1612 id->i2c_clk / 1000, (unsigned long)r_mem->start, irq); 1613 1614 return 0; 1615 1616 err_clk_notifier_unregister: 1617 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); 1618 reset_control_assert(id->reset); 1619 err_clk_dis: 1620 clk_disable_unprepare(id->clk); 1621 pm_runtime_disable(&pdev->dev); 1622 pm_runtime_set_suspended(&pdev->dev); 1623 return ret; 1624 } 1625 1626 /** 1627 * cdns_i2c_remove - Unregister the device after releasing the resources 1628 * @pdev: Handle to the platform device structure 1629 * 1630 * This function frees all the resources allocated to the device. 1631 * 1632 * Return: 0 always 1633 */ 1634 static void cdns_i2c_remove(struct platform_device *pdev) 1635 { 1636 struct cdns_i2c *id = platform_get_drvdata(pdev); 1637 1638 pm_runtime_disable(&pdev->dev); 1639 pm_runtime_set_suspended(&pdev->dev); 1640 pm_runtime_dont_use_autosuspend(&pdev->dev); 1641 1642 i2c_del_adapter(&id->adap); 1643 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); 1644 reset_control_assert(id->reset); 1645 clk_disable_unprepare(id->clk); 1646 } 1647 1648 static struct platform_driver cdns_i2c_drv = { 1649 .driver = { 1650 .name = DRIVER_NAME, 1651 .of_match_table = cdns_i2c_of_match, 1652 .pm = &cdns_i2c_dev_pm_ops, 1653 }, 1654 .probe = cdns_i2c_probe, 1655 .remove = cdns_i2c_remove, 1656 }; 1657 1658 module_platform_driver(cdns_i2c_drv); 1659 1660 MODULE_AUTHOR("Xilinx Inc."); 1661 MODULE_DESCRIPTION("Cadence I2C bus driver"); 1662 MODULE_LICENSE("GPL"); 1663