1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/i2c.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched.h> 24 #include <linux/slab.h> 25 #include <linux/version.h> 26 27 #define N_DATA_REGS 8 28 29 /* 30 * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register 31 * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per 32 * data register whereas STB SoCs use 4 byte per data register transfer, 33 * account for this difference in total count per transaction and mask to 34 * use. 35 */ 36 #define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0)) 37 #define BSC_CNT_REG1_SHIFT 0 38 39 /* BSC CTL register field definitions */ 40 #define BSC_CTL_REG_DTF_MASK 0x00000003 41 #define BSC_CTL_REG_SCL_SEL_MASK 0x00000030 42 #define BSC_CTL_REG_SCL_SEL_SHIFT 4 43 #define BSC_CTL_REG_INT_EN_MASK 0x00000040 44 #define BSC_CTL_REG_INT_EN_SHIFT 6 45 #define BSC_CTL_REG_DIV_CLK_MASK 0x00000080 46 47 /* BSC_IIC_ENABLE r/w enable and interrupt field definitions */ 48 #define BSC_IIC_EN_RESTART_MASK 0x00000040 49 #define BSC_IIC_EN_NOSTART_MASK 0x00000020 50 #define BSC_IIC_EN_NOSTOP_MASK 0x00000010 51 #define BSC_IIC_EN_NOACK_MASK 0x00000004 52 #define BSC_IIC_EN_INTRP_MASK 0x00000002 53 #define BSC_IIC_EN_ENABLE_MASK 0x00000001 54 55 /* BSC_CTLHI control register field definitions */ 56 #define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080 57 #define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040 58 #define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 59 #define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001 60 61 #define I2C_TIMEOUT 100 /* msecs */ 62 63 /* Condition mask used for non combined transfer */ 64 #define COND_RESTART BSC_IIC_EN_RESTART_MASK 65 #define COND_NOSTART BSC_IIC_EN_NOSTART_MASK 66 #define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK 67 #define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP) 68 69 /* BSC data transfer direction */ 70 #define DTF_WR_MASK 0x00000000 71 #define DTF_RD_MASK 0x00000001 72 /* BSC data transfer direction combined format */ 73 #define DTF_RD_WR_MASK 0x00000002 74 #define DTF_WR_RD_MASK 0x00000003 75 76 #define INT_ENABLE true 77 #define INT_DISABLE false 78 79 /* BSC block register map structure to cache fields to be written */ 80 struct bsc_regs { 81 u32 chip_address; /* slave address */ 82 u32 data_in[N_DATA_REGS]; /* tx data buffer*/ 83 u32 cnt_reg; /* rx/tx data length */ 84 u32 ctl_reg; /* control register */ 85 u32 iic_enable; /* xfer enable and status */ 86 u32 data_out[N_DATA_REGS]; /* rx data buffer */ 87 u32 ctlhi_reg; /* more control fields */ 88 u32 scl_param; /* reserved */ 89 }; 90 91 struct bsc_clk_param { 92 u32 hz; 93 u32 scl_mask; 94 u32 div_mask; 95 }; 96 97 enum bsc_xfer_cmd { 98 CMD_WR, 99 CMD_RD, 100 CMD_WR_NOACK, 101 CMD_RD_NOACK, 102 }; 103 104 static char const *cmd_string[] = { 105 [CMD_WR] = "WR", 106 [CMD_RD] = "RD", 107 [CMD_WR_NOACK] = "WR NOACK", 108 [CMD_RD_NOACK] = "RD NOACK", 109 }; 110 111 enum bus_speeds { 112 SPD_375K, 113 SPD_390K, 114 SPD_187K, 115 SPD_200K, 116 SPD_93K, 117 SPD_97K, 118 SPD_46K, 119 SPD_50K 120 }; 121 122 static const struct bsc_clk_param bsc_clk[] = { 123 [SPD_375K] = { 124 .hz = 375000, 125 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT, 126 .div_mask = 0 127 }, 128 [SPD_390K] = { 129 .hz = 390000, 130 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT, 131 .div_mask = 0 132 }, 133 [SPD_187K] = { 134 .hz = 187500, 135 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT, 136 .div_mask = 0 137 }, 138 [SPD_200K] = { 139 .hz = 200000, 140 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT, 141 .div_mask = 0 142 }, 143 [SPD_93K] = { 144 .hz = 93750, 145 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT, 146 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 147 }, 148 [SPD_97K] = { 149 .hz = 97500, 150 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT, 151 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 152 }, 153 [SPD_46K] = { 154 .hz = 46875, 155 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT, 156 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 157 }, 158 [SPD_50K] = { 159 .hz = 50000, 160 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT, 161 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 162 } 163 }; 164 165 struct brcmstb_i2c_dev { 166 struct device *device; 167 void __iomem *base; 168 void __iomem *irq_base; 169 int irq; 170 struct bsc_regs *bsc_regmap; 171 struct i2c_adapter adapter; 172 struct completion done; 173 bool is_suspended; 174 u32 clk_freq_hz; 175 int data_regsz; 176 }; 177 178 /* register accessors for both be and le cpu arch */ 179 #ifdef CONFIG_CPU_BIG_ENDIAN 180 #define __bsc_readl(_reg) ioread32be(_reg) 181 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) 182 #else 183 #define __bsc_readl(_reg) ioread32(_reg) 184 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) 185 #endif 186 187 #define bsc_readl(_dev, _reg) \ 188 __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg)) 189 190 #define bsc_writel(_dev, _val, _reg) \ 191 __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg)) 192 193 static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev) 194 { 195 return (N_DATA_REGS * dev->data_regsz); 196 } 197 198 static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev) 199 { 200 return dev->data_regsz; 201 } 202 203 static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev, 204 bool int_en) 205 { 206 207 if (int_en) 208 /* Enable BSC CTL interrupt line */ 209 dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK; 210 else 211 /* Disable BSC CTL interrupt line */ 212 dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK; 213 214 barrier(); 215 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); 216 } 217 218 static irqreturn_t brcmstb_i2c_isr(int irq, void *devid) 219 { 220 struct brcmstb_i2c_dev *dev = devid; 221 u32 status_bsc_ctl = bsc_readl(dev, ctl_reg); 222 u32 status_iic_intrp = bsc_readl(dev, iic_enable); 223 224 dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n", 225 status_bsc_ctl, status_iic_intrp); 226 227 if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK)) 228 return IRQ_NONE; 229 230 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 231 complete_all(&dev->done); 232 233 dev_dbg(dev->device, "isr handled"); 234 return IRQ_HANDLED; 235 } 236 237 /* Wait for device to be ready */ 238 static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev) 239 { 240 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT); 241 242 while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) { 243 if (time_after(jiffies, timeout)) 244 return -ETIMEDOUT; 245 cpu_relax(); 246 } 247 return 0; 248 } 249 250 /* i2c xfer completion function, handles both irq and polling mode */ 251 static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev) 252 { 253 int ret = 0; 254 unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT); 255 256 if (dev->irq >= 0) { 257 if (!wait_for_completion_timeout(&dev->done, timeout)) 258 ret = -ETIMEDOUT; 259 } else { 260 /* we are in polling mode */ 261 u32 bsc_intrp; 262 unsigned long time_left = jiffies + timeout; 263 264 do { 265 bsc_intrp = bsc_readl(dev, iic_enable) & 266 BSC_IIC_EN_INTRP_MASK; 267 if (time_after(jiffies, time_left)) { 268 ret = -ETIMEDOUT; 269 break; 270 } 271 cpu_relax(); 272 } while (!bsc_intrp); 273 } 274 275 if (dev->irq < 0 || ret == -ETIMEDOUT) 276 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 277 278 return ret; 279 } 280 281 /* Set xfer START/STOP conditions for subsequent transfer */ 282 static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev, 283 u32 cond_flag) 284 { 285 u32 regval = dev->bsc_regmap->iic_enable; 286 287 dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag; 288 } 289 290 /* Send I2C request check completion */ 291 static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev, 292 enum bsc_xfer_cmd cmd) 293 { 294 int rc = 0; 295 struct bsc_regs *pi2creg = dev->bsc_regmap; 296 297 /* Make sure the hardware is ready */ 298 rc = brcmstb_i2c_wait_if_busy(dev); 299 if (rc < 0) 300 return rc; 301 302 /* only if we are in interrupt mode */ 303 if (dev->irq >= 0) 304 reinit_completion(&dev->done); 305 306 /* enable BSC CTL interrupt line */ 307 brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE); 308 309 /* initiate transfer by setting iic_enable */ 310 pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK; 311 bsc_writel(dev, pi2creg->iic_enable, iic_enable); 312 313 /* Wait for transaction to finish or timeout */ 314 rc = brcmstb_i2c_wait_for_completion(dev); 315 if (rc) { 316 dev_dbg(dev->device, "intr timeout for cmd %s\n", 317 cmd_string[cmd]); 318 goto cmd_out; 319 } 320 321 if ((CMD_RD || CMD_WR) && 322 bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) { 323 rc = -EREMOTEIO; 324 dev_dbg(dev->device, "controller received NOACK intr for %s\n", 325 cmd_string[cmd]); 326 } 327 328 cmd_out: 329 bsc_writel(dev, 0, cnt_reg); 330 bsc_writel(dev, 0, iic_enable); 331 332 return rc; 333 } 334 335 /* Actual data transfer through the BSC master */ 336 static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev, 337 u8 *buf, unsigned int len, 338 struct i2c_msg *pmsg) 339 { 340 int cnt, byte, i, rc; 341 enum bsc_xfer_cmd cmd; 342 u32 ctl_reg; 343 struct bsc_regs *pi2creg = dev->bsc_regmap; 344 int no_ack = pmsg->flags & I2C_M_IGNORE_NAK; 345 int data_regsz = brcmstb_i2c_get_data_regsz(dev); 346 int xfersz = brcmstb_i2c_get_xfersz(dev); 347 348 /* see if the transaction needs to check NACK conditions */ 349 if (no_ack || len <= xfersz) { 350 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK 351 : CMD_WR_NOACK; 352 pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK; 353 } else { 354 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR; 355 pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK; 356 } 357 bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg); 358 359 /* set data transfer direction */ 360 ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK; 361 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) 362 pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK; 363 else 364 pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK; 365 366 /* set the read/write length */ 367 bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) & 368 (len << BSC_CNT_REG1_SHIFT), cnt_reg); 369 370 /* Write data into data_in register */ 371 372 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) { 373 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) { 374 u32 word = 0; 375 376 for (byte = 0; byte < data_regsz; byte++) { 377 word >>= BITS_PER_BYTE; 378 if ((cnt + byte) < len) 379 word |= buf[cnt + byte] << 380 (BITS_PER_BYTE * (data_regsz - 1)); 381 } 382 bsc_writel(dev, word, data_in[i]); 383 } 384 } 385 386 /* Initiate xfer, the function will return on completion */ 387 rc = brcmstb_send_i2c_cmd(dev, cmd); 388 389 if (rc != 0) { 390 dev_dbg(dev->device, "%s failure", cmd_string[cmd]); 391 return rc; 392 } 393 394 /* Read data from data_out register */ 395 if (cmd == CMD_RD || cmd == CMD_RD_NOACK) { 396 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) { 397 u32 data = bsc_readl(dev, data_out[i]); 398 399 for (byte = 0; byte < data_regsz && 400 (byte + cnt) < len; byte++) { 401 buf[cnt + byte] = data & 0xff; 402 data >>= BITS_PER_BYTE; 403 } 404 } 405 } 406 407 return 0; 408 } 409 410 /* Write a single byte of data to the i2c bus */ 411 static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev, 412 u8 *buf, unsigned int nak_expected) 413 { 414 enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK; 415 416 bsc_writel(dev, 1, cnt_reg); 417 bsc_writel(dev, *buf, data_in); 418 419 return brcmstb_send_i2c_cmd(dev, cmd); 420 } 421 422 /* Send i2c address */ 423 static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev, 424 struct i2c_msg *msg) 425 { 426 unsigned char addr; 427 428 if (msg->flags & I2C_M_TEN) { 429 /* First byte is 11110XX0 where XX is upper 2 bits */ 430 addr = 0xF0 | ((msg->addr & 0x300) >> 7); 431 bsc_writel(dev, addr, chip_address); 432 433 /* Second byte is the remaining 8 bits */ 434 addr = msg->addr & 0xFF; 435 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0) 436 return -EREMOTEIO; 437 438 if (msg->flags & I2C_M_RD) { 439 /* For read, send restart without stop condition */ 440 brcmstb_set_i2c_start_stop(dev, COND_RESTART 441 | COND_NOSTOP); 442 /* Then re-send the first byte with the read bit set */ 443 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01; 444 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0) 445 return -EREMOTEIO; 446 447 } 448 } else { 449 addr = msg->addr << 1; 450 if (msg->flags & I2C_M_RD) 451 addr |= 1; 452 453 bsc_writel(dev, addr, chip_address); 454 } 455 456 return 0; 457 } 458 459 /* Master transfer function */ 460 static int brcmstb_i2c_xfer(struct i2c_adapter *adapter, 461 struct i2c_msg msgs[], int num) 462 { 463 struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter); 464 struct i2c_msg *pmsg; 465 int rc = 0; 466 int i; 467 int bytes_to_xfer; 468 u8 *tmp_buf; 469 int len = 0; 470 int xfersz = brcmstb_i2c_get_xfersz(dev); 471 472 if (dev->is_suspended) 473 return -EBUSY; 474 475 /* Loop through all messages */ 476 for (i = 0; i < num; i++) { 477 pmsg = &msgs[i]; 478 len = pmsg->len; 479 tmp_buf = pmsg->buf; 480 481 dev_dbg(dev->device, 482 "msg# %d/%d flg %x buf %x len %d\n", i, 483 num - 1, pmsg->flags, 484 pmsg->buf ? pmsg->buf[0] : '0', pmsg->len); 485 486 if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART)) 487 brcmstb_set_i2c_start_stop(dev, ~(COND_START_STOP)); 488 else 489 brcmstb_set_i2c_start_stop(dev, 490 COND_RESTART | COND_NOSTOP); 491 492 /* Send slave address */ 493 if (!(pmsg->flags & I2C_M_NOSTART)) { 494 rc = brcmstb_i2c_do_addr(dev, pmsg); 495 if (rc < 0) { 496 dev_dbg(dev->device, 497 "NACK for addr %2.2x msg#%d rc = %d\n", 498 pmsg->addr, i, rc); 499 goto out; 500 } 501 } 502 503 /* Perform data transfer */ 504 while (len) { 505 bytes_to_xfer = min(len, xfersz); 506 507 if (len <= xfersz && i == (num - 1)) 508 brcmstb_set_i2c_start_stop(dev, 509 ~(COND_START_STOP)); 510 511 rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf, 512 bytes_to_xfer, pmsg); 513 if (rc < 0) 514 goto out; 515 516 len -= bytes_to_xfer; 517 tmp_buf += bytes_to_xfer; 518 } 519 } 520 521 rc = num; 522 out: 523 return rc; 524 525 } 526 527 static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap) 528 { 529 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR 530 | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING; 531 } 532 533 static const struct i2c_algorithm brcmstb_i2c_algo = { 534 .master_xfer = brcmstb_i2c_xfer, 535 .functionality = brcmstb_i2c_functionality, 536 }; 537 538 static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev) 539 { 540 int i = 0, num_speeds = ARRAY_SIZE(bsc_clk); 541 u32 clk_freq_hz = dev->clk_freq_hz; 542 543 for (i = 0; i < num_speeds; i++) { 544 if (bsc_clk[i].hz == clk_freq_hz) { 545 dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK 546 | BSC_CTL_REG_DIV_CLK_MASK); 547 dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask | 548 bsc_clk[i].div_mask); 549 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); 550 break; 551 } 552 } 553 554 /* in case we did not get find a valid speed */ 555 if (i == num_speeds) { 556 i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >> 557 BSC_CTL_REG_SCL_SEL_SHIFT; 558 dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n", 559 bsc_clk[i].hz); 560 } 561 } 562 563 static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev) 564 { 565 if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32)) 566 /* set 4 byte data in/out xfers */ 567 dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK; 568 else 569 dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK; 570 571 bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg); 572 /* set bus speed */ 573 brcmstb_i2c_set_bus_speed(dev); 574 } 575 576 static int brcmstb_i2c_probe(struct platform_device *pdev) 577 { 578 int rc = 0; 579 struct brcmstb_i2c_dev *dev; 580 struct i2c_adapter *adap; 581 struct resource *iomem; 582 const char *int_name; 583 584 /* Allocate memory for private data structure */ 585 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 586 if (!dev) 587 return -ENOMEM; 588 589 dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL); 590 if (!dev->bsc_regmap) 591 return -ENOMEM; 592 593 platform_set_drvdata(pdev, dev); 594 dev->device = &pdev->dev; 595 init_completion(&dev->done); 596 597 /* Map hardware registers */ 598 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 599 dev->base = devm_ioremap_resource(dev->device, iomem); 600 if (IS_ERR(dev->base)) { 601 rc = -ENOMEM; 602 goto probe_errorout; 603 } 604 605 rc = of_property_read_string(dev->device->of_node, "interrupt-names", 606 &int_name); 607 if (rc < 0) 608 int_name = NULL; 609 610 /* Get the interrupt number */ 611 dev->irq = platform_get_irq(pdev, 0); 612 613 /* disable the bsc interrupt line */ 614 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 615 616 /* register the ISR handler */ 617 rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr, 618 IRQF_SHARED, 619 int_name ? int_name : pdev->name, 620 dev); 621 622 if (rc) { 623 dev_dbg(dev->device, "falling back to polling mode"); 624 dev->irq = -1; 625 } 626 627 if (of_property_read_u32(dev->device->of_node, 628 "clock-frequency", &dev->clk_freq_hz)) { 629 dev_warn(dev->device, "setting clock-frequency@%dHz\n", 630 bsc_clk[0].hz); 631 dev->clk_freq_hz = bsc_clk[0].hz; 632 } 633 634 /* set the data in/out register size for compatible SoCs */ 635 if (of_device_is_compatible(dev->device->of_node, 636 "brcmstb,brcmper-i2c")) 637 dev->data_regsz = sizeof(u8); 638 else 639 dev->data_regsz = sizeof(u32); 640 641 brcmstb_i2c_set_bsc_reg_defaults(dev); 642 643 /* Add the i2c adapter */ 644 adap = &dev->adapter; 645 i2c_set_adapdata(adap, dev); 646 adap->owner = THIS_MODULE; 647 strlcpy(adap->name, "Broadcom STB : ", sizeof(adap->name)); 648 if (int_name) 649 strlcat(adap->name, int_name, sizeof(adap->name)); 650 adap->algo = &brcmstb_i2c_algo; 651 adap->dev.parent = &pdev->dev; 652 adap->dev.of_node = pdev->dev.of_node; 653 rc = i2c_add_adapter(adap); 654 if (rc) { 655 dev_err(dev->device, "failed to add adapter\n"); 656 goto probe_errorout; 657 } 658 659 dev_info(dev->device, "%s@%dhz registered in %s mode\n", 660 int_name ? int_name : " ", dev->clk_freq_hz, 661 (dev->irq >= 0) ? "interrupt" : "polling"); 662 663 return 0; 664 665 probe_errorout: 666 return rc; 667 } 668 669 static int brcmstb_i2c_remove(struct platform_device *pdev) 670 { 671 struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev); 672 673 i2c_del_adapter(&dev->adapter); 674 return 0; 675 } 676 677 #ifdef CONFIG_PM_SLEEP 678 static int brcmstb_i2c_suspend(struct device *dev) 679 { 680 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); 681 682 i2c_lock_adapter(&i2c_dev->adapter); 683 i2c_dev->is_suspended = true; 684 i2c_unlock_adapter(&i2c_dev->adapter); 685 686 return 0; 687 } 688 689 static int brcmstb_i2c_resume(struct device *dev) 690 { 691 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); 692 693 i2c_lock_adapter(&i2c_dev->adapter); 694 brcmstb_i2c_set_bsc_reg_defaults(i2c_dev); 695 i2c_dev->is_suspended = false; 696 i2c_unlock_adapter(&i2c_dev->adapter); 697 698 return 0; 699 } 700 #endif 701 702 static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend, 703 brcmstb_i2c_resume); 704 705 static const struct of_device_id brcmstb_i2c_of_match[] = { 706 {.compatible = "brcm,brcmstb-i2c"}, 707 {.compatible = "brcm,brcmper-i2c"}, 708 {}, 709 }; 710 MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match); 711 712 static struct platform_driver brcmstb_i2c_driver = { 713 .driver = { 714 .name = "brcmstb-i2c", 715 .of_match_table = brcmstb_i2c_of_match, 716 .pm = &brcmstb_i2c_pm, 717 }, 718 .probe = brcmstb_i2c_probe, 719 .remove = brcmstb_i2c_remove, 720 }; 721 module_platform_driver(brcmstb_i2c_driver); 722 723 MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>"); 724 MODULE_DESCRIPTION("Broadcom Settop I2C Driver"); 725 MODULE_LICENSE("GPL v2"); 726