1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2014 Broadcom Corporation 3 4 #include <linux/clk.h> 5 #include <linux/delay.h> 6 #include <linux/device.h> 7 #include <linux/i2c.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/sched.h> 14 #include <linux/slab.h> 15 16 #define N_DATA_REGS 8 17 18 /* 19 * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register 20 * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per 21 * data register whereas STB SoCs use 4 byte per data register transfer, 22 * account for this difference in total count per transaction and mask to 23 * use. 24 */ 25 #define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0)) 26 #define BSC_CNT_REG1_SHIFT 0 27 28 /* BSC CTL register field definitions */ 29 #define BSC_CTL_REG_DTF_MASK 0x00000003 30 #define BSC_CTL_REG_SCL_SEL_MASK 0x00000030 31 #define BSC_CTL_REG_SCL_SEL_SHIFT 4 32 #define BSC_CTL_REG_INT_EN_MASK 0x00000040 33 #define BSC_CTL_REG_INT_EN_SHIFT 6 34 #define BSC_CTL_REG_DIV_CLK_MASK 0x00000080 35 36 /* BSC_IIC_ENABLE r/w enable and interrupt field definitions */ 37 #define BSC_IIC_EN_RESTART_MASK 0x00000040 38 #define BSC_IIC_EN_NOSTART_MASK 0x00000020 39 #define BSC_IIC_EN_NOSTOP_MASK 0x00000010 40 #define BSC_IIC_EN_NOACK_MASK 0x00000004 41 #define BSC_IIC_EN_INTRP_MASK 0x00000002 42 #define BSC_IIC_EN_ENABLE_MASK 0x00000001 43 44 /* BSC_CTLHI control register field definitions */ 45 #define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080 46 #define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040 47 #define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 48 #define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001 49 50 #define I2C_TIMEOUT 100 /* msecs */ 51 52 /* Condition mask used for non combined transfer */ 53 #define COND_RESTART BSC_IIC_EN_RESTART_MASK 54 #define COND_NOSTART BSC_IIC_EN_NOSTART_MASK 55 #define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK 56 #define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP) 57 58 /* BSC data transfer direction */ 59 #define DTF_WR_MASK 0x00000000 60 #define DTF_RD_MASK 0x00000001 61 /* BSC data transfer direction combined format */ 62 #define DTF_RD_WR_MASK 0x00000002 63 #define DTF_WR_RD_MASK 0x00000003 64 65 #define INT_ENABLE true 66 #define INT_DISABLE false 67 68 /* BSC block register map structure to cache fields to be written */ 69 struct bsc_regs { 70 u32 chip_address; /* slave address */ 71 u32 data_in[N_DATA_REGS]; /* tx data buffer*/ 72 u32 cnt_reg; /* rx/tx data length */ 73 u32 ctl_reg; /* control register */ 74 u32 iic_enable; /* xfer enable and status */ 75 u32 data_out[N_DATA_REGS]; /* rx data buffer */ 76 u32 ctlhi_reg; /* more control fields */ 77 u32 scl_param; /* reserved */ 78 }; 79 80 struct bsc_clk_param { 81 u32 hz; 82 u32 scl_mask; 83 u32 div_mask; 84 }; 85 86 enum bsc_xfer_cmd { 87 CMD_WR, 88 CMD_RD, 89 CMD_WR_NOACK, 90 CMD_RD_NOACK, 91 }; 92 93 static char const *cmd_string[] = { 94 [CMD_WR] = "WR", 95 [CMD_RD] = "RD", 96 [CMD_WR_NOACK] = "WR NOACK", 97 [CMD_RD_NOACK] = "RD NOACK", 98 }; 99 100 enum bus_speeds { 101 SPD_375K, 102 SPD_390K, 103 SPD_187K, 104 SPD_200K, 105 SPD_93K, 106 SPD_97K, 107 SPD_46K, 108 SPD_50K 109 }; 110 111 static const struct bsc_clk_param bsc_clk[] = { 112 [SPD_375K] = { 113 .hz = 375000, 114 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT, 115 .div_mask = 0 116 }, 117 [SPD_390K] = { 118 .hz = 390000, 119 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT, 120 .div_mask = 0 121 }, 122 [SPD_187K] = { 123 .hz = 187500, 124 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT, 125 .div_mask = 0 126 }, 127 [SPD_200K] = { 128 .hz = 200000, 129 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT, 130 .div_mask = 0 131 }, 132 [SPD_93K] = { 133 .hz = 93750, 134 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT, 135 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 136 }, 137 [SPD_97K] = { 138 .hz = 97500, 139 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT, 140 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 141 }, 142 [SPD_46K] = { 143 .hz = 46875, 144 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT, 145 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 146 }, 147 [SPD_50K] = { 148 .hz = 50000, 149 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT, 150 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 151 } 152 }; 153 154 struct brcmstb_i2c_dev { 155 struct device *device; 156 void __iomem *base; 157 int irq; 158 struct bsc_regs *bsc_regmap; 159 struct i2c_adapter adapter; 160 struct completion done; 161 u32 clk_freq_hz; 162 int data_regsz; 163 bool atomic; 164 }; 165 166 /* register accessors for both be and le cpu arch */ 167 #ifdef CONFIG_CPU_BIG_ENDIAN 168 #define __bsc_readl(_reg) ioread32be(_reg) 169 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) 170 #else 171 #define __bsc_readl(_reg) ioread32(_reg) 172 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) 173 #endif 174 175 #define bsc_readl(_dev, _reg) \ 176 __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg)) 177 178 #define bsc_writel(_dev, _val, _reg) \ 179 __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg)) 180 181 static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev) 182 { 183 return (N_DATA_REGS * dev->data_regsz); 184 } 185 186 static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev) 187 { 188 return dev->data_regsz; 189 } 190 191 static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev, 192 bool int_en) 193 { 194 195 if (int_en) 196 /* Enable BSC CTL interrupt line */ 197 dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK; 198 else 199 /* Disable BSC CTL interrupt line */ 200 dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK; 201 202 barrier(); 203 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); 204 } 205 206 static irqreturn_t brcmstb_i2c_isr(int irq, void *devid) 207 { 208 struct brcmstb_i2c_dev *dev = devid; 209 u32 status_bsc_ctl = bsc_readl(dev, ctl_reg); 210 u32 status_iic_intrp = bsc_readl(dev, iic_enable); 211 212 dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n", 213 status_bsc_ctl, status_iic_intrp); 214 215 if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK)) 216 return IRQ_NONE; 217 218 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 219 complete(&dev->done); 220 221 dev_dbg(dev->device, "isr handled"); 222 return IRQ_HANDLED; 223 } 224 225 /* Wait for device to be ready */ 226 static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev) 227 { 228 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT); 229 230 while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) { 231 if (time_after(jiffies, timeout)) 232 return -ETIMEDOUT; 233 cpu_relax(); 234 } 235 return 0; 236 } 237 238 /* i2c xfer completion function, handles both irq and polling mode */ 239 static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev) 240 { 241 int ret = 0; 242 unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT); 243 244 if (dev->irq >= 0 && !dev->atomic) { 245 if (!wait_for_completion_timeout(&dev->done, timeout)) 246 ret = -ETIMEDOUT; 247 } else { 248 /* we are in polling mode */ 249 u32 bsc_intrp; 250 unsigned long time_left = jiffies + timeout; 251 252 do { 253 bsc_intrp = bsc_readl(dev, iic_enable) & 254 BSC_IIC_EN_INTRP_MASK; 255 if (time_after(jiffies, time_left)) { 256 ret = -ETIMEDOUT; 257 break; 258 } 259 cpu_relax(); 260 } while (!bsc_intrp); 261 } 262 263 if (dev->irq < 0 || ret == -ETIMEDOUT) 264 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 265 266 return ret; 267 } 268 269 /* Set xfer START/STOP conditions for subsequent transfer */ 270 static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev, 271 u32 cond_flag) 272 { 273 u32 regval = dev->bsc_regmap->iic_enable; 274 275 dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag; 276 } 277 278 /* Send I2C request check completion */ 279 static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev, 280 enum bsc_xfer_cmd cmd) 281 { 282 int rc = 0; 283 struct bsc_regs *pi2creg = dev->bsc_regmap; 284 285 /* Make sure the hardware is ready */ 286 rc = brcmstb_i2c_wait_if_busy(dev); 287 if (rc < 0) 288 return rc; 289 290 /* only if we are in interrupt mode */ 291 if (dev->irq >= 0 && !dev->atomic) 292 reinit_completion(&dev->done); 293 294 /* enable BSC CTL interrupt line */ 295 brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE); 296 297 /* initiate transfer by setting iic_enable */ 298 pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK; 299 bsc_writel(dev, pi2creg->iic_enable, iic_enable); 300 301 /* Wait for transaction to finish or timeout */ 302 rc = brcmstb_i2c_wait_for_completion(dev); 303 if (rc) { 304 dev_dbg(dev->device, "intr timeout for cmd %s\n", 305 cmd_string[cmd]); 306 goto cmd_out; 307 } 308 309 if ((cmd == CMD_RD || cmd == CMD_WR) && 310 bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) { 311 rc = -EREMOTEIO; 312 dev_dbg(dev->device, "controller received NOACK intr for %s\n", 313 cmd_string[cmd]); 314 } 315 316 cmd_out: 317 bsc_writel(dev, 0, cnt_reg); 318 bsc_writel(dev, 0, iic_enable); 319 320 return rc; 321 } 322 323 /* Actual data transfer through the BSC master */ 324 static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev, 325 u8 *buf, unsigned int len, 326 struct i2c_msg *pmsg) 327 { 328 int cnt, byte, i, rc; 329 enum bsc_xfer_cmd cmd; 330 u32 ctl_reg; 331 struct bsc_regs *pi2creg = dev->bsc_regmap; 332 int no_ack = pmsg->flags & I2C_M_IGNORE_NAK; 333 int data_regsz = brcmstb_i2c_get_data_regsz(dev); 334 335 /* see if the transaction needs to check NACK conditions */ 336 if (no_ack) { 337 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK 338 : CMD_WR_NOACK; 339 pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK; 340 } else { 341 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR; 342 pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK; 343 } 344 bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg); 345 346 /* set data transfer direction */ 347 ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK; 348 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) 349 pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK; 350 else 351 pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK; 352 353 /* set the read/write length */ 354 bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) & 355 (len << BSC_CNT_REG1_SHIFT), cnt_reg); 356 357 /* Write data into data_in register */ 358 359 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) { 360 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) { 361 u32 word = 0; 362 363 for (byte = 0; byte < data_regsz; byte++) { 364 word >>= BITS_PER_BYTE; 365 if ((cnt + byte) < len) 366 word |= buf[cnt + byte] << 367 (BITS_PER_BYTE * (data_regsz - 1)); 368 } 369 bsc_writel(dev, word, data_in[i]); 370 } 371 } 372 373 /* Initiate xfer, the function will return on completion */ 374 rc = brcmstb_send_i2c_cmd(dev, cmd); 375 376 if (rc != 0) { 377 dev_dbg(dev->device, "%s failure", cmd_string[cmd]); 378 return rc; 379 } 380 381 /* Read data from data_out register */ 382 if (cmd == CMD_RD || cmd == CMD_RD_NOACK) { 383 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) { 384 u32 data = bsc_readl(dev, data_out[i]); 385 386 for (byte = 0; byte < data_regsz && 387 (byte + cnt) < len; byte++) { 388 buf[cnt + byte] = data & 0xff; 389 data >>= BITS_PER_BYTE; 390 } 391 } 392 } 393 394 return 0; 395 } 396 397 /* Write a single byte of data to the i2c bus */ 398 static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev, 399 u8 *buf, unsigned int nak_expected) 400 { 401 enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK; 402 403 bsc_writel(dev, 1, cnt_reg); 404 bsc_writel(dev, *buf, data_in); 405 406 return brcmstb_send_i2c_cmd(dev, cmd); 407 } 408 409 /* Send i2c address */ 410 static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev, 411 struct i2c_msg *msg) 412 { 413 unsigned char addr; 414 415 if (msg->flags & I2C_M_TEN) { 416 /* First byte is 11110XX0 where XX is upper 2 bits */ 417 addr = 0xF0 | ((msg->addr & 0x300) >> 7); 418 bsc_writel(dev, addr, chip_address); 419 420 /* Second byte is the remaining 8 bits */ 421 addr = msg->addr & 0xFF; 422 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0) 423 return -EREMOTEIO; 424 425 if (msg->flags & I2C_M_RD) { 426 /* For read, send restart without stop condition */ 427 brcmstb_set_i2c_start_stop(dev, COND_RESTART 428 | COND_NOSTOP); 429 /* Then re-send the first byte with the read bit set */ 430 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01; 431 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0) 432 return -EREMOTEIO; 433 434 } 435 } else { 436 addr = i2c_8bit_addr_from_msg(msg); 437 438 bsc_writel(dev, addr, chip_address); 439 } 440 441 return 0; 442 } 443 444 /* Master transfer function */ 445 static int brcmstb_i2c_xfer(struct i2c_adapter *adapter, 446 struct i2c_msg msgs[], int num) 447 { 448 struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter); 449 struct i2c_msg *pmsg; 450 int rc = 0; 451 int i; 452 int bytes_to_xfer; 453 u8 *tmp_buf; 454 int len = 0; 455 int xfersz = brcmstb_i2c_get_xfersz(dev); 456 u32 cond, cond_per_msg; 457 458 /* Loop through all messages */ 459 for (i = 0; i < num; i++) { 460 pmsg = &msgs[i]; 461 len = pmsg->len; 462 tmp_buf = pmsg->buf; 463 464 dev_dbg(dev->device, 465 "msg# %d/%d flg %x buf %x len %d\n", i, 466 num - 1, pmsg->flags, 467 pmsg->buf ? pmsg->buf[0] : '0', pmsg->len); 468 469 if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART)) 470 cond = ~COND_START_STOP; 471 else 472 cond = COND_RESTART | COND_NOSTOP; 473 474 brcmstb_set_i2c_start_stop(dev, cond); 475 476 /* Send slave address */ 477 if (!(pmsg->flags & I2C_M_NOSTART)) { 478 rc = brcmstb_i2c_do_addr(dev, pmsg); 479 if (rc < 0) { 480 dev_dbg(dev->device, 481 "NACK for addr %2.2x msg#%d rc = %d\n", 482 pmsg->addr, i, rc); 483 goto out; 484 } 485 } 486 487 cond_per_msg = cond; 488 489 /* Perform data transfer */ 490 while (len) { 491 bytes_to_xfer = min(len, xfersz); 492 493 if (len <= xfersz) { 494 if (i == (num - 1)) 495 cond_per_msg = cond_per_msg & 496 ~(COND_RESTART | COND_NOSTOP); 497 else 498 cond_per_msg = cond; 499 } else { 500 cond_per_msg = (cond_per_msg & ~COND_RESTART) | 501 COND_NOSTOP; 502 } 503 504 brcmstb_set_i2c_start_stop(dev, cond_per_msg); 505 506 rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf, 507 bytes_to_xfer, pmsg); 508 if (rc < 0) 509 goto out; 510 511 len -= bytes_to_xfer; 512 tmp_buf += bytes_to_xfer; 513 514 cond_per_msg = COND_NOSTART | COND_NOSTOP; 515 } 516 } 517 518 rc = num; 519 out: 520 return rc; 521 522 } 523 524 static int brcmstb_i2c_xfer_atomic(struct i2c_adapter *adapter, 525 struct i2c_msg msgs[], int num) 526 { 527 struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter); 528 int ret; 529 530 if (dev->irq >= 0) 531 disable_irq(dev->irq); 532 dev->atomic = true; 533 ret = brcmstb_i2c_xfer(adapter, msgs, num); 534 dev->atomic = false; 535 if (dev->irq >= 0) 536 enable_irq(dev->irq); 537 538 return ret; 539 } 540 541 static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap) 542 { 543 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR 544 | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING; 545 } 546 547 static const struct i2c_algorithm brcmstb_i2c_algo = { 548 .master_xfer = brcmstb_i2c_xfer, 549 .master_xfer_atomic = brcmstb_i2c_xfer_atomic, 550 .functionality = brcmstb_i2c_functionality, 551 }; 552 553 static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev) 554 { 555 int i = 0, num_speeds = ARRAY_SIZE(bsc_clk); 556 u32 clk_freq_hz = dev->clk_freq_hz; 557 558 for (i = 0; i < num_speeds; i++) { 559 if (bsc_clk[i].hz == clk_freq_hz) { 560 dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK 561 | BSC_CTL_REG_DIV_CLK_MASK); 562 dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask | 563 bsc_clk[i].div_mask); 564 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); 565 break; 566 } 567 } 568 569 /* in case we did not get find a valid speed */ 570 if (i == num_speeds) { 571 i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >> 572 BSC_CTL_REG_SCL_SEL_SHIFT; 573 dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n", 574 bsc_clk[i].hz); 575 } 576 } 577 578 static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev) 579 { 580 if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32)) 581 /* set 4 byte data in/out xfers */ 582 dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK; 583 else 584 dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK; 585 586 bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg); 587 /* set bus speed */ 588 brcmstb_i2c_set_bus_speed(dev); 589 } 590 591 #define AUTOI2C_CTRL0 0x26c 592 #define AUTOI2C_CTRL0_RELEASE_BSC BIT(1) 593 594 static int bcm2711_release_bsc(struct brcmstb_i2c_dev *dev) 595 { 596 struct platform_device *pdev = to_platform_device(dev->device); 597 void __iomem *autoi2c; 598 599 /* Map hardware registers */ 600 autoi2c = devm_platform_ioremap_resource_byname(pdev, "auto-i2c"); 601 if (IS_ERR(autoi2c)) 602 return PTR_ERR(autoi2c); 603 604 writel(AUTOI2C_CTRL0_RELEASE_BSC, autoi2c + AUTOI2C_CTRL0); 605 devm_iounmap(&pdev->dev, autoi2c); 606 607 /* We need to reset the controller after the release */ 608 dev->bsc_regmap->iic_enable = 0; 609 bsc_writel(dev, dev->bsc_regmap->iic_enable, iic_enable); 610 611 return 0; 612 } 613 614 static int brcmstb_i2c_probe(struct platform_device *pdev) 615 { 616 struct brcmstb_i2c_dev *dev; 617 struct i2c_adapter *adap; 618 const char *int_name; 619 int rc; 620 621 /* Allocate memory for private data structure */ 622 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 623 if (!dev) 624 return -ENOMEM; 625 626 dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL); 627 if (!dev->bsc_regmap) 628 return -ENOMEM; 629 630 platform_set_drvdata(pdev, dev); 631 dev->device = &pdev->dev; 632 init_completion(&dev->done); 633 634 /* Map hardware registers */ 635 dev->base = devm_platform_ioremap_resource(pdev, 0); 636 if (IS_ERR(dev->base)) 637 return PTR_ERR(dev->base); 638 639 if (of_device_is_compatible(dev->device->of_node, 640 "brcm,bcm2711-hdmi-i2c")) { 641 rc = bcm2711_release_bsc(dev); 642 if (rc) 643 return rc; 644 } 645 646 rc = of_property_read_string(dev->device->of_node, "interrupt-names", 647 &int_name); 648 if (rc < 0) 649 int_name = NULL; 650 651 /* Get the interrupt number */ 652 dev->irq = platform_get_irq_optional(pdev, 0); 653 654 /* disable the bsc interrupt line */ 655 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 656 657 /* register the ISR handler */ 658 if (dev->irq >= 0) { 659 rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr, 660 IRQF_SHARED, 661 int_name ? int_name : pdev->name, 662 dev); 663 664 if (rc) { 665 dev_dbg(dev->device, "falling back to polling mode"); 666 dev->irq = -1; 667 } 668 } 669 670 if (of_property_read_u32(dev->device->of_node, 671 "clock-frequency", &dev->clk_freq_hz)) { 672 dev_warn(dev->device, "setting clock-frequency@%dHz\n", 673 bsc_clk[0].hz); 674 dev->clk_freq_hz = bsc_clk[0].hz; 675 } 676 677 /* set the data in/out register size for compatible SoCs */ 678 if (of_device_is_compatible(dev->device->of_node, 679 "brcm,brcmper-i2c")) 680 dev->data_regsz = sizeof(u8); 681 else 682 dev->data_regsz = sizeof(u32); 683 684 brcmstb_i2c_set_bsc_reg_defaults(dev); 685 686 /* Add the i2c adapter */ 687 adap = &dev->adapter; 688 i2c_set_adapdata(adap, dev); 689 adap->owner = THIS_MODULE; 690 strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); 691 adap->algo = &brcmstb_i2c_algo; 692 adap->dev.parent = &pdev->dev; 693 adap->dev.of_node = pdev->dev.of_node; 694 rc = i2c_add_adapter(adap); 695 if (rc) 696 return rc; 697 698 dev_info(dev->device, "%s@%dhz registered in %s mode\n", 699 int_name ? int_name : " ", dev->clk_freq_hz, 700 (dev->irq >= 0) ? "interrupt" : "polling"); 701 702 return 0; 703 } 704 705 static void brcmstb_i2c_remove(struct platform_device *pdev) 706 { 707 struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev); 708 709 i2c_del_adapter(&dev->adapter); 710 } 711 712 static int brcmstb_i2c_suspend(struct device *dev) 713 { 714 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); 715 716 i2c_mark_adapter_suspended(&i2c_dev->adapter); 717 return 0; 718 } 719 720 static int brcmstb_i2c_resume(struct device *dev) 721 { 722 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); 723 724 brcmstb_i2c_set_bsc_reg_defaults(i2c_dev); 725 i2c_mark_adapter_resumed(&i2c_dev->adapter); 726 727 return 0; 728 } 729 730 static DEFINE_SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend, 731 brcmstb_i2c_resume); 732 733 static const struct of_device_id brcmstb_i2c_of_match[] = { 734 {.compatible = "brcm,brcmstb-i2c"}, 735 {.compatible = "brcm,brcmper-i2c"}, 736 {.compatible = "brcm,bcm2711-hdmi-i2c"}, 737 {}, 738 }; 739 MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match); 740 741 static struct platform_driver brcmstb_i2c_driver = { 742 .driver = { 743 .name = "brcmstb-i2c", 744 .of_match_table = brcmstb_i2c_of_match, 745 .pm = pm_sleep_ptr(&brcmstb_i2c_pm), 746 }, 747 .probe = brcmstb_i2c_probe, 748 .remove_new = brcmstb_i2c_remove, 749 }; 750 module_platform_driver(brcmstb_i2c_driver); 751 752 MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>"); 753 MODULE_DESCRIPTION("Broadcom Settop I2C Driver"); 754 MODULE_LICENSE("GPL v2"); 755