1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BCM2835 master mode driver 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/completion.h> 8 #include <linux/err.h> 9 #include <linux/i2c.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 16 #define BCM2835_I2C_C 0x0 17 #define BCM2835_I2C_S 0x4 18 #define BCM2835_I2C_DLEN 0x8 19 #define BCM2835_I2C_A 0xc 20 #define BCM2835_I2C_FIFO 0x10 21 #define BCM2835_I2C_DIV 0x14 22 #define BCM2835_I2C_DEL 0x18 23 #define BCM2835_I2C_CLKT 0x1c 24 25 #define BCM2835_I2C_C_READ BIT(0) 26 #define BCM2835_I2C_C_CLEAR BIT(4) /* bits 4 and 5 both clear */ 27 #define BCM2835_I2C_C_ST BIT(7) 28 #define BCM2835_I2C_C_INTD BIT(8) 29 #define BCM2835_I2C_C_INTT BIT(9) 30 #define BCM2835_I2C_C_INTR BIT(10) 31 #define BCM2835_I2C_C_I2CEN BIT(15) 32 33 #define BCM2835_I2C_S_TA BIT(0) 34 #define BCM2835_I2C_S_DONE BIT(1) 35 #define BCM2835_I2C_S_TXW BIT(2) 36 #define BCM2835_I2C_S_RXR BIT(3) 37 #define BCM2835_I2C_S_TXD BIT(4) 38 #define BCM2835_I2C_S_RXD BIT(5) 39 #define BCM2835_I2C_S_TXE BIT(6) 40 #define BCM2835_I2C_S_RXF BIT(7) 41 #define BCM2835_I2C_S_ERR BIT(8) 42 #define BCM2835_I2C_S_CLKT BIT(9) 43 #define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */ 44 45 #define BCM2835_I2C_FEDL_SHIFT 16 46 #define BCM2835_I2C_REDL_SHIFT 0 47 48 #define BCM2835_I2C_CDIV_MIN 0x0002 49 #define BCM2835_I2C_CDIV_MAX 0xFFFE 50 51 struct bcm2835_i2c_dev { 52 struct device *dev; 53 void __iomem *regs; 54 struct clk *clk; 55 int irq; 56 u32 bus_clk_rate; 57 struct i2c_adapter adapter; 58 struct completion completion; 59 struct i2c_msg *curr_msg; 60 int num_msgs; 61 u32 msg_err; 62 u8 *msg_buf; 63 size_t msg_buf_remaining; 64 }; 65 66 static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev, 67 u32 reg, u32 val) 68 { 69 writel(val, i2c_dev->regs + reg); 70 } 71 72 static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg) 73 { 74 return readl(i2c_dev->regs + reg); 75 } 76 77 static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev) 78 { 79 u32 divider, redl, fedl; 80 81 divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk), 82 i2c_dev->bus_clk_rate); 83 /* 84 * Per the datasheet, the register is always interpreted as an even 85 * number, by rounding down. In other words, the LSB is ignored. So, 86 * if the LSB is set, increment the divider to avoid any issue. 87 */ 88 if (divider & 1) 89 divider++; 90 if ((divider < BCM2835_I2C_CDIV_MIN) || 91 (divider > BCM2835_I2C_CDIV_MAX)) { 92 dev_err_ratelimited(i2c_dev->dev, "Invalid clock-frequency\n"); 93 return -EINVAL; 94 } 95 96 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider); 97 98 /* 99 * Number of core clocks to wait after falling edge before 100 * outputting the next data bit. Note that both FEDL and REDL 101 * can't be greater than CDIV/2. 102 */ 103 fedl = max(divider / 16, 1u); 104 105 /* 106 * Number of core clocks to wait after rising edge before 107 * sampling the next incoming data bit. 108 */ 109 redl = max(divider / 4, 1u); 110 111 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DEL, 112 (fedl << BCM2835_I2C_FEDL_SHIFT) | 113 (redl << BCM2835_I2C_REDL_SHIFT)); 114 return 0; 115 } 116 117 static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev) 118 { 119 u32 val; 120 121 while (i2c_dev->msg_buf_remaining) { 122 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 123 if (!(val & BCM2835_I2C_S_TXD)) 124 break; 125 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO, 126 *i2c_dev->msg_buf); 127 i2c_dev->msg_buf++; 128 i2c_dev->msg_buf_remaining--; 129 } 130 } 131 132 static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev) 133 { 134 u32 val; 135 136 while (i2c_dev->msg_buf_remaining) { 137 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 138 if (!(val & BCM2835_I2C_S_RXD)) 139 break; 140 *i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev, 141 BCM2835_I2C_FIFO); 142 i2c_dev->msg_buf++; 143 i2c_dev->msg_buf_remaining--; 144 } 145 } 146 147 /* 148 * Repeated Start Condition (Sr) 149 * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it 150 * talks about reading from a slave with 10 bit address. This is achieved by 151 * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then 152 * issue a read. 153 * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the 154 * firmware actually does it using polling and says that it's a workaround for 155 * a problem in the state machine. 156 * It turns out that it is possible to use the TXW interrupt to know when the 157 * transfer is active, provided the FIFO has not been prefilled. 158 */ 159 160 static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev) 161 { 162 u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN; 163 struct i2c_msg *msg = i2c_dev->curr_msg; 164 bool last_msg = (i2c_dev->num_msgs == 1); 165 166 if (!i2c_dev->num_msgs) 167 return; 168 169 i2c_dev->num_msgs--; 170 i2c_dev->msg_buf = msg->buf; 171 i2c_dev->msg_buf_remaining = msg->len; 172 173 if (msg->flags & I2C_M_RD) 174 c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR; 175 else 176 c |= BCM2835_I2C_C_INTT; 177 178 if (last_msg) 179 c |= BCM2835_I2C_C_INTD; 180 181 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr); 182 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len); 183 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c); 184 } 185 186 /* 187 * Note about I2C_C_CLEAR on error: 188 * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in 189 * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through 190 * the state machine to send a NACK and a STOP. Since we're setting CLEAR 191 * without I2CEN, that NACK will be hanging around queued up for next time 192 * we start the engine. 193 */ 194 195 static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data) 196 { 197 struct bcm2835_i2c_dev *i2c_dev = data; 198 u32 val, err; 199 200 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 201 202 err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR); 203 if (err) { 204 i2c_dev->msg_err = err; 205 goto complete; 206 } 207 208 if (val & BCM2835_I2C_S_DONE) { 209 if (!i2c_dev->curr_msg) { 210 dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n"); 211 } else if (i2c_dev->curr_msg->flags & I2C_M_RD) { 212 bcm2835_drain_rxfifo(i2c_dev); 213 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 214 } 215 216 if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining) 217 i2c_dev->msg_err = BCM2835_I2C_S_LEN; 218 else 219 i2c_dev->msg_err = 0; 220 goto complete; 221 } 222 223 if (val & BCM2835_I2C_S_TXW) { 224 if (!i2c_dev->msg_buf_remaining) { 225 i2c_dev->msg_err = val | BCM2835_I2C_S_LEN; 226 goto complete; 227 } 228 229 bcm2835_fill_txfifo(i2c_dev); 230 231 if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) { 232 i2c_dev->curr_msg++; 233 bcm2835_i2c_start_transfer(i2c_dev); 234 } 235 236 return IRQ_HANDLED; 237 } 238 239 if (val & BCM2835_I2C_S_RXR) { 240 if (!i2c_dev->msg_buf_remaining) { 241 i2c_dev->msg_err = val | BCM2835_I2C_S_LEN; 242 goto complete; 243 } 244 245 bcm2835_drain_rxfifo(i2c_dev); 246 return IRQ_HANDLED; 247 } 248 249 return IRQ_NONE; 250 251 complete: 252 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR); 253 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT | 254 BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE); 255 complete(&i2c_dev->completion); 256 257 return IRQ_HANDLED; 258 } 259 260 static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 261 int num) 262 { 263 struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 264 unsigned long time_left; 265 int i, ret; 266 267 for (i = 0; i < (num - 1); i++) 268 if (msgs[i].flags & I2C_M_RD) { 269 dev_warn_once(i2c_dev->dev, 270 "only one read message supported, has to be last\n"); 271 return -EOPNOTSUPP; 272 } 273 274 ret = bcm2835_i2c_set_divider(i2c_dev); 275 if (ret) 276 return ret; 277 278 i2c_dev->curr_msg = msgs; 279 i2c_dev->num_msgs = num; 280 reinit_completion(&i2c_dev->completion); 281 282 bcm2835_i2c_start_transfer(i2c_dev); 283 284 time_left = wait_for_completion_timeout(&i2c_dev->completion, 285 adap->timeout); 286 if (!time_left) { 287 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 288 BCM2835_I2C_C_CLEAR); 289 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 290 return -ETIMEDOUT; 291 } 292 293 if (!i2c_dev->msg_err) 294 return num; 295 296 dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err); 297 298 if (i2c_dev->msg_err & BCM2835_I2C_S_ERR) 299 return -EREMOTEIO; 300 301 return -EIO; 302 } 303 304 static u32 bcm2835_i2c_func(struct i2c_adapter *adap) 305 { 306 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 307 } 308 309 static const struct i2c_algorithm bcm2835_i2c_algo = { 310 .master_xfer = bcm2835_i2c_xfer, 311 .functionality = bcm2835_i2c_func, 312 }; 313 314 /* 315 * This HW was reported to have problems with clock stretching: 316 * http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html 317 * https://www.raspberrypi.org/forums/viewtopic.php?p=146272 318 */ 319 static const struct i2c_adapter_quirks bcm2835_i2c_quirks = { 320 .flags = I2C_AQ_NO_CLK_STRETCH, 321 }; 322 323 static int bcm2835_i2c_probe(struct platform_device *pdev) 324 { 325 struct bcm2835_i2c_dev *i2c_dev; 326 struct resource *mem, *irq; 327 int ret; 328 struct i2c_adapter *adap; 329 330 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 331 if (!i2c_dev) 332 return -ENOMEM; 333 platform_set_drvdata(pdev, i2c_dev); 334 i2c_dev->dev = &pdev->dev; 335 init_completion(&i2c_dev->completion); 336 337 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 338 i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem); 339 if (IS_ERR(i2c_dev->regs)) 340 return PTR_ERR(i2c_dev->regs); 341 342 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 343 if (IS_ERR(i2c_dev->clk)) { 344 if (PTR_ERR(i2c_dev->clk) != -EPROBE_DEFER) 345 dev_err(&pdev->dev, "Could not get clock\n"); 346 return PTR_ERR(i2c_dev->clk); 347 } 348 349 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 350 &i2c_dev->bus_clk_rate); 351 if (ret < 0) { 352 dev_warn(&pdev->dev, 353 "Could not read clock-frequency property\n"); 354 i2c_dev->bus_clk_rate = 100000; 355 } 356 357 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 358 if (!irq) { 359 dev_err(&pdev->dev, "No IRQ resource\n"); 360 return -ENODEV; 361 } 362 i2c_dev->irq = irq->start; 363 364 ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED, 365 dev_name(&pdev->dev), i2c_dev); 366 if (ret) { 367 dev_err(&pdev->dev, "Could not request IRQ\n"); 368 return -ENODEV; 369 } 370 371 adap = &i2c_dev->adapter; 372 i2c_set_adapdata(adap, i2c_dev); 373 adap->owner = THIS_MODULE; 374 adap->class = I2C_CLASS_DEPRECATED; 375 strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name)); 376 adap->algo = &bcm2835_i2c_algo; 377 adap->dev.parent = &pdev->dev; 378 adap->dev.of_node = pdev->dev.of_node; 379 adap->quirks = &bcm2835_i2c_quirks; 380 381 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0); 382 383 ret = i2c_add_adapter(adap); 384 if (ret) 385 free_irq(i2c_dev->irq, i2c_dev); 386 387 return ret; 388 } 389 390 static int bcm2835_i2c_remove(struct platform_device *pdev) 391 { 392 struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 393 394 free_irq(i2c_dev->irq, i2c_dev); 395 i2c_del_adapter(&i2c_dev->adapter); 396 397 return 0; 398 } 399 400 static const struct of_device_id bcm2835_i2c_of_match[] = { 401 { .compatible = "brcm,bcm2835-i2c" }, 402 {}, 403 }; 404 MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match); 405 406 static struct platform_driver bcm2835_i2c_driver = { 407 .probe = bcm2835_i2c_probe, 408 .remove = bcm2835_i2c_remove, 409 .driver = { 410 .name = "i2c-bcm2835", 411 .of_match_table = bcm2835_i2c_of_match, 412 }, 413 }; 414 module_platform_driver(bcm2835_i2c_driver); 415 416 MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>"); 417 MODULE_DESCRIPTION("BCM2835 I2C bus adapter"); 418 MODULE_LICENSE("GPL v2"); 419 MODULE_ALIAS("platform:i2c-bcm2835"); 420