1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2013 Broadcom Corporation 3 4 #include <linux/device.h> 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/sched.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/platform_device.h> 11 #include <linux/clk.h> 12 #include <linux/io.h> 13 #include <linux/slab.h> 14 15 /* Hardware register offsets and field defintions */ 16 #define CS_OFFSET 0x00000020 17 #define CS_ACK_SHIFT 3 18 #define CS_ACK_MASK 0x00000008 19 #define CS_ACK_CMD_GEN_START 0x00000000 20 #define CS_ACK_CMD_GEN_RESTART 0x00000001 21 #define CS_CMD_SHIFT 1 22 #define CS_CMD_CMD_NO_ACTION 0x00000000 23 #define CS_CMD_CMD_START_RESTART 0x00000001 24 #define CS_CMD_CMD_STOP 0x00000002 25 #define CS_EN_SHIFT 0 26 #define CS_EN_CMD_ENABLE_BSC 0x00000001 27 28 #define TIM_OFFSET 0x00000024 29 #define TIM_PRESCALE_SHIFT 6 30 #define TIM_P_SHIFT 3 31 #define TIM_NO_DIV_SHIFT 2 32 #define TIM_DIV_SHIFT 0 33 34 #define DAT_OFFSET 0x00000028 35 36 #define TOUT_OFFSET 0x0000002c 37 38 #define TXFCR_OFFSET 0x0000003c 39 #define TXFCR_FIFO_FLUSH_MASK 0x00000080 40 #define TXFCR_FIFO_EN_MASK 0x00000040 41 42 #define IER_OFFSET 0x00000044 43 #define IER_READ_COMPLETE_INT_MASK 0x00000010 44 #define IER_I2C_INT_EN_MASK 0x00000008 45 #define IER_FIFO_INT_EN_MASK 0x00000002 46 #define IER_NOACK_EN_MASK 0x00000001 47 48 #define ISR_OFFSET 0x00000048 49 #define ISR_RESERVED_MASK 0xffffff60 50 #define ISR_CMDBUSY_MASK 0x00000080 51 #define ISR_READ_COMPLETE_MASK 0x00000010 52 #define ISR_SES_DONE_MASK 0x00000008 53 #define ISR_ERR_MASK 0x00000004 54 #define ISR_TXFIFOEMPTY_MASK 0x00000002 55 #define ISR_NOACK_MASK 0x00000001 56 57 #define CLKEN_OFFSET 0x0000004C 58 #define CLKEN_AUTOSENSE_OFF_MASK 0x00000080 59 #define CLKEN_M_SHIFT 4 60 #define CLKEN_N_SHIFT 1 61 #define CLKEN_CLKEN_MASK 0x00000001 62 63 #define FIFO_STATUS_OFFSET 0x00000054 64 #define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004 65 #define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010 66 67 #define HSTIM_OFFSET 0x00000058 68 #define HSTIM_HS_MODE_MASK 0x00008000 69 #define HSTIM_HS_HOLD_SHIFT 10 70 #define HSTIM_HS_HIGH_PHASE_SHIFT 5 71 #define HSTIM_HS_SETUP_SHIFT 0 72 73 #define PADCTL_OFFSET 0x0000005c 74 #define PADCTL_PAD_OUT_EN_MASK 0x00000004 75 76 #define RXFCR_OFFSET 0x00000068 77 #define RXFCR_NACK_EN_SHIFT 7 78 #define RXFCR_READ_COUNT_SHIFT 0 79 #define RXFIFORDOUT_OFFSET 0x0000006c 80 81 /* Locally used constants */ 82 #define MAX_RX_FIFO_SIZE 64U /* bytes */ 83 #define MAX_TX_FIFO_SIZE 64U /* bytes */ 84 85 #define STD_EXT_CLK_FREQ 13000000UL 86 #define HS_EXT_CLK_FREQ 104000000UL 87 88 #define CONTROLLER_CODE 0x08 /* Controller codes are 0000_1xxxb */ 89 90 #define I2C_TIMEOUT 100 /* msecs */ 91 92 /* Operations that can be commanded to the controller */ 93 enum bcm_kona_cmd_t { 94 BCM_CMD_NOACTION = 0, 95 BCM_CMD_START, 96 BCM_CMD_RESTART, 97 BCM_CMD_STOP, 98 }; 99 100 enum bus_speed_index { 101 BCM_SPD_100K = 0, 102 BCM_SPD_400K, 103 BCM_SPD_1MHZ, 104 }; 105 106 enum hs_bus_speed_index { 107 BCM_SPD_3P4MHZ = 0, 108 }; 109 110 /* Internal divider settings for standard mode, fast mode and fast mode plus */ 111 struct bus_speed_cfg { 112 uint8_t time_m; /* Number of cycles for setup time */ 113 uint8_t time_n; /* Number of cycles for hold time */ 114 uint8_t prescale; /* Prescale divider */ 115 uint8_t time_p; /* Timing coefficient */ 116 uint8_t no_div; /* Disable clock divider */ 117 uint8_t time_div; /* Post-prescale divider */ 118 }; 119 120 /* Internal divider settings for high-speed mode */ 121 struct hs_bus_speed_cfg { 122 uint8_t hs_hold; /* Number of clock cycles SCL stays low until 123 the end of bit period */ 124 uint8_t hs_high_phase; /* Number of clock cycles SCL stays high 125 before it falls */ 126 uint8_t hs_setup; /* Number of clock cycles SCL stays low 127 before it rises */ 128 uint8_t prescale; /* Prescale divider */ 129 uint8_t time_p; /* Timing coefficient */ 130 uint8_t no_div; /* Disable clock divider */ 131 uint8_t time_div; /* Post-prescale divider */ 132 }; 133 134 static const struct bus_speed_cfg std_cfg_table[] = { 135 [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02}, 136 [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02}, 137 [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03}, 138 }; 139 140 static const struct hs_bus_speed_cfg hs_cfg_table[] = { 141 [BCM_SPD_3P4MHZ] = {0x01, 0x08, 0x14, 0x00, 0x06, 0x01, 0x00}, 142 }; 143 144 struct bcm_kona_i2c_dev { 145 struct device *device; 146 147 void __iomem *base; 148 int irq; 149 struct clk *external_clk; 150 151 struct i2c_adapter adapter; 152 153 struct completion done; 154 155 const struct bus_speed_cfg *std_cfg; 156 const struct hs_bus_speed_cfg *hs_cfg; 157 }; 158 159 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev, 160 enum bcm_kona_cmd_t cmd) 161 { 162 dev_dbg(dev->device, "%s, %d\n", __func__, cmd); 163 164 switch (cmd) { 165 case BCM_CMD_NOACTION: 166 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | 167 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), 168 dev->base + CS_OFFSET); 169 break; 170 171 case BCM_CMD_START: 172 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | 173 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | 174 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), 175 dev->base + CS_OFFSET); 176 break; 177 178 case BCM_CMD_RESTART: 179 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | 180 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | 181 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), 182 dev->base + CS_OFFSET); 183 break; 184 185 case BCM_CMD_STOP: 186 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | 187 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), 188 dev->base + CS_OFFSET); 189 break; 190 191 default: 192 dev_err(dev->device, "Unknown command %d\n", cmd); 193 } 194 } 195 196 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev) 197 { 198 writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, 199 dev->base + CLKEN_OFFSET); 200 } 201 202 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev) 203 { 204 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, 205 dev->base + CLKEN_OFFSET); 206 } 207 208 static irqreturn_t bcm_kona_i2c_isr(int irq, void *devid) 209 { 210 struct bcm_kona_i2c_dev *dev = devid; 211 uint32_t status = readl(dev->base + ISR_OFFSET); 212 213 if ((status & ~ISR_RESERVED_MASK) == 0) 214 return IRQ_NONE; 215 216 /* Must flush the TX FIFO when NAK detected */ 217 if (status & ISR_NOACK_MASK) 218 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, 219 dev->base + TXFCR_OFFSET); 220 221 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); 222 complete(&dev->done); 223 224 return IRQ_HANDLED; 225 } 226 227 /* Wait for ISR_CMDBUSY_MASK to go low before writing to CS, DAT, or RCD */ 228 static int bcm_kona_i2c_wait_if_busy(struct bcm_kona_i2c_dev *dev) 229 { 230 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT); 231 232 while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK) 233 if (time_after(jiffies, timeout)) { 234 dev_err(dev->device, "CMDBUSY timeout\n"); 235 return -ETIMEDOUT; 236 } 237 238 return 0; 239 } 240 241 /* Send command to I2C bus */ 242 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev, 243 enum bcm_kona_cmd_t cmd) 244 { 245 int rc; 246 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); 247 248 /* Make sure the hardware is ready */ 249 rc = bcm_kona_i2c_wait_if_busy(dev); 250 if (rc < 0) 251 return rc; 252 253 /* Unmask the session done interrupt */ 254 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); 255 256 /* Mark as incomplete before sending the command */ 257 reinit_completion(&dev->done); 258 259 /* Send the command */ 260 bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd); 261 262 /* Wait for transaction to finish or timeout */ 263 time_left = wait_for_completion_timeout(&dev->done, time_left); 264 265 /* Mask all interrupts */ 266 writel(0, dev->base + IER_OFFSET); 267 268 if (!time_left) { 269 dev_err(dev->device, "controller timed out\n"); 270 rc = -ETIMEDOUT; 271 } 272 273 /* Clear command */ 274 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); 275 276 return rc; 277 } 278 279 /* Read a single RX FIFO worth of data from the i2c bus */ 280 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, 281 uint8_t *buf, unsigned int len, 282 unsigned int last_byte_nak) 283 { 284 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); 285 286 /* Mark as incomplete before starting the RX FIFO */ 287 reinit_completion(&dev->done); 288 289 /* Unmask the read complete interrupt */ 290 writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET); 291 292 /* Start the RX FIFO */ 293 writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | 294 (len << RXFCR_READ_COUNT_SHIFT), 295 dev->base + RXFCR_OFFSET); 296 297 /* Wait for FIFO read to complete */ 298 time_left = wait_for_completion_timeout(&dev->done, time_left); 299 300 /* Mask all interrupts */ 301 writel(0, dev->base + IER_OFFSET); 302 303 if (!time_left) { 304 dev_err(dev->device, "RX FIFO time out\n"); 305 return -EREMOTEIO; 306 } 307 308 /* Read data from FIFO */ 309 for (; len > 0; len--, buf++) 310 *buf = readl(dev->base + RXFIFORDOUT_OFFSET); 311 312 return 0; 313 } 314 315 /* Read any amount of data using the RX FIFO from the i2c bus */ 316 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, 317 struct i2c_msg *msg) 318 { 319 unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; 320 unsigned int last_byte_nak = 0; 321 unsigned int bytes_read = 0; 322 int rc; 323 324 uint8_t *tmp_buf = msg->buf; 325 326 while (bytes_read < msg->len) { 327 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) { 328 last_byte_nak = 1; /* NAK last byte of transfer */ 329 bytes_to_read = msg->len - bytes_read; 330 } 331 332 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read, 333 last_byte_nak); 334 if (rc < 0) 335 return -EREMOTEIO; 336 337 bytes_read += bytes_to_read; 338 tmp_buf += bytes_to_read; 339 } 340 341 return 0; 342 } 343 344 /* Write a single byte of data to the i2c bus */ 345 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data, 346 unsigned int nak_expected) 347 { 348 int rc; 349 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); 350 unsigned int nak_received; 351 352 /* Make sure the hardware is ready */ 353 rc = bcm_kona_i2c_wait_if_busy(dev); 354 if (rc < 0) 355 return rc; 356 357 /* Clear pending session done interrupt */ 358 writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); 359 360 /* Unmask the session done interrupt */ 361 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); 362 363 /* Mark as incomplete before sending the data */ 364 reinit_completion(&dev->done); 365 366 /* Send one byte of data */ 367 writel(data, dev->base + DAT_OFFSET); 368 369 /* Wait for byte to be written */ 370 time_left = wait_for_completion_timeout(&dev->done, time_left); 371 372 /* Mask all interrupts */ 373 writel(0, dev->base + IER_OFFSET); 374 375 if (!time_left) { 376 dev_dbg(dev->device, "controller timed out\n"); 377 return -ETIMEDOUT; 378 } 379 380 nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; 381 382 if (nak_received ^ nak_expected) { 383 dev_dbg(dev->device, "unexpected NAK/ACK\n"); 384 return -EREMOTEIO; 385 } 386 387 return 0; 388 } 389 390 /* Write a single TX FIFO worth of data to the i2c bus */ 391 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, 392 uint8_t *buf, unsigned int len) 393 { 394 int k; 395 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); 396 unsigned int fifo_status; 397 398 /* Mark as incomplete before sending data to the TX FIFO */ 399 reinit_completion(&dev->done); 400 401 /* Unmask the fifo empty and nak interrupt */ 402 writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK, 403 dev->base + IER_OFFSET); 404 405 /* Disable IRQ to load a FIFO worth of data without interruption */ 406 disable_irq(dev->irq); 407 408 /* Write data into FIFO */ 409 for (k = 0; k < len; k++) 410 writel(buf[k], (dev->base + DAT_OFFSET)); 411 412 /* Enable IRQ now that data has been loaded */ 413 enable_irq(dev->irq); 414 415 /* Wait for FIFO to empty */ 416 do { 417 time_left = wait_for_completion_timeout(&dev->done, time_left); 418 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); 419 } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK)); 420 421 /* Mask all interrupts */ 422 writel(0, dev->base + IER_OFFSET); 423 424 /* Check if there was a NAK */ 425 if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { 426 dev_err(dev->device, "unexpected NAK\n"); 427 return -EREMOTEIO; 428 } 429 430 /* Check if a timeout occured */ 431 if (!time_left) { 432 dev_err(dev->device, "completion timed out\n"); 433 return -EREMOTEIO; 434 } 435 436 return 0; 437 } 438 439 440 /* Write any amount of data using TX FIFO to the i2c bus */ 441 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, 442 struct i2c_msg *msg) 443 { 444 unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; 445 unsigned int bytes_written = 0; 446 int rc; 447 448 uint8_t *tmp_buf = msg->buf; 449 450 while (bytes_written < msg->len) { 451 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE) 452 bytes_to_write = msg->len - bytes_written; 453 454 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf, 455 bytes_to_write); 456 if (rc < 0) 457 return -EREMOTEIO; 458 459 bytes_written += bytes_to_write; 460 tmp_buf += bytes_to_write; 461 } 462 463 return 0; 464 } 465 466 /* Send i2c address */ 467 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, 468 struct i2c_msg *msg) 469 { 470 unsigned char addr; 471 472 if (msg->flags & I2C_M_TEN) { 473 /* First byte is 11110XX0 where XX is upper 2 bits */ 474 addr = 0xF0 | ((msg->addr & 0x300) >> 7); 475 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) 476 return -EREMOTEIO; 477 478 /* Second byte is the remaining 8 bits */ 479 addr = msg->addr & 0xFF; 480 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) 481 return -EREMOTEIO; 482 483 if (msg->flags & I2C_M_RD) { 484 /* For read, send restart command */ 485 if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0) 486 return -EREMOTEIO; 487 488 /* Then re-send the first byte with the read bit set */ 489 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01; 490 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) 491 return -EREMOTEIO; 492 } 493 } else { 494 addr = i2c_8bit_addr_from_msg(msg); 495 496 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) 497 return -EREMOTEIO; 498 } 499 500 return 0; 501 } 502 503 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev) 504 { 505 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, 506 dev->base + CLKEN_OFFSET); 507 } 508 509 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) 510 { 511 writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, 512 dev->base + HSTIM_OFFSET); 513 514 writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | 515 (dev->std_cfg->time_p << TIM_P_SHIFT) | 516 (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) | 517 (dev->std_cfg->time_div << TIM_DIV_SHIFT), 518 dev->base + TIM_OFFSET); 519 520 writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | 521 (dev->std_cfg->time_n << CLKEN_N_SHIFT) | 522 CLKEN_CLKEN_MASK, 523 dev->base + CLKEN_OFFSET); 524 } 525 526 static void bcm_kona_i2c_config_timing_hs(struct bcm_kona_i2c_dev *dev) 527 { 528 writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) | 529 (dev->hs_cfg->time_p << TIM_P_SHIFT) | 530 (dev->hs_cfg->no_div << TIM_NO_DIV_SHIFT) | 531 (dev->hs_cfg->time_div << TIM_DIV_SHIFT), 532 dev->base + TIM_OFFSET); 533 534 writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) | 535 (dev->hs_cfg->hs_high_phase << HSTIM_HS_HIGH_PHASE_SHIFT) | 536 (dev->hs_cfg->hs_setup << HSTIM_HS_SETUP_SHIFT), 537 dev->base + HSTIM_OFFSET); 538 539 writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK, 540 dev->base + HSTIM_OFFSET); 541 } 542 543 static int bcm_kona_i2c_switch_to_hs(struct bcm_kona_i2c_dev *dev) 544 { 545 int rc; 546 547 /* Send controller code at standard speed */ 548 rc = bcm_kona_i2c_write_byte(dev, CONTROLLER_CODE, 1); 549 if (rc < 0) { 550 pr_err("High speed handshake failed\n"); 551 return rc; 552 } 553 554 /* Configure external clock to higher frequency */ 555 rc = clk_set_rate(dev->external_clk, HS_EXT_CLK_FREQ); 556 if (rc) { 557 dev_err(dev->device, "%s: clk_set_rate returned %d\n", 558 __func__, rc); 559 return rc; 560 } 561 562 /* Reconfigure internal dividers */ 563 bcm_kona_i2c_config_timing_hs(dev); 564 565 /* Send a restart command */ 566 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); 567 if (rc < 0) 568 dev_err(dev->device, "High speed restart command failed\n"); 569 570 return rc; 571 } 572 573 static int bcm_kona_i2c_switch_to_std(struct bcm_kona_i2c_dev *dev) 574 { 575 int rc; 576 577 /* Reconfigure internal dividers */ 578 bcm_kona_i2c_config_timing(dev); 579 580 /* Configure external clock to lower frequency */ 581 rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ); 582 if (rc) { 583 dev_err(dev->device, "%s: clk_set_rate returned %d\n", 584 __func__, rc); 585 } 586 587 return rc; 588 } 589 590 static int bcm_kona_i2c_xfer(struct i2c_adapter *adapter, 591 struct i2c_msg msgs[], int num) 592 { 593 struct bcm_kona_i2c_dev *dev = i2c_get_adapdata(adapter); 594 struct i2c_msg *pmsg; 595 int rc = 0; 596 int i; 597 598 rc = clk_prepare_enable(dev->external_clk); 599 if (rc) { 600 dev_err(dev->device, "%s: peri clock enable failed. err %d\n", 601 __func__, rc); 602 return rc; 603 } 604 605 /* Enable pad output */ 606 writel(0, dev->base + PADCTL_OFFSET); 607 608 /* Enable internal clocks */ 609 bcm_kona_i2c_enable_clock(dev); 610 611 /* Send start command */ 612 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START); 613 if (rc < 0) { 614 dev_err(dev->device, "Start command failed rc = %d\n", rc); 615 goto xfer_disable_pad; 616 } 617 618 /* Switch to high speed if applicable */ 619 if (dev->hs_cfg) { 620 rc = bcm_kona_i2c_switch_to_hs(dev); 621 if (rc < 0) 622 goto xfer_send_stop; 623 } 624 625 /* Loop through all messages */ 626 for (i = 0; i < num; i++) { 627 pmsg = &msgs[i]; 628 629 /* Send restart for subsequent messages */ 630 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) { 631 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); 632 if (rc < 0) { 633 dev_err(dev->device, 634 "restart cmd failed rc = %d\n", rc); 635 goto xfer_send_stop; 636 } 637 } 638 639 /* Send target address */ 640 if (!(pmsg->flags & I2C_M_NOSTART)) { 641 rc = bcm_kona_i2c_do_addr(dev, pmsg); 642 if (rc < 0) { 643 dev_err(dev->device, 644 "NAK from addr %2.2x msg#%d rc = %d\n", 645 pmsg->addr, i, rc); 646 goto xfer_send_stop; 647 } 648 } 649 650 /* Perform data transfer */ 651 if (pmsg->flags & I2C_M_RD) { 652 rc = bcm_kona_i2c_read_fifo(dev, pmsg); 653 if (rc < 0) { 654 dev_err(dev->device, "read failure\n"); 655 goto xfer_send_stop; 656 } 657 } else { 658 rc = bcm_kona_i2c_write_fifo(dev, pmsg); 659 if (rc < 0) { 660 dev_err(dev->device, "write failure"); 661 goto xfer_send_stop; 662 } 663 } 664 } 665 666 rc = num; 667 668 xfer_send_stop: 669 /* Send a STOP command */ 670 bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP); 671 672 /* Return from high speed if applicable */ 673 if (dev->hs_cfg) { 674 int hs_rc = bcm_kona_i2c_switch_to_std(dev); 675 676 if (hs_rc) 677 rc = hs_rc; 678 } 679 680 xfer_disable_pad: 681 /* Disable pad output */ 682 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); 683 684 /* Stop internal clock */ 685 bcm_kona_i2c_disable_clock(dev); 686 687 clk_disable_unprepare(dev->external_clk); 688 689 return rc; 690 } 691 692 static uint32_t bcm_kona_i2c_functionality(struct i2c_adapter *adap) 693 { 694 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | 695 I2C_FUNC_NOSTART; 696 } 697 698 static const struct i2c_algorithm bcm_algo = { 699 .xfer = bcm_kona_i2c_xfer, 700 .functionality = bcm_kona_i2c_functionality, 701 }; 702 703 static int bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev) 704 { 705 unsigned int bus_speed; 706 int ret = of_property_read_u32(dev->device->of_node, "clock-frequency", 707 &bus_speed); 708 if (ret < 0) { 709 dev_err(dev->device, "missing clock-frequency property\n"); 710 return -ENODEV; 711 } 712 713 switch (bus_speed) { 714 case I2C_MAX_STANDARD_MODE_FREQ: 715 dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; 716 break; 717 case I2C_MAX_FAST_MODE_FREQ: 718 dev->std_cfg = &std_cfg_table[BCM_SPD_400K]; 719 break; 720 case I2C_MAX_FAST_MODE_PLUS_FREQ: 721 dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ]; 722 break; 723 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 724 /* Send controller code at 100k */ 725 dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; 726 dev->hs_cfg = &hs_cfg_table[BCM_SPD_3P4MHZ]; 727 break; 728 default: 729 pr_err("%d hz bus speed not supported\n", bus_speed); 730 pr_err("Valid speeds are 100khz, 400khz, 1mhz, and 3.4mhz\n"); 731 return -EINVAL; 732 } 733 734 return 0; 735 } 736 737 static int bcm_kona_i2c_probe(struct platform_device *pdev) 738 { 739 int rc = 0; 740 struct bcm_kona_i2c_dev *dev; 741 struct i2c_adapter *adap; 742 743 /* Allocate memory for private data structure */ 744 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 745 if (!dev) 746 return -ENOMEM; 747 748 platform_set_drvdata(pdev, dev); 749 dev->device = &pdev->dev; 750 init_completion(&dev->done); 751 752 /* Map hardware registers */ 753 dev->base = devm_platform_ioremap_resource(pdev, 0); 754 if (IS_ERR(dev->base)) 755 return PTR_ERR(dev->base); 756 757 /* Get and enable external clock */ 758 dev->external_clk = devm_clk_get(dev->device, NULL); 759 if (IS_ERR(dev->external_clk)) { 760 dev_err(dev->device, "couldn't get clock\n"); 761 return -ENODEV; 762 } 763 764 rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ); 765 if (rc) { 766 dev_err(dev->device, "%s: clk_set_rate returned %d\n", 767 __func__, rc); 768 return rc; 769 } 770 771 rc = clk_prepare_enable(dev->external_clk); 772 if (rc) { 773 dev_err(dev->device, "couldn't enable clock\n"); 774 return rc; 775 } 776 777 /* Parse bus speed */ 778 rc = bcm_kona_i2c_assign_bus_speed(dev); 779 if (rc) 780 goto probe_disable_clk; 781 782 /* Enable internal clocks */ 783 bcm_kona_i2c_enable_clock(dev); 784 785 /* Configure internal dividers */ 786 bcm_kona_i2c_config_timing(dev); 787 788 /* Disable timeout */ 789 writel(0, dev->base + TOUT_OFFSET); 790 791 /* Enable autosense */ 792 bcm_kona_i2c_enable_autosense(dev); 793 794 /* Enable TX FIFO */ 795 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, 796 dev->base + TXFCR_OFFSET); 797 798 /* Mask all interrupts */ 799 writel(0, dev->base + IER_OFFSET); 800 801 /* Clear all pending interrupts */ 802 writel(ISR_CMDBUSY_MASK | 803 ISR_READ_COMPLETE_MASK | 804 ISR_SES_DONE_MASK | 805 ISR_ERR_MASK | 806 ISR_TXFIFOEMPTY_MASK | 807 ISR_NOACK_MASK, 808 dev->base + ISR_OFFSET); 809 810 /* Get the interrupt number */ 811 dev->irq = platform_get_irq(pdev, 0); 812 if (dev->irq < 0) { 813 rc = dev->irq; 814 goto probe_disable_clk; 815 } 816 817 /* register the ISR handler */ 818 rc = devm_request_irq(&pdev->dev, dev->irq, bcm_kona_i2c_isr, 819 IRQF_SHARED, pdev->name, dev); 820 if (rc) { 821 dev_err(dev->device, "failed to request irq %i\n", dev->irq); 822 goto probe_disable_clk; 823 } 824 825 /* Enable the controller but leave it idle */ 826 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); 827 828 /* Disable pad output */ 829 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); 830 831 /* Disable internal clock */ 832 bcm_kona_i2c_disable_clock(dev); 833 834 /* Disable external clock */ 835 clk_disable_unprepare(dev->external_clk); 836 837 /* Add the i2c adapter */ 838 adap = &dev->adapter; 839 i2c_set_adapdata(adap, dev); 840 adap->owner = THIS_MODULE; 841 strscpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); 842 adap->algo = &bcm_algo; 843 adap->dev.parent = &pdev->dev; 844 adap->dev.of_node = pdev->dev.of_node; 845 846 rc = i2c_add_adapter(adap); 847 if (rc) 848 return rc; 849 850 dev_info(dev->device, "device registered successfully\n"); 851 852 return 0; 853 854 probe_disable_clk: 855 bcm_kona_i2c_disable_clock(dev); 856 clk_disable_unprepare(dev->external_clk); 857 858 return rc; 859 } 860 861 static void bcm_kona_i2c_remove(struct platform_device *pdev) 862 { 863 struct bcm_kona_i2c_dev *dev = platform_get_drvdata(pdev); 864 865 i2c_del_adapter(&dev->adapter); 866 } 867 868 static const struct of_device_id bcm_kona_i2c_of_match[] = { 869 {.compatible = "brcm,kona-i2c",}, 870 {}, 871 }; 872 MODULE_DEVICE_TABLE(of, bcm_kona_i2c_of_match); 873 874 static struct platform_driver bcm_kona_i2c_driver = { 875 .driver = { 876 .name = "bcm-kona-i2c", 877 .of_match_table = bcm_kona_i2c_of_match, 878 }, 879 .probe = bcm_kona_i2c_probe, 880 .remove_new = bcm_kona_i2c_remove, 881 }; 882 module_platform_driver(bcm_kona_i2c_driver); 883 884 MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>"); 885 MODULE_DESCRIPTION("Broadcom Kona I2C Driver"); 886 MODULE_LICENSE("GPL v2"); 887