1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2014 Broadcom Corporation 3 4 #include <linux/delay.h> 5 #include <linux/i2c.h> 6 #include <linux/interrupt.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 14 #define IDM_CTRL_DIRECT_OFFSET 0x00 15 #define CFG_OFFSET 0x00 16 #define CFG_RESET_SHIFT 31 17 #define CFG_EN_SHIFT 30 18 #define CFG_SLAVE_ADDR_0_SHIFT 28 19 #define CFG_M_RETRY_CNT_SHIFT 16 20 #define CFG_M_RETRY_CNT_MASK 0x0f 21 22 #define TIM_CFG_OFFSET 0x04 23 #define TIM_CFG_MODE_400_SHIFT 31 24 #define TIM_RAND_SLAVE_STRETCH_SHIFT 24 25 #define TIM_RAND_SLAVE_STRETCH_MASK 0x7f 26 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16 27 #define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f 28 29 #define S_CFG_SMBUS_ADDR_OFFSET 0x08 30 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31 31 #define S_CFG_NIC_SMB_ADDR3_SHIFT 24 32 #define S_CFG_NIC_SMB_ADDR3_MASK 0x7f 33 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23 34 #define S_CFG_NIC_SMB_ADDR2_SHIFT 16 35 #define S_CFG_NIC_SMB_ADDR2_MASK 0x7f 36 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15 37 #define S_CFG_NIC_SMB_ADDR1_SHIFT 8 38 #define S_CFG_NIC_SMB_ADDR1_MASK 0x7f 39 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7 40 #define S_CFG_NIC_SMB_ADDR0_SHIFT 0 41 #define S_CFG_NIC_SMB_ADDR0_MASK 0x7f 42 43 #define M_FIFO_CTRL_OFFSET 0x0c 44 #define M_FIFO_RX_FLUSH_SHIFT 31 45 #define M_FIFO_TX_FLUSH_SHIFT 30 46 #define M_FIFO_RX_CNT_SHIFT 16 47 #define M_FIFO_RX_CNT_MASK 0x7f 48 #define M_FIFO_RX_THLD_SHIFT 8 49 #define M_FIFO_RX_THLD_MASK 0x3f 50 51 #define S_FIFO_CTRL_OFFSET 0x10 52 #define S_FIFO_RX_FLUSH_SHIFT 31 53 #define S_FIFO_TX_FLUSH_SHIFT 30 54 #define S_FIFO_RX_CNT_SHIFT 16 55 #define S_FIFO_RX_CNT_MASK 0x7f 56 #define S_FIFO_RX_THLD_SHIFT 8 57 #define S_FIFO_RX_THLD_MASK 0x3f 58 59 #define M_CMD_OFFSET 0x30 60 #define M_CMD_START_BUSY_SHIFT 31 61 #define M_CMD_STATUS_SHIFT 25 62 #define M_CMD_STATUS_MASK 0x07 63 #define M_CMD_STATUS_SUCCESS 0x0 64 #define M_CMD_STATUS_LOST_ARB 0x1 65 #define M_CMD_STATUS_NACK_ADDR 0x2 66 #define M_CMD_STATUS_NACK_DATA 0x3 67 #define M_CMD_STATUS_TIMEOUT 0x4 68 #define M_CMD_STATUS_FIFO_UNDERRUN 0x5 69 #define M_CMD_STATUS_RX_FIFO_FULL 0x6 70 #define M_CMD_PROTOCOL_SHIFT 9 71 #define M_CMD_PROTOCOL_MASK 0xf 72 #define M_CMD_PROTOCOL_QUICK 0x0 73 #define M_CMD_PROTOCOL_BLK_WR 0x7 74 #define M_CMD_PROTOCOL_BLK_RD 0x8 75 #define M_CMD_PROTOCOL_PROCESS 0xa 76 #define M_CMD_PEC_SHIFT 8 77 #define M_CMD_RD_CNT_SHIFT 0 78 #define M_CMD_RD_CNT_MASK 0xff 79 80 #define S_CMD_OFFSET 0x34 81 #define S_CMD_START_BUSY_SHIFT 31 82 #define S_CMD_STATUS_SHIFT 23 83 #define S_CMD_STATUS_MASK 0x07 84 #define S_CMD_STATUS_SUCCESS 0x0 85 #define S_CMD_STATUS_TIMEOUT 0x5 86 #define S_CMD_STATUS_MASTER_ABORT 0x7 87 88 #define IE_OFFSET 0x38 89 #define IE_M_RX_FIFO_FULL_SHIFT 31 90 #define IE_M_RX_THLD_SHIFT 30 91 #define IE_M_START_BUSY_SHIFT 28 92 #define IE_M_TX_UNDERRUN_SHIFT 27 93 #define IE_S_RX_FIFO_FULL_SHIFT 26 94 #define IE_S_RX_THLD_SHIFT 25 95 #define IE_S_RX_EVENT_SHIFT 24 96 #define IE_S_START_BUSY_SHIFT 23 97 #define IE_S_TX_UNDERRUN_SHIFT 22 98 #define IE_S_RD_EVENT_SHIFT 21 99 100 #define IS_OFFSET 0x3c 101 #define IS_M_RX_FIFO_FULL_SHIFT 31 102 #define IS_M_RX_THLD_SHIFT 30 103 #define IS_M_START_BUSY_SHIFT 28 104 #define IS_M_TX_UNDERRUN_SHIFT 27 105 #define IS_S_RX_FIFO_FULL_SHIFT 26 106 #define IS_S_RX_THLD_SHIFT 25 107 #define IS_S_RX_EVENT_SHIFT 24 108 #define IS_S_START_BUSY_SHIFT 23 109 #define IS_S_TX_UNDERRUN_SHIFT 22 110 #define IS_S_RD_EVENT_SHIFT 21 111 112 #define M_TX_OFFSET 0x40 113 #define M_TX_WR_STATUS_SHIFT 31 114 #define M_TX_DATA_SHIFT 0 115 #define M_TX_DATA_MASK 0xff 116 117 #define M_RX_OFFSET 0x44 118 #define M_RX_STATUS_SHIFT 30 119 #define M_RX_STATUS_MASK 0x03 120 #define M_RX_PEC_ERR_SHIFT 29 121 #define M_RX_DATA_SHIFT 0 122 #define M_RX_DATA_MASK 0xff 123 124 #define S_TX_OFFSET 0x48 125 #define S_TX_WR_STATUS_SHIFT 31 126 #define S_TX_DATA_SHIFT 0 127 #define S_TX_DATA_MASK 0xff 128 129 #define S_RX_OFFSET 0x4c 130 #define S_RX_STATUS_SHIFT 30 131 #define S_RX_STATUS_MASK 0x03 132 #define S_RX_PEC_ERR_SHIFT 29 133 #define S_RX_DATA_SHIFT 0 134 #define S_RX_DATA_MASK 0xff 135 136 #define I2C_TIMEOUT_MSEC 50000 137 #define M_TX_RX_FIFO_SIZE 64 138 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1) 139 140 #define M_RX_MAX_READ_LEN 255 141 #define M_RX_FIFO_THLD_VALUE 50 142 143 #define IE_M_ALL_INTERRUPT_SHIFT 27 144 #define IE_M_ALL_INTERRUPT_MASK 0x1e 145 146 #define SLAVE_READ_WRITE_BIT_MASK 0x1 147 #define SLAVE_READ_WRITE_BIT_SHIFT 0x1 148 #define SLAVE_MAX_SIZE_TRANSACTION 64 149 #define SLAVE_CLOCK_STRETCH_TIME 25 150 151 #define IE_S_ALL_INTERRUPT_SHIFT 21 152 #define IE_S_ALL_INTERRUPT_MASK 0x3f 153 /* 154 * It takes ~18us to reading 10bytes of data, hence to keep tasklet 155 * running for less time, max slave read per tasklet is set to 10 bytes. 156 */ 157 #define MAX_SLAVE_RX_PER_INT 10 158 159 enum i2c_slave_read_status { 160 I2C_SLAVE_RX_FIFO_EMPTY = 0, 161 I2C_SLAVE_RX_START, 162 I2C_SLAVE_RX_DATA, 163 I2C_SLAVE_RX_END, 164 }; 165 166 enum bus_speed_index { 167 I2C_SPD_100K = 0, 168 I2C_SPD_400K, 169 }; 170 171 enum bcm_iproc_i2c_type { 172 IPROC_I2C, 173 IPROC_I2C_NIC 174 }; 175 176 struct bcm_iproc_i2c_dev { 177 struct device *device; 178 enum bcm_iproc_i2c_type type; 179 int irq; 180 181 void __iomem *base; 182 void __iomem *idm_base; 183 184 u32 ape_addr_mask; 185 186 /* lock for indirect access through IDM */ 187 spinlock_t idm_lock; 188 189 struct i2c_adapter adapter; 190 unsigned int bus_speed; 191 192 struct completion done; 193 int xfer_is_done; 194 195 struct i2c_msg *msg; 196 197 struct i2c_client *slave; 198 199 /* bytes that have been transferred */ 200 unsigned int tx_bytes; 201 /* bytes that have been read */ 202 unsigned int rx_bytes; 203 unsigned int thld_bytes; 204 205 bool slave_rx_only; 206 bool rx_start_rcvd; 207 bool slave_read_complete; 208 u32 tx_underrun; 209 u32 slave_int_mask; 210 struct tasklet_struct slave_rx_tasklet; 211 }; 212 213 /* tasklet to process slave rx data */ 214 static void slave_rx_tasklet_fn(unsigned long); 215 216 /* 217 * Can be expanded in the future if more interrupt status bits are utilized 218 */ 219 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\ 220 | BIT(IS_M_RX_THLD_SHIFT)) 221 222 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\ 223 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\ 224 | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\ 225 | BIT(IS_S_RX_THLD_SHIFT)) 226 227 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave); 228 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave); 229 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, 230 bool enable); 231 232 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c, 233 u32 offset) 234 { 235 u32 val; 236 unsigned long flags; 237 238 if (iproc_i2c->idm_base) { 239 spin_lock_irqsave(&iproc_i2c->idm_lock, flags); 240 writel(iproc_i2c->ape_addr_mask, 241 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); 242 val = readl(iproc_i2c->base + offset); 243 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags); 244 } else { 245 val = readl(iproc_i2c->base + offset); 246 } 247 248 return val; 249 } 250 251 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, 252 u32 offset, u32 val) 253 { 254 unsigned long flags; 255 256 if (iproc_i2c->idm_base) { 257 spin_lock_irqsave(&iproc_i2c->idm_lock, flags); 258 writel(iproc_i2c->ape_addr_mask, 259 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); 260 writel(val, iproc_i2c->base + offset); 261 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags); 262 } else { 263 writel(val, iproc_i2c->base + offset); 264 } 265 } 266 267 static void bcm_iproc_i2c_slave_init( 268 struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset) 269 { 270 u32 val; 271 272 iproc_i2c->tx_underrun = 0; 273 if (need_reset) { 274 /* put controller in reset */ 275 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 276 val |= BIT(CFG_RESET_SHIFT); 277 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 278 279 /* wait 100 usec per spec */ 280 udelay(100); 281 282 /* bring controller out of reset */ 283 val &= ~(BIT(CFG_RESET_SHIFT)); 284 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 285 } 286 287 /* flush TX/RX FIFOs */ 288 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); 289 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val); 290 291 /* Maximum slave stretch time */ 292 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 293 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT); 294 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT); 295 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 296 297 /* Configure the slave address */ 298 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); 299 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); 300 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT); 301 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT); 302 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val); 303 304 /* clear all pending slave interrupts */ 305 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE); 306 307 /* Enable interrupt register to indicate a valid byte in receive fifo */ 308 val = BIT(IE_S_RX_EVENT_SHIFT); 309 /* Enable interrupt register to indicate Slave Rx FIFO Full */ 310 val |= BIT(IE_S_RX_FIFO_FULL_SHIFT); 311 /* Enable interrupt register to indicate a Master read transaction */ 312 val |= BIT(IE_S_RD_EVENT_SHIFT); 313 /* Enable interrupt register for the Slave BUSY command */ 314 val |= BIT(IE_S_START_BUSY_SHIFT); 315 iproc_i2c->slave_int_mask = val; 316 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 317 } 318 319 static void bcm_iproc_i2c_check_slave_status( 320 struct bcm_iproc_i2c_dev *iproc_i2c) 321 { 322 u32 val; 323 324 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET); 325 /* status is valid only when START_BUSY is cleared after it was set */ 326 if (val & BIT(S_CMD_START_BUSY_SHIFT)) 327 return; 328 329 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK; 330 if (val == S_CMD_STATUS_TIMEOUT || val == S_CMD_STATUS_MASTER_ABORT) { 331 dev_err(iproc_i2c->device, (val == S_CMD_STATUS_TIMEOUT) ? 332 "slave random stretch time timeout\n" : 333 "Master aborted read transaction\n"); 334 /* re-initialize i2c for recovery */ 335 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 336 bcm_iproc_i2c_slave_init(iproc_i2c, true); 337 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 338 } 339 } 340 341 static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c) 342 { 343 u8 rx_data, rx_status; 344 u32 rx_bytes = 0; 345 u32 val; 346 347 while (rx_bytes < MAX_SLAVE_RX_PER_INT) { 348 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); 349 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK; 350 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK); 351 352 if (rx_status == I2C_SLAVE_RX_START) { 353 /* Start of SMBUS Master write */ 354 i2c_slave_event(iproc_i2c->slave, 355 I2C_SLAVE_WRITE_REQUESTED, &rx_data); 356 iproc_i2c->rx_start_rcvd = true; 357 iproc_i2c->slave_read_complete = false; 358 } else if (rx_status == I2C_SLAVE_RX_DATA && 359 iproc_i2c->rx_start_rcvd) { 360 /* Middle of SMBUS Master write */ 361 i2c_slave_event(iproc_i2c->slave, 362 I2C_SLAVE_WRITE_RECEIVED, &rx_data); 363 } else if (rx_status == I2C_SLAVE_RX_END && 364 iproc_i2c->rx_start_rcvd) { 365 /* End of SMBUS Master write */ 366 if (iproc_i2c->slave_rx_only) 367 i2c_slave_event(iproc_i2c->slave, 368 I2C_SLAVE_WRITE_RECEIVED, 369 &rx_data); 370 371 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, 372 &rx_data); 373 } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) { 374 iproc_i2c->rx_start_rcvd = false; 375 iproc_i2c->slave_read_complete = true; 376 break; 377 } 378 379 rx_bytes++; 380 } 381 } 382 383 static void slave_rx_tasklet_fn(unsigned long data) 384 { 385 struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data; 386 u32 int_clr; 387 388 bcm_iproc_i2c_slave_read(iproc_i2c); 389 390 /* clear pending IS_S_RX_EVENT_SHIFT interrupt */ 391 int_clr = BIT(IS_S_RX_EVENT_SHIFT); 392 393 if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) { 394 /* 395 * In case of single byte master-read request, 396 * IS_S_TX_UNDERRUN_SHIFT event is generated before 397 * IS_S_START_BUSY_SHIFT event. Hence start slave data send 398 * from first IS_S_TX_UNDERRUN_SHIFT event. 399 * 400 * This means don't send any data from slave when 401 * IS_S_RD_EVENT_SHIFT event is generated else it will increment 402 * eeprom or other backend slave driver read pointer twice. 403 */ 404 iproc_i2c->tx_underrun = 0; 405 iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT); 406 407 /* clear IS_S_RD_EVENT_SHIFT interrupt */ 408 int_clr |= BIT(IS_S_RD_EVENT_SHIFT); 409 } 410 411 /* clear slave interrupt */ 412 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr); 413 /* enable slave interrupts */ 414 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask); 415 } 416 417 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, 418 u32 status) 419 { 420 u32 val; 421 u8 value; 422 423 /* 424 * Slave events in case of master-write, master-write-read and, 425 * master-read 426 * 427 * Master-write : only IS_S_RX_EVENT_SHIFT event 428 * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT 429 * events 430 * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT 431 * events or only IS_S_RD_EVENT_SHIFT 432 * 433 * iproc has a slave rx fifo size of 64 bytes. Rx fifo full interrupt 434 * (IS_S_RX_FIFO_FULL_SHIFT) will be generated when RX fifo becomes 435 * full. This can happen if Master issues write requests of more than 436 * 64 bytes. 437 */ 438 if (status & BIT(IS_S_RX_EVENT_SHIFT) || 439 status & BIT(IS_S_RD_EVENT_SHIFT) || 440 status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) { 441 /* disable slave interrupts */ 442 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 443 val &= ~iproc_i2c->slave_int_mask; 444 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 445 446 if (status & BIT(IS_S_RD_EVENT_SHIFT)) 447 /* Master-write-read request */ 448 iproc_i2c->slave_rx_only = false; 449 else 450 /* Master-write request only */ 451 iproc_i2c->slave_rx_only = true; 452 453 /* schedule tasklet to read data later */ 454 tasklet_schedule(&iproc_i2c->slave_rx_tasklet); 455 456 /* 457 * clear only IS_S_RX_EVENT_SHIFT and 458 * IS_S_RX_FIFO_FULL_SHIFT interrupt. 459 */ 460 val = BIT(IS_S_RX_EVENT_SHIFT); 461 if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) 462 val |= BIT(IS_S_RX_FIFO_FULL_SHIFT); 463 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val); 464 } 465 466 if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) { 467 iproc_i2c->tx_underrun++; 468 if (iproc_i2c->tx_underrun == 1) 469 /* Start of SMBUS for Master Read */ 470 i2c_slave_event(iproc_i2c->slave, 471 I2C_SLAVE_READ_REQUESTED, 472 &value); 473 else 474 /* Master read other than start */ 475 i2c_slave_event(iproc_i2c->slave, 476 I2C_SLAVE_READ_PROCESSED, 477 &value); 478 479 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value); 480 /* start transfer */ 481 val = BIT(S_CMD_START_BUSY_SHIFT); 482 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); 483 484 /* clear interrupt */ 485 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 486 BIT(IS_S_TX_UNDERRUN_SHIFT)); 487 } 488 489 /* Stop received from master in case of master read transaction */ 490 if (status & BIT(IS_S_START_BUSY_SHIFT)) { 491 /* 492 * Disable interrupt for TX FIFO becomes empty and 493 * less than PKT_LENGTH bytes were output on the SMBUS 494 */ 495 iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT); 496 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 497 iproc_i2c->slave_int_mask); 498 499 /* End of SMBUS for Master Read */ 500 val = BIT(S_TX_WR_STATUS_SHIFT); 501 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val); 502 503 val = BIT(S_CMD_START_BUSY_SHIFT); 504 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); 505 506 /* flush TX FIFOs */ 507 val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET); 508 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT)); 509 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val); 510 511 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value); 512 513 /* clear interrupt */ 514 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 515 BIT(IS_S_START_BUSY_SHIFT)); 516 } 517 518 /* check slave transmit status only if slave is transmitting */ 519 if (!iproc_i2c->slave_rx_only) 520 bcm_iproc_i2c_check_slave_status(iproc_i2c); 521 522 return true; 523 } 524 525 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) 526 { 527 struct i2c_msg *msg = iproc_i2c->msg; 528 uint32_t val; 529 530 /* Read valid data from RX FIFO */ 531 while (iproc_i2c->rx_bytes < msg->len) { 532 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET); 533 534 /* rx fifo empty */ 535 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK)) 536 break; 537 538 msg->buf[iproc_i2c->rx_bytes] = 539 (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK; 540 iproc_i2c->rx_bytes++; 541 } 542 } 543 544 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c) 545 { 546 struct i2c_msg *msg = iproc_i2c->msg; 547 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes; 548 unsigned int i; 549 u32 val; 550 551 /* can only fill up to the FIFO size */ 552 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE); 553 for (i = 0; i < tx_bytes; i++) { 554 /* start from where we left over */ 555 unsigned int idx = iproc_i2c->tx_bytes + i; 556 557 val = msg->buf[idx]; 558 559 /* mark the last byte */ 560 if (idx == msg->len - 1) { 561 val |= BIT(M_TX_WR_STATUS_SHIFT); 562 563 if (iproc_i2c->irq) { 564 u32 tmp; 565 566 /* 567 * Since this is the last byte, we should now 568 * disable TX FIFO underrun interrupt 569 */ 570 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 571 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT); 572 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 573 tmp); 574 } 575 } 576 577 /* load data into TX FIFO */ 578 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); 579 } 580 581 /* update number of transferred bytes */ 582 iproc_i2c->tx_bytes += tx_bytes; 583 } 584 585 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c) 586 { 587 struct i2c_msg *msg = iproc_i2c->msg; 588 u32 bytes_left, val; 589 590 bcm_iproc_i2c_read_valid_bytes(iproc_i2c); 591 bytes_left = msg->len - iproc_i2c->rx_bytes; 592 if (bytes_left == 0) { 593 if (iproc_i2c->irq) { 594 /* finished reading all data, disable rx thld event */ 595 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 596 val &= ~BIT(IS_M_RX_THLD_SHIFT); 597 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 598 } 599 } else if (bytes_left < iproc_i2c->thld_bytes) { 600 /* set bytes left as threshold */ 601 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); 602 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); 603 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT); 604 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 605 iproc_i2c->thld_bytes = bytes_left; 606 } 607 /* 608 * bytes_left >= iproc_i2c->thld_bytes, 609 * hence no need to change the THRESHOLD SET. 610 * It will remain as iproc_i2c->thld_bytes itself 611 */ 612 } 613 614 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c, 615 u32 status) 616 { 617 /* TX FIFO is empty and we have more data to send */ 618 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) 619 bcm_iproc_i2c_send(iproc_i2c); 620 621 /* RX FIFO threshold is reached and data needs to be read out */ 622 if (status & BIT(IS_M_RX_THLD_SHIFT)) 623 bcm_iproc_i2c_read(iproc_i2c); 624 625 /* transfer is done */ 626 if (status & BIT(IS_M_START_BUSY_SHIFT)) { 627 iproc_i2c->xfer_is_done = 1; 628 if (iproc_i2c->irq) 629 complete(&iproc_i2c->done); 630 } 631 } 632 633 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) 634 { 635 struct bcm_iproc_i2c_dev *iproc_i2c = data; 636 u32 slave_status; 637 u32 status; 638 bool ret; 639 640 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET); 641 /* process only slave interrupt which are enabled */ 642 slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) & 643 ISR_MASK_SLAVE; 644 645 if (slave_status) { 646 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status); 647 if (ret) 648 return IRQ_HANDLED; 649 else 650 return IRQ_NONE; 651 } 652 653 status &= ISR_MASK; 654 if (!status) 655 return IRQ_NONE; 656 657 /* process all master based events */ 658 bcm_iproc_i2c_process_m_event(iproc_i2c, status); 659 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 660 661 return IRQ_HANDLED; 662 } 663 664 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c) 665 { 666 u32 val; 667 668 /* put controller in reset */ 669 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 670 val |= BIT(CFG_RESET_SHIFT); 671 val &= ~(BIT(CFG_EN_SHIFT)); 672 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 673 674 /* wait 100 usec per spec */ 675 udelay(100); 676 677 /* bring controller out of reset */ 678 val &= ~(BIT(CFG_RESET_SHIFT)); 679 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 680 681 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */ 682 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT)); 683 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 684 /* disable all interrupts */ 685 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 686 val &= ~(IE_M_ALL_INTERRUPT_MASK << 687 IE_M_ALL_INTERRUPT_SHIFT); 688 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 689 690 /* clear all pending interrupts */ 691 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff); 692 693 return 0; 694 } 695 696 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, 697 bool enable) 698 { 699 u32 val; 700 701 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 702 if (enable) 703 val |= BIT(CFG_EN_SHIFT); 704 else 705 val &= ~BIT(CFG_EN_SHIFT); 706 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 707 } 708 709 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, 710 struct i2c_msg *msg) 711 { 712 u32 val; 713 714 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET); 715 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK; 716 717 switch (val) { 718 case M_CMD_STATUS_SUCCESS: 719 return 0; 720 721 case M_CMD_STATUS_LOST_ARB: 722 dev_dbg(iproc_i2c->device, "lost bus arbitration\n"); 723 return -EAGAIN; 724 725 case M_CMD_STATUS_NACK_ADDR: 726 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr); 727 return -ENXIO; 728 729 case M_CMD_STATUS_NACK_DATA: 730 dev_dbg(iproc_i2c->device, "NAK data\n"); 731 return -ENXIO; 732 733 case M_CMD_STATUS_TIMEOUT: 734 dev_dbg(iproc_i2c->device, "bus timeout\n"); 735 return -ETIMEDOUT; 736 737 case M_CMD_STATUS_FIFO_UNDERRUN: 738 dev_dbg(iproc_i2c->device, "FIFO under-run\n"); 739 return -ENXIO; 740 741 case M_CMD_STATUS_RX_FIFO_FULL: 742 dev_dbg(iproc_i2c->device, "RX FIFO full\n"); 743 return -ETIMEDOUT; 744 745 default: 746 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val); 747 748 /* re-initialize i2c for recovery */ 749 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 750 bcm_iproc_i2c_init(iproc_i2c); 751 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 752 753 return -EIO; 754 } 755 } 756 757 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, 758 struct i2c_msg *msg, 759 u32 cmd) 760 { 761 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC); 762 u32 val, status; 763 int ret; 764 765 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd); 766 767 if (iproc_i2c->irq) { 768 time_left = wait_for_completion_timeout(&iproc_i2c->done, 769 time_left); 770 /* disable all interrupts */ 771 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 772 /* read it back to flush the write */ 773 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 774 /* make sure the interrupt handler isn't running */ 775 synchronize_irq(iproc_i2c->irq); 776 777 } else { /* polling mode */ 778 unsigned long timeout = jiffies + time_left; 779 780 do { 781 status = iproc_i2c_rd_reg(iproc_i2c, 782 IS_OFFSET) & ISR_MASK; 783 bcm_iproc_i2c_process_m_event(iproc_i2c, status); 784 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 785 786 if (time_after(jiffies, timeout)) { 787 time_left = 0; 788 break; 789 } 790 791 cpu_relax(); 792 cond_resched(); 793 } while (!iproc_i2c->xfer_is_done); 794 } 795 796 if (!time_left && !iproc_i2c->xfer_is_done) { 797 dev_err(iproc_i2c->device, "transaction timed out\n"); 798 799 /* flush both TX/RX FIFOs */ 800 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); 801 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 802 return -ETIMEDOUT; 803 } 804 805 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg); 806 if (ret) { 807 /* flush both TX/RX FIFOs */ 808 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); 809 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 810 return ret; 811 } 812 813 return 0; 814 } 815 816 /* 817 * If 'process_call' is true, then this is a multi-msg transfer that requires 818 * a repeated start between the messages. 819 * More specifically, it must be a write (reg) followed by a read (data). 820 * The i2c quirks are set to enforce this rule. 821 */ 822 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c, 823 struct i2c_msg *msgs, bool process_call) 824 { 825 int i; 826 u8 addr; 827 u32 val, tmp, val_intr_en; 828 unsigned int tx_bytes; 829 struct i2c_msg *msg = &msgs[0]; 830 831 /* check if bus is busy */ 832 if (!!(iproc_i2c_rd_reg(iproc_i2c, 833 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) { 834 dev_warn(iproc_i2c->device, "bus is busy\n"); 835 return -EBUSY; 836 } 837 838 iproc_i2c->msg = msg; 839 840 /* format and load slave address into the TX FIFO */ 841 addr = i2c_8bit_addr_from_msg(msg); 842 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr); 843 844 /* 845 * For a write transaction, load data into the TX FIFO. Only allow 846 * loading up to TX FIFO size - 1 bytes of data since the first byte 847 * has been used up by the slave address 848 */ 849 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1); 850 if (!(msg->flags & I2C_M_RD)) { 851 for (i = 0; i < tx_bytes; i++) { 852 val = msg->buf[i]; 853 854 /* mark the last byte */ 855 if (!process_call && (i == msg->len - 1)) 856 val |= BIT(M_TX_WR_STATUS_SHIFT); 857 858 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); 859 } 860 iproc_i2c->tx_bytes = tx_bytes; 861 } 862 863 /* Process the read message if this is process call */ 864 if (process_call) { 865 msg++; 866 iproc_i2c->msg = msg; /* point to second msg */ 867 868 /* 869 * The last byte to be sent out should be a slave 870 * address with read operation 871 */ 872 addr = i2c_8bit_addr_from_msg(msg); 873 /* mark it the last byte out */ 874 val = addr | BIT(M_TX_WR_STATUS_SHIFT); 875 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); 876 } 877 878 /* mark as incomplete before starting the transaction */ 879 if (iproc_i2c->irq) 880 reinit_completion(&iproc_i2c->done); 881 882 iproc_i2c->xfer_is_done = 0; 883 884 /* 885 * Enable the "start busy" interrupt, which will be triggered after the 886 * transaction is done, i.e., the internal start_busy bit, transitions 887 * from 1 to 0. 888 */ 889 val_intr_en = BIT(IE_M_START_BUSY_SHIFT); 890 891 /* 892 * If TX data size is larger than the TX FIFO, need to enable TX 893 * underrun interrupt, which will be triggerred when the TX FIFO is 894 * empty. When that happens we can then pump more data into the FIFO 895 */ 896 if (!process_call && !(msg->flags & I2C_M_RD) && 897 msg->len > iproc_i2c->tx_bytes) 898 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT); 899 900 /* 901 * Now we can activate the transfer. For a read operation, specify the 902 * number of bytes to read 903 */ 904 val = BIT(M_CMD_START_BUSY_SHIFT); 905 906 if (msg->len == 0) { 907 /* SMBUS QUICK Command (Read/Write) */ 908 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT); 909 } else if (msg->flags & I2C_M_RD) { 910 u32 protocol; 911 912 iproc_i2c->rx_bytes = 0; 913 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE) 914 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE; 915 else 916 iproc_i2c->thld_bytes = msg->len; 917 918 /* set threshold value */ 919 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); 920 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); 921 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT; 922 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp); 923 924 /* enable the RX threshold interrupt */ 925 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT); 926 927 protocol = process_call ? 928 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD; 929 930 val |= (protocol << M_CMD_PROTOCOL_SHIFT) | 931 (msg->len << M_CMD_RD_CNT_SHIFT); 932 } else { 933 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); 934 } 935 936 if (iproc_i2c->irq) 937 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en); 938 939 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val); 940 } 941 942 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, 943 struct i2c_msg msgs[], int num) 944 { 945 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter); 946 bool process_call = false; 947 int ret; 948 949 if (num == 2) { 950 /* Repeated start, use process call */ 951 process_call = true; 952 if (msgs[1].flags & I2C_M_NOSTART) { 953 dev_err(iproc_i2c->device, "Invalid repeated start\n"); 954 return -EOPNOTSUPP; 955 } 956 } 957 958 ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call); 959 if (ret) { 960 dev_dbg(iproc_i2c->device, "xfer failed\n"); 961 return ret; 962 } 963 964 return num; 965 } 966 967 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) 968 { 969 u32 val; 970 971 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 972 973 if (adap->algo->reg_slave) 974 val |= I2C_FUNC_SLAVE; 975 976 return val; 977 } 978 979 static struct i2c_algorithm bcm_iproc_algo = { 980 .master_xfer = bcm_iproc_i2c_xfer, 981 .functionality = bcm_iproc_i2c_functionality, 982 .reg_slave = bcm_iproc_i2c_reg_slave, 983 .unreg_slave = bcm_iproc_i2c_unreg_slave, 984 }; 985 986 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = { 987 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 988 .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE, 989 .max_read_len = M_RX_MAX_READ_LEN, 990 }; 991 992 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) 993 { 994 unsigned int bus_speed; 995 u32 val; 996 int ret = of_property_read_u32(iproc_i2c->device->of_node, 997 "clock-frequency", &bus_speed); 998 if (ret < 0) { 999 dev_info(iproc_i2c->device, 1000 "unable to interpret clock-frequency DT property\n"); 1001 bus_speed = I2C_MAX_STANDARD_MODE_FREQ; 1002 } 1003 1004 if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) { 1005 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n", 1006 bus_speed); 1007 dev_err(iproc_i2c->device, 1008 "valid speeds are 100khz and 400khz\n"); 1009 return -EINVAL; 1010 } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) { 1011 bus_speed = I2C_MAX_STANDARD_MODE_FREQ; 1012 } else { 1013 bus_speed = I2C_MAX_FAST_MODE_FREQ; 1014 } 1015 1016 iproc_i2c->bus_speed = bus_speed; 1017 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 1018 val &= ~BIT(TIM_CFG_MODE_400_SHIFT); 1019 val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT; 1020 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 1021 1022 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed); 1023 1024 return 0; 1025 } 1026 1027 static int bcm_iproc_i2c_probe(struct platform_device *pdev) 1028 { 1029 int irq, ret = 0; 1030 struct bcm_iproc_i2c_dev *iproc_i2c; 1031 struct i2c_adapter *adap; 1032 1033 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c), 1034 GFP_KERNEL); 1035 if (!iproc_i2c) 1036 return -ENOMEM; 1037 1038 platform_set_drvdata(pdev, iproc_i2c); 1039 iproc_i2c->device = &pdev->dev; 1040 iproc_i2c->type = 1041 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev); 1042 init_completion(&iproc_i2c->done); 1043 1044 iproc_i2c->base = devm_platform_ioremap_resource(pdev, 0); 1045 if (IS_ERR(iproc_i2c->base)) 1046 return PTR_ERR(iproc_i2c->base); 1047 1048 if (iproc_i2c->type == IPROC_I2C_NIC) { 1049 iproc_i2c->idm_base = devm_platform_ioremap_resource(pdev, 1); 1050 if (IS_ERR(iproc_i2c->idm_base)) 1051 return PTR_ERR(iproc_i2c->idm_base); 1052 1053 ret = of_property_read_u32(iproc_i2c->device->of_node, 1054 "brcm,ape-hsls-addr-mask", 1055 &iproc_i2c->ape_addr_mask); 1056 if (ret < 0) { 1057 dev_err(iproc_i2c->device, 1058 "'brcm,ape-hsls-addr-mask' missing\n"); 1059 return -EINVAL; 1060 } 1061 1062 spin_lock_init(&iproc_i2c->idm_lock); 1063 1064 /* no slave support */ 1065 bcm_iproc_algo.reg_slave = NULL; 1066 bcm_iproc_algo.unreg_slave = NULL; 1067 } 1068 1069 ret = bcm_iproc_i2c_init(iproc_i2c); 1070 if (ret) 1071 return ret; 1072 1073 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c); 1074 if (ret) 1075 return ret; 1076 1077 irq = platform_get_irq(pdev, 0); 1078 if (irq > 0) { 1079 ret = devm_request_irq(iproc_i2c->device, irq, 1080 bcm_iproc_i2c_isr, 0, pdev->name, 1081 iproc_i2c); 1082 if (ret < 0) { 1083 dev_err(iproc_i2c->device, 1084 "unable to request irq %i\n", irq); 1085 return ret; 1086 } 1087 1088 iproc_i2c->irq = irq; 1089 } else { 1090 dev_warn(iproc_i2c->device, 1091 "no irq resource, falling back to poll mode\n"); 1092 } 1093 1094 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 1095 1096 adap = &iproc_i2c->adapter; 1097 i2c_set_adapdata(adap, iproc_i2c); 1098 snprintf(adap->name, sizeof(adap->name), 1099 "Broadcom iProc (%s)", 1100 of_node_full_name(iproc_i2c->device->of_node)); 1101 adap->algo = &bcm_iproc_algo; 1102 adap->quirks = &bcm_iproc_i2c_quirks; 1103 adap->dev.parent = &pdev->dev; 1104 adap->dev.of_node = pdev->dev.of_node; 1105 1106 return i2c_add_adapter(adap); 1107 } 1108 1109 static void bcm_iproc_i2c_remove(struct platform_device *pdev) 1110 { 1111 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev); 1112 1113 if (iproc_i2c->irq) { 1114 /* 1115 * Make sure there's no pending interrupt when we remove the 1116 * adapter 1117 */ 1118 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 1119 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 1120 synchronize_irq(iproc_i2c->irq); 1121 } 1122 1123 i2c_del_adapter(&iproc_i2c->adapter); 1124 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 1125 } 1126 1127 static int bcm_iproc_i2c_suspend(struct device *dev) 1128 { 1129 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 1130 1131 if (iproc_i2c->irq) { 1132 /* 1133 * Make sure there's no pending interrupt when we go into 1134 * suspend 1135 */ 1136 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 1137 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 1138 synchronize_irq(iproc_i2c->irq); 1139 } 1140 1141 /* now disable the controller */ 1142 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 1143 1144 return 0; 1145 } 1146 1147 static int bcm_iproc_i2c_resume(struct device *dev) 1148 { 1149 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 1150 int ret; 1151 u32 val; 1152 1153 /* 1154 * Power domain could have been shut off completely in system deep 1155 * sleep, so re-initialize the block here 1156 */ 1157 ret = bcm_iproc_i2c_init(iproc_i2c); 1158 if (ret) 1159 return ret; 1160 1161 /* configure to the desired bus speed */ 1162 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 1163 val &= ~BIT(TIM_CFG_MODE_400_SHIFT); 1164 val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT; 1165 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 1166 1167 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 1168 1169 return 0; 1170 } 1171 1172 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = { 1173 .suspend_late = &bcm_iproc_i2c_suspend, 1174 .resume_early = &bcm_iproc_i2c_resume 1175 }; 1176 1177 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave) 1178 { 1179 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter); 1180 1181 if (iproc_i2c->slave) 1182 return -EBUSY; 1183 1184 if (slave->flags & I2C_CLIENT_TEN) 1185 return -EAFNOSUPPORT; 1186 1187 iproc_i2c->slave = slave; 1188 1189 tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn, 1190 (unsigned long)iproc_i2c); 1191 1192 bcm_iproc_i2c_slave_init(iproc_i2c, false); 1193 return 0; 1194 } 1195 1196 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) 1197 { 1198 u32 tmp; 1199 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter); 1200 1201 if (!iproc_i2c->slave) 1202 return -EINVAL; 1203 1204 disable_irq(iproc_i2c->irq); 1205 1206 tasklet_kill(&iproc_i2c->slave_rx_tasklet); 1207 1208 /* disable all slave interrupts */ 1209 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 1210 tmp &= ~(IE_S_ALL_INTERRUPT_MASK << 1211 IE_S_ALL_INTERRUPT_SHIFT); 1212 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp); 1213 1214 /* Erase the slave address programmed */ 1215 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); 1216 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); 1217 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp); 1218 1219 /* flush TX/RX FIFOs */ 1220 tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); 1221 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp); 1222 1223 /* clear all pending slave interrupts */ 1224 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE); 1225 1226 iproc_i2c->slave = NULL; 1227 1228 enable_irq(iproc_i2c->irq); 1229 1230 return 0; 1231 } 1232 1233 static const struct of_device_id bcm_iproc_i2c_of_match[] = { 1234 { 1235 .compatible = "brcm,iproc-i2c", 1236 .data = (int *)IPROC_I2C, 1237 }, { 1238 .compatible = "brcm,iproc-nic-i2c", 1239 .data = (int *)IPROC_I2C_NIC, 1240 }, 1241 { /* sentinel */ } 1242 }; 1243 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match); 1244 1245 static struct platform_driver bcm_iproc_i2c_driver = { 1246 .driver = { 1247 .name = "bcm-iproc-i2c", 1248 .of_match_table = bcm_iproc_i2c_of_match, 1249 .pm = pm_sleep_ptr(&bcm_iproc_i2c_pm_ops), 1250 }, 1251 .probe = bcm_iproc_i2c_probe, 1252 .remove_new = bcm_iproc_i2c_remove, 1253 }; 1254 module_platform_driver(bcm_iproc_i2c_driver); 1255 1256 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); 1257 MODULE_DESCRIPTION("Broadcom iProc I2C Driver"); 1258 MODULE_LICENSE("GPL v2"); 1259