1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface 4 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> 5 * 6 * 2.6 port by Matt Porter <mporter@kernel.crashing.org> 7 * 8 * The documentation describes this as an SMBus controller, but it doesn't 9 * understand any of the SMBus protocol in hardware. It's really an I2C 10 * controller that could emulate most of the SMBus in software. 11 * 12 * This is just a skeleton adapter to use with the Au1550 PSC 13 * algorithm. It was developed for the Pb1550, but will work with 14 * any Au1550 board that has a similar PSC configuration. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/errno.h> 22 #include <linux/i2c.h> 23 #include <linux/slab.h> 24 25 #include <asm/mach-au1x00/au1000.h> 26 #include <asm/mach-au1x00/au1xxx_psc.h> 27 28 #define PSC_SEL 0x00 29 #define PSC_CTRL 0x04 30 #define PSC_SMBCFG 0x08 31 #define PSC_SMBMSK 0x0C 32 #define PSC_SMBPCR 0x10 33 #define PSC_SMBSTAT 0x14 34 #define PSC_SMBEVNT 0x18 35 #define PSC_SMBTXRX 0x1C 36 #define PSC_SMBTMR 0x20 37 38 struct i2c_au1550_data { 39 void __iomem *psc_base; 40 int xfer_timeout; 41 struct i2c_adapter adap; 42 }; 43 44 static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v) 45 { 46 __raw_writel(v, a->psc_base + r); 47 wmb(); 48 } 49 50 static inline unsigned long RD(struct i2c_au1550_data *a, int r) 51 { 52 return __raw_readl(a->psc_base + r); 53 } 54 55 static int wait_xfer_done(struct i2c_au1550_data *adap) 56 { 57 int i; 58 59 /* Wait for Tx Buffer Empty */ 60 for (i = 0; i < adap->xfer_timeout; i++) { 61 if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE) 62 return 0; 63 64 udelay(1); 65 } 66 67 return -ETIMEDOUT; 68 } 69 70 static int wait_ack(struct i2c_au1550_data *adap) 71 { 72 unsigned long stat; 73 74 if (wait_xfer_done(adap)) 75 return -ETIMEDOUT; 76 77 stat = RD(adap, PSC_SMBEVNT); 78 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) 79 return -ETIMEDOUT; 80 81 return 0; 82 } 83 84 static int wait_controller_done(struct i2c_au1550_data *adap) 85 { 86 int i; 87 88 for (i = 0; i < 2 * adap->xfer_timeout; i++) { 89 if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0) 90 return 0; 91 udelay(1); 92 } 93 94 return -ETIMEDOUT; 95 } 96 97 static int 98 do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q) 99 { 100 unsigned long stat; 101 102 /* Reset the FIFOs, clear events. */ 103 stat = RD(adap, PSC_SMBSTAT); 104 WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR); 105 106 if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) { 107 WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC); 108 while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0) 109 cpu_relax(); 110 udelay(50); 111 } 112 113 /* Write out the i2c chip address and specify operation */ 114 addr <<= 1; 115 if (rd) 116 addr |= 1; 117 118 /* zero-byte xfers stop immediately */ 119 if (q) 120 addr |= PSC_SMBTXRX_STP; 121 122 /* Put byte into fifo, start up controller */ 123 WR(adap, PSC_SMBTXRX, addr); 124 WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS); 125 if (wait_ack(adap)) 126 return -EIO; 127 return (q) ? wait_controller_done(adap) : 0; 128 } 129 130 static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out) 131 { 132 int j; 133 134 if (wait_xfer_done(adap)) 135 return -EIO; 136 137 j = adap->xfer_timeout * 100; 138 do { 139 j--; 140 if (j <= 0) 141 return -EIO; 142 143 if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0) 144 j = 0; 145 else 146 udelay(1); 147 } while (j > 0); 148 149 *out = RD(adap, PSC_SMBTXRX); 150 151 return 0; 152 } 153 154 static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf, 155 unsigned int len) 156 { 157 int i; 158 159 if (len == 0) 160 return 0; 161 162 /* A read is performed by stuffing the transmit fifo with 163 * zero bytes for timing, waiting for bytes to appear in the 164 * receive fifo, then reading the bytes. 165 */ 166 i = 0; 167 while (i < (len - 1)) { 168 WR(adap, PSC_SMBTXRX, 0); 169 if (wait_for_rx_byte(adap, &buf[i])) 170 return -EIO; 171 172 i++; 173 } 174 175 /* The last byte has to indicate transfer done. */ 176 WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP); 177 if (wait_controller_done(adap)) 178 return -EIO; 179 180 buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff); 181 return 0; 182 } 183 184 static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf, 185 unsigned int len) 186 { 187 int i; 188 unsigned long data; 189 190 if (len == 0) 191 return 0; 192 193 i = 0; 194 while (i < (len-1)) { 195 data = buf[i]; 196 WR(adap, PSC_SMBTXRX, data); 197 if (wait_ack(adap)) 198 return -EIO; 199 i++; 200 } 201 202 /* The last byte has to indicate transfer done. */ 203 data = buf[i]; 204 data |= PSC_SMBTXRX_STP; 205 WR(adap, PSC_SMBTXRX, data); 206 if (wait_controller_done(adap)) 207 return -EIO; 208 return 0; 209 } 210 211 static int 212 au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) 213 { 214 struct i2c_au1550_data *adap = i2c_adap->algo_data; 215 struct i2c_msg *p; 216 int i, err = 0; 217 218 WR(adap, PSC_CTRL, PSC_CTRL_ENABLE); 219 220 for (i = 0; !err && i < num; i++) { 221 p = &msgs[i]; 222 err = do_address(adap, p->addr, p->flags & I2C_M_RD, 223 (p->len == 0)); 224 if (err || !p->len) 225 continue; 226 if (p->flags & I2C_M_RD) 227 err = i2c_read(adap, p->buf, p->len); 228 else 229 err = i2c_write(adap, p->buf, p->len); 230 } 231 232 /* Return the number of messages processed, or the error code. 233 */ 234 if (err == 0) 235 err = num; 236 237 WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND); 238 239 return err; 240 } 241 242 static u32 au1550_func(struct i2c_adapter *adap) 243 { 244 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 245 } 246 247 static const struct i2c_algorithm au1550_algo = { 248 .xfer = au1550_xfer, 249 .functionality = au1550_func, 250 }; 251 252 static void i2c_au1550_setup(struct i2c_au1550_data *priv) 253 { 254 unsigned long cfg; 255 256 WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); 257 WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE); 258 WR(priv, PSC_SMBCFG, 0); 259 WR(priv, PSC_CTRL, PSC_CTRL_ENABLE); 260 while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0) 261 cpu_relax(); 262 263 cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE; 264 WR(priv, PSC_SMBCFG, cfg); 265 266 /* Divide by 8 to get a 6.25 MHz clock. The later protocol 267 * timings are based on this clock. 268 */ 269 cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8); 270 WR(priv, PSC_SMBCFG, cfg); 271 WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK); 272 273 /* Set the protocol timer values. See Table 71 in the 274 * Au1550 Data Book for standard timing values. 275 */ 276 WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(20) | \ 277 PSC_SMBTMR_SET_PU(20) | PSC_SMBTMR_SET_SH(20) | \ 278 PSC_SMBTMR_SET_SU(20) | PSC_SMBTMR_SET_CL(20) | \ 279 PSC_SMBTMR_SET_CH(20)); 280 281 cfg |= PSC_SMBCFG_DE_ENABLE; 282 WR(priv, PSC_SMBCFG, cfg); 283 while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0) 284 cpu_relax(); 285 286 WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND); 287 } 288 289 static void i2c_au1550_disable(struct i2c_au1550_data *priv) 290 { 291 WR(priv, PSC_SMBCFG, 0); 292 WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); 293 } 294 295 /* 296 * registering functions to load algorithms at runtime 297 * Prior to calling us, the 50MHz clock frequency and routing 298 * must have been set up for the PSC indicated by the adapter. 299 */ 300 static int 301 i2c_au1550_probe(struct platform_device *pdev) 302 { 303 struct i2c_au1550_data *priv; 304 int ret; 305 306 priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_au1550_data), 307 GFP_KERNEL); 308 if (!priv) 309 return -ENOMEM; 310 311 priv->psc_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 312 if (IS_ERR(priv->psc_base)) 313 return PTR_ERR(priv->psc_base); 314 315 priv->xfer_timeout = 200; 316 317 priv->adap.nr = pdev->id; 318 priv->adap.algo = &au1550_algo; 319 priv->adap.algo_data = priv; 320 priv->adap.dev.parent = &pdev->dev; 321 strscpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); 322 323 /* Now, set up the PSC for SMBus PIO mode. */ 324 i2c_au1550_setup(priv); 325 326 ret = i2c_add_numbered_adapter(&priv->adap); 327 if (ret) { 328 i2c_au1550_disable(priv); 329 return ret; 330 } 331 332 platform_set_drvdata(pdev, priv); 333 return 0; 334 } 335 336 static void i2c_au1550_remove(struct platform_device *pdev) 337 { 338 struct i2c_au1550_data *priv = platform_get_drvdata(pdev); 339 340 i2c_del_adapter(&priv->adap); 341 i2c_au1550_disable(priv); 342 } 343 344 static int i2c_au1550_suspend(struct device *dev) 345 { 346 struct i2c_au1550_data *priv = dev_get_drvdata(dev); 347 348 i2c_au1550_disable(priv); 349 350 return 0; 351 } 352 353 static int i2c_au1550_resume(struct device *dev) 354 { 355 struct i2c_au1550_data *priv = dev_get_drvdata(dev); 356 357 i2c_au1550_setup(priv); 358 359 return 0; 360 } 361 362 static DEFINE_SIMPLE_DEV_PM_OPS(i2c_au1550_pmops, 363 i2c_au1550_suspend, i2c_au1550_resume); 364 365 static struct platform_driver au1xpsc_smbus_driver = { 366 .driver = { 367 .name = "au1xpsc_smbus", 368 .pm = pm_sleep_ptr(&i2c_au1550_pmops), 369 }, 370 .probe = i2c_au1550_probe, 371 .remove_new = i2c_au1550_remove, 372 }; 373 374 module_platform_driver(au1xpsc_smbus_driver); 375 376 MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC."); 377 MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550"); 378 MODULE_LICENSE("GPL"); 379 MODULE_ALIAS("platform:au1xpsc_smbus"); 380