1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2012, The Linux Foundation. All rights reserved. 3 * 4 * Description: CoreSight Trace Memory Controller driver 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/types.h> 11 #include <linux/device.h> 12 #include <linux/idr.h> 13 #include <linux/io.h> 14 #include <linux/iommu.h> 15 #include <linux/err.h> 16 #include <linux/fs.h> 17 #include <linux/miscdevice.h> 18 #include <linux/mutex.h> 19 #include <linux/property.h> 20 #include <linux/uaccess.h> 21 #include <linux/slab.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/spinlock.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/of.h> 26 #include <linux/coresight.h> 27 #include <linux/amba/bus.h> 28 #include <linux/platform_device.h> 29 30 #include "coresight-priv.h" 31 #include "coresight-tmc.h" 32 33 DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); 34 DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); 35 DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); 36 37 int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) 38 { 39 struct coresight_device *csdev = drvdata->csdev; 40 struct csdev_access *csa = &csdev->access; 41 42 /* Ensure formatter, unformatter and hardware fifo are empty */ 43 if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { 44 dev_err(&csdev->dev, 45 "timeout while waiting for TMC to be Ready\n"); 46 return -EBUSY; 47 } 48 return 0; 49 } 50 51 void tmc_flush_and_stop(struct tmc_drvdata *drvdata) 52 { 53 struct coresight_device *csdev = drvdata->csdev; 54 struct csdev_access *csa = &csdev->access; 55 u32 ffcr; 56 57 ffcr = readl_relaxed(drvdata->base + TMC_FFCR); 58 ffcr |= TMC_FFCR_STOP_ON_FLUSH; 59 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); 60 ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT); 61 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); 62 /* Ensure flush completes */ 63 if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { 64 dev_err(&csdev->dev, 65 "timeout while waiting for completion of Manual Flush\n"); 66 } 67 68 tmc_wait_for_tmcready(drvdata); 69 } 70 71 void tmc_enable_hw(struct tmc_drvdata *drvdata) 72 { 73 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL); 74 } 75 76 void tmc_disable_hw(struct tmc_drvdata *drvdata) 77 { 78 writel_relaxed(0x0, drvdata->base + TMC_CTL); 79 } 80 81 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata) 82 { 83 u32 mask = 0; 84 85 /* 86 * When moving RRP or an offset address forward, the new values must 87 * be byte-address aligned to the width of the trace memory databus 88 * _and_ to a frame boundary (16 byte), whichever is the biggest. For 89 * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four 90 * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must 91 * be 0s. 92 */ 93 switch (drvdata->memwidth) { 94 case TMC_MEM_INTF_WIDTH_32BITS: 95 case TMC_MEM_INTF_WIDTH_64BITS: 96 case TMC_MEM_INTF_WIDTH_128BITS: 97 mask = GENMASK(31, 4); 98 break; 99 case TMC_MEM_INTF_WIDTH_256BITS: 100 mask = GENMASK(31, 5); 101 break; 102 } 103 104 return mask; 105 } 106 107 static int tmc_read_prepare(struct tmc_drvdata *drvdata) 108 { 109 int ret = 0; 110 111 switch (drvdata->config_type) { 112 case TMC_CONFIG_TYPE_ETB: 113 case TMC_CONFIG_TYPE_ETF: 114 ret = tmc_read_prepare_etb(drvdata); 115 break; 116 case TMC_CONFIG_TYPE_ETR: 117 ret = tmc_read_prepare_etr(drvdata); 118 break; 119 default: 120 ret = -EINVAL; 121 } 122 123 if (!ret) 124 dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); 125 126 return ret; 127 } 128 129 static int tmc_read_unprepare(struct tmc_drvdata *drvdata) 130 { 131 int ret = 0; 132 133 switch (drvdata->config_type) { 134 case TMC_CONFIG_TYPE_ETB: 135 case TMC_CONFIG_TYPE_ETF: 136 ret = tmc_read_unprepare_etb(drvdata); 137 break; 138 case TMC_CONFIG_TYPE_ETR: 139 ret = tmc_read_unprepare_etr(drvdata); 140 break; 141 default: 142 ret = -EINVAL; 143 } 144 145 if (!ret) 146 dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); 147 148 return ret; 149 } 150 151 static int tmc_open(struct inode *inode, struct file *file) 152 { 153 int ret; 154 struct tmc_drvdata *drvdata = container_of(file->private_data, 155 struct tmc_drvdata, miscdev); 156 157 ret = tmc_read_prepare(drvdata); 158 if (ret) 159 return ret; 160 161 nonseekable_open(inode, file); 162 163 dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__); 164 return 0; 165 } 166 167 static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, 168 loff_t pos, size_t len, char **bufpp) 169 { 170 switch (drvdata->config_type) { 171 case TMC_CONFIG_TYPE_ETB: 172 case TMC_CONFIG_TYPE_ETF: 173 return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); 174 case TMC_CONFIG_TYPE_ETR: 175 return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); 176 } 177 178 return -EINVAL; 179 } 180 181 static ssize_t tmc_read(struct file *file, char __user *data, size_t len, 182 loff_t *ppos) 183 { 184 char *bufp; 185 ssize_t actual; 186 struct tmc_drvdata *drvdata = container_of(file->private_data, 187 struct tmc_drvdata, miscdev); 188 actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp); 189 if (actual <= 0) 190 return 0; 191 192 if (copy_to_user(data, bufp, actual)) { 193 dev_dbg(&drvdata->csdev->dev, 194 "%s: copy_to_user failed\n", __func__); 195 return -EFAULT; 196 } 197 198 *ppos += actual; 199 dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); 200 201 return actual; 202 } 203 204 static int tmc_release(struct inode *inode, struct file *file) 205 { 206 int ret; 207 struct tmc_drvdata *drvdata = container_of(file->private_data, 208 struct tmc_drvdata, miscdev); 209 210 ret = tmc_read_unprepare(drvdata); 211 if (ret) 212 return ret; 213 214 dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__); 215 return 0; 216 } 217 218 static const struct file_operations tmc_fops = { 219 .owner = THIS_MODULE, 220 .open = tmc_open, 221 .read = tmc_read, 222 .release = tmc_release, 223 .llseek = no_llseek, 224 }; 225 226 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid) 227 { 228 enum tmc_mem_intf_width memwidth; 229 230 /* 231 * Excerpt from the TRM: 232 * 233 * DEVID::MEMWIDTH[10:8] 234 * 0x2 Memory interface databus is 32 bits wide. 235 * 0x3 Memory interface databus is 64 bits wide. 236 * 0x4 Memory interface databus is 128 bits wide. 237 * 0x5 Memory interface databus is 256 bits wide. 238 */ 239 switch (BMVAL(devid, 8, 10)) { 240 case 0x2: 241 memwidth = TMC_MEM_INTF_WIDTH_32BITS; 242 break; 243 case 0x3: 244 memwidth = TMC_MEM_INTF_WIDTH_64BITS; 245 break; 246 case 0x4: 247 memwidth = TMC_MEM_INTF_WIDTH_128BITS; 248 break; 249 case 0x5: 250 memwidth = TMC_MEM_INTF_WIDTH_256BITS; 251 break; 252 default: 253 memwidth = 0; 254 } 255 256 return memwidth; 257 } 258 259 static struct attribute *coresight_tmc_mgmt_attrs[] = { 260 coresight_simple_reg32(rsz, TMC_RSZ), 261 coresight_simple_reg32(sts, TMC_STS), 262 coresight_simple_reg64(rrp, TMC_RRP, TMC_RRPHI), 263 coresight_simple_reg64(rwp, TMC_RWP, TMC_RWPHI), 264 coresight_simple_reg32(trg, TMC_TRG), 265 coresight_simple_reg32(ctl, TMC_CTL), 266 coresight_simple_reg32(ffsr, TMC_FFSR), 267 coresight_simple_reg32(ffcr, TMC_FFCR), 268 coresight_simple_reg32(mode, TMC_MODE), 269 coresight_simple_reg32(pscr, TMC_PSCR), 270 coresight_simple_reg32(devid, CORESIGHT_DEVID), 271 coresight_simple_reg64(dba, TMC_DBALO, TMC_DBAHI), 272 coresight_simple_reg32(axictl, TMC_AXICTL), 273 coresight_simple_reg32(authstatus, TMC_AUTHSTATUS), 274 NULL, 275 }; 276 277 static ssize_t trigger_cntr_show(struct device *dev, 278 struct device_attribute *attr, char *buf) 279 { 280 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 281 unsigned long val = drvdata->trigger_cntr; 282 283 return sprintf(buf, "%#lx\n", val); 284 } 285 286 static ssize_t trigger_cntr_store(struct device *dev, 287 struct device_attribute *attr, 288 const char *buf, size_t size) 289 { 290 int ret; 291 unsigned long val; 292 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 293 294 ret = kstrtoul(buf, 16, &val); 295 if (ret) 296 return ret; 297 298 drvdata->trigger_cntr = val; 299 return size; 300 } 301 static DEVICE_ATTR_RW(trigger_cntr); 302 303 static ssize_t buffer_size_show(struct device *dev, 304 struct device_attribute *attr, char *buf) 305 { 306 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 307 308 return sprintf(buf, "%#x\n", drvdata->size); 309 } 310 311 static ssize_t buffer_size_store(struct device *dev, 312 struct device_attribute *attr, 313 const char *buf, size_t size) 314 { 315 int ret; 316 unsigned long val; 317 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 318 319 /* Only permitted for TMC-ETRs */ 320 if (drvdata->config_type != TMC_CONFIG_TYPE_ETR) 321 return -EPERM; 322 323 ret = kstrtoul(buf, 0, &val); 324 if (ret) 325 return ret; 326 /* The buffer size should be page aligned */ 327 if (val & (PAGE_SIZE - 1)) 328 return -EINVAL; 329 drvdata->size = val; 330 return size; 331 } 332 333 static DEVICE_ATTR_RW(buffer_size); 334 335 static struct attribute *coresight_tmc_attrs[] = { 336 &dev_attr_trigger_cntr.attr, 337 &dev_attr_buffer_size.attr, 338 NULL, 339 }; 340 341 static const struct attribute_group coresight_tmc_group = { 342 .attrs = coresight_tmc_attrs, 343 }; 344 345 static const struct attribute_group coresight_tmc_mgmt_group = { 346 .attrs = coresight_tmc_mgmt_attrs, 347 .name = "mgmt", 348 }; 349 350 static const struct attribute_group *coresight_etf_groups[] = { 351 &coresight_tmc_group, 352 &coresight_tmc_mgmt_group, 353 NULL, 354 }; 355 356 static const struct attribute_group *coresight_etr_groups[] = { 357 &coresight_etr_group, 358 &coresight_tmc_group, 359 &coresight_tmc_mgmt_group, 360 NULL, 361 }; 362 363 static inline bool tmc_etr_can_use_sg(struct device *dev) 364 { 365 int ret; 366 u8 val_u8; 367 368 /* 369 * Presence of the property 'arm,scatter-gather' is checked 370 * on the platform for the feature support, rather than its 371 * value. 372 */ 373 if (is_of_node(dev->fwnode)) { 374 return fwnode_property_present(dev->fwnode, "arm,scatter-gather"); 375 } else if (is_acpi_device_node(dev->fwnode)) { 376 /* 377 * TMC_DEVID_NOSCAT test in tmc_etr_setup_caps(), has already ensured 378 * this property is only checked for Coresight SoC 400 TMC configured 379 * as ETR. 380 */ 381 ret = fwnode_property_read_u8(dev->fwnode, "arm-armhc97c-sg-enable", &val_u8); 382 if (!ret) 383 return !!val_u8; 384 385 if (fwnode_property_present(dev->fwnode, "arm,scatter-gather")) { 386 pr_warn_once("Deprecated ACPI property - arm,scatter-gather\n"); 387 return true; 388 } 389 } 390 return false; 391 } 392 393 static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata) 394 { 395 u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS); 396 397 return (auth & TMC_AUTH_NSID_MASK) == 0x3; 398 } 399 400 static const struct amba_id tmc_ids[]; 401 402 /* Detect and initialise the capabilities of a TMC ETR */ 403 static int tmc_etr_setup_caps(struct device *parent, u32 devid, 404 struct csdev_access *access) 405 { 406 int rc; 407 u32 tmc_pid, dma_mask = 0; 408 struct tmc_drvdata *drvdata = dev_get_drvdata(parent); 409 void *dev_caps; 410 411 if (!tmc_etr_has_non_secure_access(drvdata)) 412 return -EACCES; 413 414 tmc_pid = coresight_get_pid(access); 415 dev_caps = coresight_get_uci_data_from_amba(tmc_ids, tmc_pid); 416 417 /* Set the unadvertised capabilities */ 418 tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps); 419 420 if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(parent)) 421 tmc_etr_set_cap(drvdata, TMC_ETR_SG); 422 423 /* Check if the AXI address width is available */ 424 if (devid & TMC_DEVID_AXIAW_VALID) 425 dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) & 426 TMC_DEVID_AXIAW_MASK); 427 428 /* 429 * Unless specified in the device configuration, ETR uses a 40-bit 430 * AXI master in place of the embedded SRAM of ETB/ETF. 431 */ 432 switch (dma_mask) { 433 case 32: 434 case 40: 435 case 44: 436 case 48: 437 case 52: 438 dev_info(parent, "Detected dma mask %dbits\n", dma_mask); 439 break; 440 default: 441 dma_mask = 40; 442 } 443 444 rc = dma_set_mask_and_coherent(parent, DMA_BIT_MASK(dma_mask)); 445 if (rc) 446 dev_err(parent, "Failed to setup DMA mask: %d\n", rc); 447 return rc; 448 } 449 450 static u32 tmc_etr_get_default_buffer_size(struct device *dev) 451 { 452 u32 size; 453 454 if (fwnode_property_read_u32(dev->fwnode, "arm,buffer-size", &size)) 455 size = SZ_1M; 456 return size; 457 } 458 459 static u32 tmc_etr_get_max_burst_size(struct device *dev) 460 { 461 u32 burst_size; 462 463 if (fwnode_property_read_u32(dev->fwnode, "arm,max-burst-size", 464 &burst_size)) 465 return TMC_AXICTL_WR_BURST_16; 466 467 /* Only permissible values are 0 to 15 */ 468 if (burst_size > 0xF) 469 burst_size = TMC_AXICTL_WR_BURST_16; 470 471 return burst_size; 472 } 473 474 static int __tmc_probe(struct device *dev, struct resource *res) 475 { 476 int ret = 0; 477 u32 devid; 478 void __iomem *base; 479 struct coresight_platform_data *pdata = NULL; 480 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 481 struct coresight_desc desc = { 0 }; 482 struct coresight_dev_list *dev_list = NULL; 483 484 ret = -ENOMEM; 485 486 /* Validity for the resource is already checked by the AMBA core */ 487 base = devm_ioremap_resource(dev, res); 488 if (IS_ERR(base)) { 489 ret = PTR_ERR(base); 490 goto out; 491 } 492 493 drvdata->base = base; 494 desc.access = CSDEV_ACCESS_IOMEM(base); 495 496 spin_lock_init(&drvdata->spinlock); 497 498 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); 499 drvdata->config_type = BMVAL(devid, 6, 7); 500 drvdata->memwidth = tmc_get_memwidth(devid); 501 /* This device is not associated with a session */ 502 drvdata->pid = -1; 503 drvdata->etr_mode = ETR_MODE_AUTO; 504 505 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { 506 drvdata->size = tmc_etr_get_default_buffer_size(dev); 507 drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev); 508 } else { 509 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; 510 } 511 512 desc.dev = dev; 513 514 switch (drvdata->config_type) { 515 case TMC_CONFIG_TYPE_ETB: 516 desc.groups = coresight_etf_groups; 517 desc.type = CORESIGHT_DEV_TYPE_SINK; 518 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 519 desc.ops = &tmc_etb_cs_ops; 520 dev_list = &etb_devs; 521 break; 522 case TMC_CONFIG_TYPE_ETR: 523 desc.groups = coresight_etr_groups; 524 desc.type = CORESIGHT_DEV_TYPE_SINK; 525 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; 526 desc.ops = &tmc_etr_cs_ops; 527 ret = tmc_etr_setup_caps(dev, devid, &desc.access); 528 if (ret) 529 goto out; 530 idr_init(&drvdata->idr); 531 mutex_init(&drvdata->idr_mutex); 532 dev_list = &etr_devs; 533 break; 534 case TMC_CONFIG_TYPE_ETF: 535 desc.groups = coresight_etf_groups; 536 desc.type = CORESIGHT_DEV_TYPE_LINKSINK; 537 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 538 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; 539 desc.ops = &tmc_etf_cs_ops; 540 dev_list = &etf_devs; 541 break; 542 default: 543 pr_err("%s: Unsupported TMC config\n", desc.name); 544 ret = -EINVAL; 545 goto out; 546 } 547 548 desc.name = coresight_alloc_device_name(dev_list, dev); 549 if (!desc.name) { 550 ret = -ENOMEM; 551 goto out; 552 } 553 554 pdata = coresight_get_platform_data(dev); 555 if (IS_ERR(pdata)) { 556 ret = PTR_ERR(pdata); 557 goto out; 558 } 559 dev->platform_data = pdata; 560 desc.pdata = pdata; 561 562 drvdata->csdev = coresight_register(&desc); 563 if (IS_ERR(drvdata->csdev)) { 564 ret = PTR_ERR(drvdata->csdev); 565 goto out; 566 } 567 568 drvdata->miscdev.name = desc.name; 569 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; 570 drvdata->miscdev.fops = &tmc_fops; 571 ret = misc_register(&drvdata->miscdev); 572 if (ret) 573 coresight_unregister(drvdata->csdev); 574 out: 575 return ret; 576 } 577 578 static int tmc_probe(struct amba_device *adev, const struct amba_id *id) 579 { 580 struct tmc_drvdata *drvdata; 581 int ret; 582 583 drvdata = devm_kzalloc(&adev->dev, sizeof(*drvdata), GFP_KERNEL); 584 if (!drvdata) 585 return -ENOMEM; 586 587 amba_set_drvdata(adev, drvdata); 588 ret = __tmc_probe(&adev->dev, &adev->res); 589 if (!ret) 590 pm_runtime_put(&adev->dev); 591 592 return ret; 593 } 594 595 static void tmc_shutdown(struct amba_device *adev) 596 { 597 unsigned long flags; 598 struct tmc_drvdata *drvdata = amba_get_drvdata(adev); 599 600 spin_lock_irqsave(&drvdata->spinlock, flags); 601 602 if (coresight_get_mode(drvdata->csdev) == CS_MODE_DISABLED) 603 goto out; 604 605 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) 606 tmc_etr_disable_hw(drvdata); 607 608 /* 609 * We do not care about coresight unregister here unlike remove 610 * callback which is required for making coresight modular since 611 * the system is going down after this. 612 */ 613 out: 614 spin_unlock_irqrestore(&drvdata->spinlock, flags); 615 } 616 617 static void __tmc_remove(struct device *dev) 618 { 619 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 620 621 /* 622 * Since misc_open() holds a refcount on the f_ops, which is 623 * etb fops in this case, device is there until last file 624 * handler to this device is closed. 625 */ 626 misc_deregister(&drvdata->miscdev); 627 coresight_unregister(drvdata->csdev); 628 } 629 630 static void tmc_remove(struct amba_device *adev) 631 { 632 __tmc_remove(&adev->dev); 633 } 634 635 static const struct amba_id tmc_ids[] = { 636 CS_AMBA_ID(0x000bb961), 637 /* Coresight SoC 600 TMC-ETR/ETS */ 638 CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS), 639 /* Coresight SoC 600 TMC-ETB */ 640 CS_AMBA_ID(0x000bb9e9), 641 /* Coresight SoC 600 TMC-ETF */ 642 CS_AMBA_ID(0x000bb9ea), 643 { 0, 0, NULL }, 644 }; 645 646 MODULE_DEVICE_TABLE(amba, tmc_ids); 647 648 static struct amba_driver tmc_driver = { 649 .drv = { 650 .name = "coresight-tmc", 651 .suppress_bind_attrs = true, 652 }, 653 .probe = tmc_probe, 654 .shutdown = tmc_shutdown, 655 .remove = tmc_remove, 656 .id_table = tmc_ids, 657 }; 658 659 static int tmc_platform_probe(struct platform_device *pdev) 660 { 661 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 662 struct tmc_drvdata *drvdata; 663 int ret = 0; 664 665 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); 666 if (!drvdata) 667 return -ENOMEM; 668 669 drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev); 670 if (IS_ERR(drvdata->pclk)) 671 return -ENODEV; 672 673 dev_set_drvdata(&pdev->dev, drvdata); 674 pm_runtime_get_noresume(&pdev->dev); 675 pm_runtime_set_active(&pdev->dev); 676 pm_runtime_enable(&pdev->dev); 677 678 ret = __tmc_probe(&pdev->dev, res); 679 pm_runtime_put(&pdev->dev); 680 if (ret) 681 pm_runtime_disable(&pdev->dev); 682 683 return ret; 684 } 685 686 static void tmc_platform_remove(struct platform_device *pdev) 687 { 688 struct tmc_drvdata *drvdata = dev_get_drvdata(&pdev->dev); 689 690 if (WARN_ON(!drvdata)) 691 return; 692 693 __tmc_remove(&pdev->dev); 694 pm_runtime_disable(&pdev->dev); 695 if (!IS_ERR_OR_NULL(drvdata->pclk)) 696 clk_put(drvdata->pclk); 697 } 698 699 #ifdef CONFIG_PM 700 static int tmc_runtime_suspend(struct device *dev) 701 { 702 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 703 704 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) 705 clk_disable_unprepare(drvdata->pclk); 706 return 0; 707 } 708 709 static int tmc_runtime_resume(struct device *dev) 710 { 711 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 712 713 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) 714 clk_prepare_enable(drvdata->pclk); 715 return 0; 716 } 717 #endif 718 719 static const struct dev_pm_ops tmc_dev_pm_ops = { 720 SET_RUNTIME_PM_OPS(tmc_runtime_suspend, tmc_runtime_resume, NULL) 721 }; 722 723 #ifdef CONFIG_ACPI 724 static const struct acpi_device_id tmc_acpi_ids[] = { 725 {"ARMHC501", 0, 0, 0}, /* ARM CoreSight ETR */ 726 {"ARMHC97C", 0, 0, 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */ 727 {}, 728 }; 729 MODULE_DEVICE_TABLE(acpi, tmc_acpi_ids); 730 #endif 731 732 static struct platform_driver tmc_platform_driver = { 733 .probe = tmc_platform_probe, 734 .remove_new = tmc_platform_remove, 735 .driver = { 736 .name = "coresight-tmc-platform", 737 .acpi_match_table = ACPI_PTR(tmc_acpi_ids), 738 .suppress_bind_attrs = true, 739 .pm = &tmc_dev_pm_ops, 740 }, 741 }; 742 743 static int __init tmc_init(void) 744 { 745 return coresight_init_driver("tmc", &tmc_driver, &tmc_platform_driver); 746 } 747 748 static void __exit tmc_exit(void) 749 { 750 coresight_remove_driver(&tmc_driver, &tmc_platform_driver); 751 } 752 module_init(tmc_init); 753 module_exit(tmc_exit); 754 755 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>"); 756 MODULE_DESCRIPTION("Arm CoreSight Trace Memory Controller driver"); 757 MODULE_LICENSE("GPL v2"); 758