1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2012, The Linux Foundation. All rights reserved. 3 * 4 * Description: CoreSight Trace Memory Controller driver 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/types.h> 11 #include <linux/device.h> 12 #include <linux/idr.h> 13 #include <linux/io.h> 14 #include <linux/iommu.h> 15 #include <linux/err.h> 16 #include <linux/fs.h> 17 #include <linux/miscdevice.h> 18 #include <linux/mutex.h> 19 #include <linux/property.h> 20 #include <linux/uaccess.h> 21 #include <linux/slab.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/spinlock.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/of_reserved_mem.h> 28 #include <linux/coresight.h> 29 #include <linux/amba/bus.h> 30 #include <linux/platform_device.h> 31 32 #include "coresight-priv.h" 33 #include "coresight-tmc.h" 34 35 DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); 36 DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); 37 DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); 38 39 int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) 40 { 41 struct coresight_device *csdev = drvdata->csdev; 42 struct csdev_access *csa = &csdev->access; 43 44 /* Ensure formatter, unformatter and hardware fifo are empty */ 45 if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { 46 dev_err(&csdev->dev, 47 "timeout while waiting for TMC to be Ready\n"); 48 return -EBUSY; 49 } 50 return 0; 51 } 52 53 void tmc_flush_and_stop(struct tmc_drvdata *drvdata) 54 { 55 struct coresight_device *csdev = drvdata->csdev; 56 struct csdev_access *csa = &csdev->access; 57 u32 ffcr; 58 59 ffcr = readl_relaxed(drvdata->base + TMC_FFCR); 60 ffcr |= TMC_FFCR_STOP_ON_FLUSH; 61 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); 62 ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT); 63 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); 64 /* Ensure flush completes */ 65 if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { 66 dev_err(&csdev->dev, 67 "timeout while waiting for completion of Manual Flush\n"); 68 } 69 70 tmc_wait_for_tmcready(drvdata); 71 } 72 73 void tmc_enable_hw(struct tmc_drvdata *drvdata) 74 { 75 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL); 76 } 77 78 void tmc_disable_hw(struct tmc_drvdata *drvdata) 79 { 80 writel_relaxed(0x0, drvdata->base + TMC_CTL); 81 } 82 83 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata) 84 { 85 u32 mask = 0; 86 87 /* 88 * When moving RRP or an offset address forward, the new values must 89 * be byte-address aligned to the width of the trace memory databus 90 * _and_ to a frame boundary (16 byte), whichever is the biggest. For 91 * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four 92 * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must 93 * be 0s. 94 */ 95 switch (drvdata->memwidth) { 96 case TMC_MEM_INTF_WIDTH_32BITS: 97 case TMC_MEM_INTF_WIDTH_64BITS: 98 case TMC_MEM_INTF_WIDTH_128BITS: 99 mask = GENMASK(31, 4); 100 break; 101 case TMC_MEM_INTF_WIDTH_256BITS: 102 mask = GENMASK(31, 5); 103 break; 104 } 105 106 return mask; 107 } 108 109 static bool is_tmc_crashdata_valid(struct tmc_drvdata *drvdata) 110 { 111 struct tmc_crash_metadata *mdata; 112 113 if (!tmc_has_reserved_buffer(drvdata) || 114 !tmc_has_crash_mdata_buffer(drvdata)) 115 return false; 116 117 mdata = drvdata->crash_mdata.vaddr; 118 119 /* Check version match */ 120 if (mdata->version != CS_CRASHDATA_VERSION) 121 return false; 122 123 /* Check for valid metadata */ 124 if (!mdata->valid) { 125 dev_dbg(&drvdata->csdev->dev, 126 "Data invalid in tmc crash metadata\n"); 127 return false; 128 } 129 130 /* 131 * Buffer address given by metadata for retrieval of trace data 132 * from previous boot is expected to be same as the reserved 133 * trace buffer memory region provided through DTS 134 */ 135 if (drvdata->resrv_buf.paddr != mdata->trace_paddr) { 136 dev_dbg(&drvdata->csdev->dev, 137 "Trace buffer address of previous boot invalid\n"); 138 return false; 139 } 140 141 /* Check data integrity of metadata */ 142 if (mdata->crc32_mdata != find_crash_metadata_crc(mdata)) { 143 dev_err(&drvdata->csdev->dev, 144 "CRC mismatch in tmc crash metadata\n"); 145 return false; 146 } 147 /* Check data integrity of tracedata */ 148 if (mdata->crc32_tdata != find_crash_tracedata_crc(drvdata, mdata)) { 149 dev_err(&drvdata->csdev->dev, 150 "CRC mismatch in tmc crash tracedata\n"); 151 return false; 152 } 153 154 return true; 155 } 156 157 static inline ssize_t tmc_get_resvbuf_trace(struct tmc_drvdata *drvdata, 158 loff_t pos, size_t len, char **bufpp) 159 { 160 s64 offset; 161 ssize_t actual = len; 162 struct tmc_resrv_buf *rbuf = &drvdata->resrv_buf; 163 164 if (pos + actual > rbuf->len) 165 actual = rbuf->len - pos; 166 if (actual <= 0) 167 return 0; 168 169 /* Compute the offset from which we read the data */ 170 offset = rbuf->offset + pos; 171 if (offset >= rbuf->size) 172 offset -= rbuf->size; 173 174 /* Adjust the length to limit this transaction to end of buffer */ 175 actual = (actual < (rbuf->size - offset)) ? 176 actual : rbuf->size - offset; 177 178 *bufpp = (char *)rbuf->vaddr + offset; 179 180 return actual; 181 } 182 183 static int tmc_prepare_crashdata(struct tmc_drvdata *drvdata) 184 { 185 char *bufp; 186 ssize_t len; 187 u32 status, size; 188 u64 rrp, rwp, dba; 189 struct tmc_resrv_buf *rbuf; 190 struct tmc_crash_metadata *mdata; 191 192 mdata = drvdata->crash_mdata.vaddr; 193 rbuf = &drvdata->resrv_buf; 194 195 rrp = mdata->tmc_rrp; 196 rwp = mdata->tmc_rwp; 197 dba = mdata->tmc_dba; 198 status = mdata->tmc_sts; 199 size = mdata->tmc_ram_size << 2; 200 201 /* Sync the buffer pointers */ 202 rbuf->offset = rrp - dba; 203 if (status & TMC_STS_FULL) 204 rbuf->len = size; 205 else 206 rbuf->len = rwp - rrp; 207 208 /* Additional sanity checks for validating metadata */ 209 if ((rbuf->offset > size) || 210 (rbuf->len > size)) { 211 dev_dbg(&drvdata->csdev->dev, 212 "Offset and length invalid in tmc crash metadata\n"); 213 return -EINVAL; 214 } 215 216 if (status & TMC_STS_FULL) { 217 len = tmc_get_resvbuf_trace(drvdata, 0x0, 218 CORESIGHT_BARRIER_PKT_SIZE, &bufp); 219 if (len >= CORESIGHT_BARRIER_PKT_SIZE) { 220 coresight_insert_barrier_packet(bufp); 221 /* Recalculate crc */ 222 mdata->crc32_tdata = find_crash_tracedata_crc(drvdata, 223 mdata); 224 mdata->crc32_mdata = find_crash_metadata_crc(mdata); 225 } 226 } 227 228 return 0; 229 } 230 231 static int tmc_read_prepare(struct tmc_drvdata *drvdata) 232 { 233 int ret = 0; 234 235 switch (drvdata->config_type) { 236 case TMC_CONFIG_TYPE_ETB: 237 case TMC_CONFIG_TYPE_ETF: 238 ret = tmc_read_prepare_etb(drvdata); 239 break; 240 case TMC_CONFIG_TYPE_ETR: 241 ret = tmc_read_prepare_etr(drvdata); 242 break; 243 default: 244 ret = -EINVAL; 245 } 246 247 if (!ret) 248 dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); 249 250 return ret; 251 } 252 253 static int tmc_read_unprepare(struct tmc_drvdata *drvdata) 254 { 255 int ret = 0; 256 257 switch (drvdata->config_type) { 258 case TMC_CONFIG_TYPE_ETB: 259 case TMC_CONFIG_TYPE_ETF: 260 ret = tmc_read_unprepare_etb(drvdata); 261 break; 262 case TMC_CONFIG_TYPE_ETR: 263 ret = tmc_read_unprepare_etr(drvdata); 264 break; 265 default: 266 ret = -EINVAL; 267 } 268 269 if (!ret) 270 dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); 271 272 return ret; 273 } 274 275 static int tmc_open(struct inode *inode, struct file *file) 276 { 277 int ret; 278 struct tmc_drvdata *drvdata = container_of(file->private_data, 279 struct tmc_drvdata, miscdev); 280 281 ret = tmc_read_prepare(drvdata); 282 if (ret) 283 return ret; 284 285 nonseekable_open(inode, file); 286 287 dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__); 288 return 0; 289 } 290 291 static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, 292 char **bufpp) 293 { 294 switch (drvdata->config_type) { 295 case TMC_CONFIG_TYPE_ETB: 296 case TMC_CONFIG_TYPE_ETF: 297 return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); 298 case TMC_CONFIG_TYPE_ETR: 299 return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); 300 } 301 302 return -EINVAL; 303 } 304 305 static ssize_t tmc_read(struct file *file, char __user *data, size_t len, 306 loff_t *ppos) 307 { 308 char *bufp; 309 ssize_t actual; 310 struct tmc_drvdata *drvdata = container_of(file->private_data, 311 struct tmc_drvdata, miscdev); 312 actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp); 313 if (actual <= 0) 314 return 0; 315 316 if (copy_to_user(data, bufp, actual)) { 317 dev_dbg(&drvdata->csdev->dev, 318 "%s: copy_to_user failed\n", __func__); 319 return -EFAULT; 320 } 321 322 *ppos += actual; 323 dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); 324 325 return actual; 326 } 327 328 static int tmc_release(struct inode *inode, struct file *file) 329 { 330 int ret; 331 struct tmc_drvdata *drvdata = container_of(file->private_data, 332 struct tmc_drvdata, miscdev); 333 334 ret = tmc_read_unprepare(drvdata); 335 if (ret) 336 return ret; 337 338 dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__); 339 return 0; 340 } 341 342 static const struct file_operations tmc_fops = { 343 .owner = THIS_MODULE, 344 .open = tmc_open, 345 .read = tmc_read, 346 .release = tmc_release, 347 }; 348 349 static int tmc_crashdata_open(struct inode *inode, struct file *file) 350 { 351 int err = 0; 352 unsigned long flags; 353 struct tmc_resrv_buf *rbuf; 354 struct tmc_crash_metadata *mdata; 355 struct tmc_drvdata *drvdata = container_of(file->private_data, 356 struct tmc_drvdata, 357 crashdev); 358 359 mdata = drvdata->crash_mdata.vaddr; 360 rbuf = &drvdata->resrv_buf; 361 362 raw_spin_lock_irqsave(&drvdata->spinlock, flags); 363 if (mdata->valid) 364 rbuf->reading = true; 365 else 366 err = -ENOENT; 367 raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); 368 if (err) 369 goto exit; 370 371 nonseekable_open(inode, file); 372 dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__); 373 exit: 374 return err; 375 } 376 377 static ssize_t tmc_crashdata_read(struct file *file, char __user *data, 378 size_t len, loff_t *ppos) 379 { 380 char *bufp; 381 ssize_t actual; 382 struct tmc_drvdata *drvdata = container_of(file->private_data, 383 struct tmc_drvdata, 384 crashdev); 385 386 actual = tmc_get_resvbuf_trace(drvdata, *ppos, len, &bufp); 387 if (actual <= 0) 388 return 0; 389 390 if (copy_to_user(data, bufp, actual)) { 391 dev_dbg(&drvdata->csdev->dev, 392 "%s: copy_to_user failed\n", __func__); 393 return -EFAULT; 394 } 395 396 *ppos += actual; 397 dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); 398 399 return actual; 400 } 401 402 static int tmc_crashdata_release(struct inode *inode, struct file *file) 403 { 404 int ret = 0; 405 unsigned long flags; 406 struct tmc_resrv_buf *rbuf; 407 struct tmc_drvdata *drvdata = container_of(file->private_data, 408 struct tmc_drvdata, 409 crashdev); 410 411 rbuf = &drvdata->resrv_buf; 412 raw_spin_lock_irqsave(&drvdata->spinlock, flags); 413 rbuf->reading = false; 414 raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); 415 416 dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__); 417 return ret; 418 } 419 420 static const struct file_operations tmc_crashdata_fops = { 421 .owner = THIS_MODULE, 422 .open = tmc_crashdata_open, 423 .read = tmc_crashdata_read, 424 .release = tmc_crashdata_release, 425 }; 426 427 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid) 428 { 429 enum tmc_mem_intf_width memwidth; 430 431 /* 432 * Excerpt from the TRM: 433 * 434 * DEVID::MEMWIDTH[10:8] 435 * 0x2 Memory interface databus is 32 bits wide. 436 * 0x3 Memory interface databus is 64 bits wide. 437 * 0x4 Memory interface databus is 128 bits wide. 438 * 0x5 Memory interface databus is 256 bits wide. 439 */ 440 switch (BMVAL(devid, 8, 10)) { 441 case 0x2: 442 memwidth = TMC_MEM_INTF_WIDTH_32BITS; 443 break; 444 case 0x3: 445 memwidth = TMC_MEM_INTF_WIDTH_64BITS; 446 break; 447 case 0x4: 448 memwidth = TMC_MEM_INTF_WIDTH_128BITS; 449 break; 450 case 0x5: 451 memwidth = TMC_MEM_INTF_WIDTH_256BITS; 452 break; 453 default: 454 memwidth = 0; 455 } 456 457 return memwidth; 458 } 459 460 static struct attribute *coresight_tmc_mgmt_attrs[] = { 461 coresight_simple_reg32(rsz, TMC_RSZ), 462 coresight_simple_reg32(sts, TMC_STS), 463 coresight_simple_reg64(rrp, TMC_RRP, TMC_RRPHI), 464 coresight_simple_reg64(rwp, TMC_RWP, TMC_RWPHI), 465 coresight_simple_reg32(trg, TMC_TRG), 466 coresight_simple_reg32(ctl, TMC_CTL), 467 coresight_simple_reg32(ffsr, TMC_FFSR), 468 coresight_simple_reg32(ffcr, TMC_FFCR), 469 coresight_simple_reg32(mode, TMC_MODE), 470 coresight_simple_reg32(pscr, TMC_PSCR), 471 coresight_simple_reg32(devid, CORESIGHT_DEVID), 472 coresight_simple_reg64(dba, TMC_DBALO, TMC_DBAHI), 473 coresight_simple_reg32(axictl, TMC_AXICTL), 474 coresight_simple_reg32(authstatus, TMC_AUTHSTATUS), 475 NULL, 476 }; 477 478 static ssize_t trigger_cntr_show(struct device *dev, 479 struct device_attribute *attr, char *buf) 480 { 481 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 482 unsigned long val = drvdata->trigger_cntr; 483 484 return sprintf(buf, "%#lx\n", val); 485 } 486 487 static ssize_t trigger_cntr_store(struct device *dev, 488 struct device_attribute *attr, 489 const char *buf, size_t size) 490 { 491 int ret; 492 unsigned long val; 493 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 494 495 ret = kstrtoul(buf, 16, &val); 496 if (ret) 497 return ret; 498 499 drvdata->trigger_cntr = val; 500 return size; 501 } 502 static DEVICE_ATTR_RW(trigger_cntr); 503 504 static ssize_t buffer_size_show(struct device *dev, 505 struct device_attribute *attr, char *buf) 506 { 507 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 508 509 return sprintf(buf, "%#x\n", drvdata->size); 510 } 511 512 static ssize_t buffer_size_store(struct device *dev, 513 struct device_attribute *attr, 514 const char *buf, size_t size) 515 { 516 int ret; 517 unsigned long val; 518 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 519 520 /* Only permitted for TMC-ETRs */ 521 if (drvdata->config_type != TMC_CONFIG_TYPE_ETR) 522 return -EPERM; 523 524 ret = kstrtoul(buf, 0, &val); 525 if (ret) 526 return ret; 527 /* The buffer size should be page aligned */ 528 if (val & (PAGE_SIZE - 1)) 529 return -EINVAL; 530 drvdata->size = val; 531 return size; 532 } 533 534 static DEVICE_ATTR_RW(buffer_size); 535 536 static ssize_t stop_on_flush_show(struct device *dev, 537 struct device_attribute *attr, char *buf) 538 { 539 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 540 541 return sprintf(buf, "%#x\n", drvdata->stop_on_flush); 542 } 543 544 static ssize_t stop_on_flush_store(struct device *dev, 545 struct device_attribute *attr, 546 const char *buf, size_t size) 547 { 548 int ret; 549 u8 val; 550 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 551 552 ret = kstrtou8(buf, 0, &val); 553 if (ret) 554 return ret; 555 if (val) 556 drvdata->stop_on_flush = true; 557 else 558 drvdata->stop_on_flush = false; 559 560 return size; 561 } 562 563 static DEVICE_ATTR_RW(stop_on_flush); 564 565 566 static struct attribute *coresight_tmc_attrs[] = { 567 &dev_attr_trigger_cntr.attr, 568 &dev_attr_buffer_size.attr, 569 &dev_attr_stop_on_flush.attr, 570 NULL, 571 }; 572 573 static const struct attribute_group coresight_tmc_group = { 574 .attrs = coresight_tmc_attrs, 575 }; 576 577 static const struct attribute_group coresight_tmc_mgmt_group = { 578 .attrs = coresight_tmc_mgmt_attrs, 579 .name = "mgmt", 580 }; 581 582 static const struct attribute_group *coresight_etf_groups[] = { 583 &coresight_tmc_group, 584 &coresight_tmc_mgmt_group, 585 NULL, 586 }; 587 588 static const struct attribute_group *coresight_etr_groups[] = { 589 &coresight_etr_group, 590 &coresight_tmc_group, 591 &coresight_tmc_mgmt_group, 592 NULL, 593 }; 594 595 static bool tmc_etr_can_use_sg(struct device *dev) 596 { 597 int ret; 598 u8 val_u8; 599 600 /* 601 * Presence of the property 'arm,scatter-gather' is checked 602 * on the platform for the feature support, rather than its 603 * value. 604 */ 605 if (is_of_node(dev->fwnode)) { 606 return fwnode_property_present(dev->fwnode, "arm,scatter-gather"); 607 } else if (is_acpi_device_node(dev->fwnode)) { 608 /* 609 * TMC_DEVID_NOSCAT test in tmc_etr_setup_caps(), has already ensured 610 * this property is only checked for Coresight SoC 400 TMC configured 611 * as ETR. 612 */ 613 ret = fwnode_property_read_u8(dev->fwnode, "arm-armhc97c-sg-enable", &val_u8); 614 if (!ret) 615 return !!val_u8; 616 617 if (fwnode_property_present(dev->fwnode, "arm,scatter-gather")) { 618 pr_warn_once("Deprecated ACPI property - arm,scatter-gather\n"); 619 return true; 620 } 621 } 622 return false; 623 } 624 625 static bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata) 626 { 627 u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS); 628 629 return (auth & TMC_AUTH_NSID_MASK) == 0x3; 630 } 631 632 static const struct amba_id tmc_ids[]; 633 634 static int of_tmc_get_reserved_resource_by_name(struct device *dev, 635 const char *name, 636 struct resource *res) 637 { 638 int rc = -ENODEV; 639 640 rc = of_reserved_mem_region_to_resource_byname(dev->of_node, name, res); 641 if (rc < 0) 642 return rc; 643 644 if (res->start == 0 || resource_size(res) == 0) 645 rc = -ENODEV; 646 647 return rc; 648 } 649 650 static void tmc_get_reserved_region(struct device *parent) 651 { 652 struct tmc_drvdata *drvdata = dev_get_drvdata(parent); 653 struct resource res; 654 655 if (of_tmc_get_reserved_resource_by_name(parent, "tracedata", &res)) 656 return; 657 658 drvdata->resrv_buf.vaddr = memremap(res.start, 659 resource_size(&res), 660 MEMREMAP_WC); 661 if (IS_ERR_OR_NULL(drvdata->resrv_buf.vaddr)) { 662 dev_err(parent, "Reserved trace buffer mapping failed\n"); 663 return; 664 } 665 666 drvdata->resrv_buf.paddr = res.start; 667 drvdata->resrv_buf.size = resource_size(&res); 668 669 if (of_tmc_get_reserved_resource_by_name(parent, "metadata", &res)) 670 return; 671 672 drvdata->crash_mdata.vaddr = memremap(res.start, 673 resource_size(&res), 674 MEMREMAP_WC); 675 if (IS_ERR_OR_NULL(drvdata->crash_mdata.vaddr)) { 676 dev_err(parent, "Metadata memory mapping failed\n"); 677 return; 678 } 679 680 drvdata->crash_mdata.paddr = res.start; 681 drvdata->crash_mdata.size = resource_size(&res); 682 } 683 684 /* Detect and initialise the capabilities of a TMC ETR */ 685 static int tmc_etr_setup_caps(struct device *parent, u32 devid, 686 struct csdev_access *access) 687 { 688 int rc; 689 u32 tmc_pid, dma_mask = 0; 690 struct tmc_drvdata *drvdata = dev_get_drvdata(parent); 691 void *dev_caps; 692 693 if (!tmc_etr_has_non_secure_access(drvdata)) 694 return -EACCES; 695 696 tmc_pid = coresight_get_pid(access); 697 dev_caps = coresight_get_uci_data_from_amba(tmc_ids, tmc_pid); 698 699 /* Set the unadvertised capabilities */ 700 tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps); 701 702 if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(parent)) 703 tmc_etr_set_cap(drvdata, TMC_ETR_SG); 704 705 /* Check if the AXI address width is available */ 706 if (devid & TMC_DEVID_AXIAW_VALID) 707 dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) & 708 TMC_DEVID_AXIAW_MASK); 709 710 /* 711 * Unless specified in the device configuration, ETR uses a 40-bit 712 * AXI master in place of the embedded SRAM of ETB/ETF. 713 */ 714 switch (dma_mask) { 715 case 32: 716 case 40: 717 case 44: 718 case 48: 719 case 52: 720 dev_info(parent, "Detected dma mask %dbits\n", dma_mask); 721 break; 722 default: 723 dma_mask = 40; 724 } 725 726 rc = dma_set_mask_and_coherent(parent, DMA_BIT_MASK(dma_mask)); 727 if (rc) 728 dev_err(parent, "Failed to setup DMA mask: %d\n", rc); 729 return rc; 730 } 731 732 static u32 tmc_etr_get_default_buffer_size(struct device *dev) 733 { 734 u32 size; 735 736 if (fwnode_property_read_u32(dev->fwnode, "arm,buffer-size", &size)) 737 size = SZ_1M; 738 return size; 739 } 740 741 static u32 tmc_etr_get_max_burst_size(struct device *dev) 742 { 743 u32 burst_size; 744 745 if (fwnode_property_read_u32(dev->fwnode, "arm,max-burst-size", 746 &burst_size)) 747 return TMC_AXICTL_WR_BURST_16; 748 749 /* Only permissible values are 0 to 15 */ 750 if (burst_size > 0xF) 751 burst_size = TMC_AXICTL_WR_BURST_16; 752 753 return burst_size; 754 } 755 756 static void register_crash_dev_interface(struct tmc_drvdata *drvdata, 757 const char *name) 758 { 759 drvdata->crashdev.name = 760 devm_kasprintf(&drvdata->csdev->dev, GFP_KERNEL, "%s_%s", "crash", name); 761 drvdata->crashdev.minor = MISC_DYNAMIC_MINOR; 762 drvdata->crashdev.fops = &tmc_crashdata_fops; 763 if (misc_register(&drvdata->crashdev)) { 764 dev_dbg(&drvdata->csdev->dev, 765 "Failed to setup user interface for crashdata\n"); 766 drvdata->crashdev.fops = NULL; 767 } else 768 dev_info(&drvdata->csdev->dev, 769 "Valid crash tracedata found\n"); 770 } 771 772 static int __tmc_probe(struct device *dev, struct resource *res) 773 { 774 int ret = 0; 775 u32 devid; 776 void __iomem *base; 777 struct coresight_platform_data *pdata = NULL; 778 struct tmc_drvdata *drvdata; 779 struct coresight_desc desc = { 0 }; 780 struct coresight_dev_list *dev_list = NULL; 781 782 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 783 if (!drvdata) 784 return -ENOMEM; 785 786 dev_set_drvdata(dev, drvdata); 787 788 ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); 789 if (ret) 790 return ret; 791 792 ret = -ENOMEM; 793 794 /* Validity for the resource is already checked by the AMBA core */ 795 base = devm_ioremap_resource(dev, res); 796 if (IS_ERR(base)) { 797 ret = PTR_ERR(base); 798 goto out; 799 } 800 801 drvdata->base = base; 802 desc.access = CSDEV_ACCESS_IOMEM(base); 803 804 raw_spin_lock_init(&drvdata->spinlock); 805 806 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); 807 drvdata->config_type = BMVAL(devid, 6, 7); 808 drvdata->memwidth = tmc_get_memwidth(devid); 809 /* This device is not associated with a session */ 810 drvdata->pid = -1; 811 drvdata->etr_mode = ETR_MODE_AUTO; 812 813 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { 814 drvdata->size = tmc_etr_get_default_buffer_size(dev); 815 drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev); 816 } else { 817 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; 818 } 819 820 tmc_get_reserved_region(dev); 821 822 desc.dev = dev; 823 824 switch (drvdata->config_type) { 825 case TMC_CONFIG_TYPE_ETB: 826 desc.groups = coresight_etf_groups; 827 desc.type = CORESIGHT_DEV_TYPE_SINK; 828 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 829 desc.ops = &tmc_etb_cs_ops; 830 dev_list = &etb_devs; 831 break; 832 case TMC_CONFIG_TYPE_ETR: 833 desc.groups = coresight_etr_groups; 834 desc.type = CORESIGHT_DEV_TYPE_SINK; 835 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; 836 desc.ops = &tmc_etr_cs_ops; 837 ret = tmc_etr_setup_caps(dev, devid, &desc.access); 838 if (ret) 839 goto out; 840 idr_init(&drvdata->idr); 841 mutex_init(&drvdata->idr_mutex); 842 dev_list = &etr_devs; 843 break; 844 case TMC_CONFIG_TYPE_ETF: 845 desc.groups = coresight_etf_groups; 846 desc.type = CORESIGHT_DEV_TYPE_LINKSINK; 847 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 848 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; 849 desc.ops = &tmc_etf_cs_ops; 850 dev_list = &etf_devs; 851 break; 852 default: 853 pr_err("%s: Unsupported TMC config\n", desc.name); 854 ret = -EINVAL; 855 goto out; 856 } 857 858 desc.name = coresight_alloc_device_name(dev_list, dev); 859 if (!desc.name) { 860 ret = -ENOMEM; 861 goto out; 862 } 863 864 pdata = coresight_get_platform_data(dev); 865 if (IS_ERR(pdata)) { 866 ret = PTR_ERR(pdata); 867 goto out; 868 } 869 dev->platform_data = pdata; 870 desc.pdata = pdata; 871 872 coresight_clear_self_claim_tag(&desc.access); 873 drvdata->csdev = coresight_register(&desc); 874 if (IS_ERR(drvdata->csdev)) { 875 ret = PTR_ERR(drvdata->csdev); 876 goto out; 877 } 878 879 drvdata->miscdev.name = desc.name; 880 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; 881 drvdata->miscdev.fops = &tmc_fops; 882 ret = misc_register(&drvdata->miscdev); 883 if (ret) { 884 coresight_unregister(drvdata->csdev); 885 goto out; 886 } 887 888 out: 889 if (is_tmc_crashdata_valid(drvdata) && 890 !tmc_prepare_crashdata(drvdata)) 891 register_crash_dev_interface(drvdata, desc.name); 892 return ret; 893 } 894 895 static int tmc_probe(struct amba_device *adev, const struct amba_id *id) 896 { 897 int ret; 898 899 ret = __tmc_probe(&adev->dev, &adev->res); 900 if (!ret) 901 pm_runtime_put(&adev->dev); 902 903 return ret; 904 } 905 906 static void tmc_shutdown(struct amba_device *adev) 907 { 908 unsigned long flags; 909 struct tmc_drvdata *drvdata = amba_get_drvdata(adev); 910 911 raw_spin_lock_irqsave(&drvdata->spinlock, flags); 912 913 if (coresight_get_mode(drvdata->csdev) == CS_MODE_DISABLED) 914 goto out; 915 916 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) 917 tmc_etr_disable_hw(drvdata); 918 919 /* 920 * We do not care about coresight unregister here unlike remove 921 * callback which is required for making coresight modular since 922 * the system is going down after this. 923 */ 924 out: 925 raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); 926 } 927 928 static void __tmc_remove(struct device *dev) 929 { 930 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 931 932 /* 933 * Since misc_open() holds a refcount on the f_ops, which is 934 * etb fops in this case, device is there until last file 935 * handler to this device is closed. 936 */ 937 misc_deregister(&drvdata->miscdev); 938 if (drvdata->crashdev.fops) 939 misc_deregister(&drvdata->crashdev); 940 coresight_unregister(drvdata->csdev); 941 } 942 943 static void tmc_remove(struct amba_device *adev) 944 { 945 __tmc_remove(&adev->dev); 946 } 947 948 static const struct amba_id tmc_ids[] = { 949 CS_AMBA_ID(0x000bb961), 950 /* Coresight SoC 600 TMC-ETR/ETS */ 951 CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS), 952 /* Coresight SoC 600 TMC-ETB */ 953 CS_AMBA_ID(0x000bb9e9), 954 /* Coresight SoC 600 TMC-ETF */ 955 CS_AMBA_ID(0x000bb9ea), 956 { 0, 0, NULL }, 957 }; 958 959 MODULE_DEVICE_TABLE(amba, tmc_ids); 960 961 static struct amba_driver tmc_driver = { 962 .drv = { 963 .name = "coresight-tmc", 964 .suppress_bind_attrs = true, 965 }, 966 .probe = tmc_probe, 967 .shutdown = tmc_shutdown, 968 .remove = tmc_remove, 969 .id_table = tmc_ids, 970 }; 971 972 static int tmc_platform_probe(struct platform_device *pdev) 973 { 974 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 975 int ret = 0; 976 977 pm_runtime_get_noresume(&pdev->dev); 978 pm_runtime_set_active(&pdev->dev); 979 pm_runtime_enable(&pdev->dev); 980 981 ret = __tmc_probe(&pdev->dev, res); 982 pm_runtime_put(&pdev->dev); 983 if (ret) 984 pm_runtime_disable(&pdev->dev); 985 986 return ret; 987 } 988 989 static void tmc_platform_remove(struct platform_device *pdev) 990 { 991 struct tmc_drvdata *drvdata = dev_get_drvdata(&pdev->dev); 992 993 if (WARN_ON(!drvdata)) 994 return; 995 996 __tmc_remove(&pdev->dev); 997 pm_runtime_disable(&pdev->dev); 998 } 999 1000 #ifdef CONFIG_PM 1001 static int tmc_runtime_suspend(struct device *dev) 1002 { 1003 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 1004 1005 clk_disable_unprepare(drvdata->atclk); 1006 clk_disable_unprepare(drvdata->pclk); 1007 1008 return 0; 1009 } 1010 1011 static int tmc_runtime_resume(struct device *dev) 1012 { 1013 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 1014 int ret; 1015 1016 ret = clk_prepare_enable(drvdata->pclk); 1017 if (ret) 1018 return ret; 1019 1020 ret = clk_prepare_enable(drvdata->atclk); 1021 if (ret) 1022 clk_disable_unprepare(drvdata->pclk); 1023 1024 return ret; 1025 } 1026 #endif 1027 1028 static const struct dev_pm_ops tmc_dev_pm_ops = { 1029 SET_RUNTIME_PM_OPS(tmc_runtime_suspend, tmc_runtime_resume, NULL) 1030 }; 1031 1032 #ifdef CONFIG_ACPI 1033 static const struct acpi_device_id tmc_acpi_ids[] = { 1034 {"ARMHC501", 0, 0, 0}, /* ARM CoreSight ETR */ 1035 {"ARMHC97C", 0, 0, 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */ 1036 {}, 1037 }; 1038 MODULE_DEVICE_TABLE(acpi, tmc_acpi_ids); 1039 #endif 1040 1041 static struct platform_driver tmc_platform_driver = { 1042 .probe = tmc_platform_probe, 1043 .remove = tmc_platform_remove, 1044 .driver = { 1045 .name = "coresight-tmc-platform", 1046 .acpi_match_table = ACPI_PTR(tmc_acpi_ids), 1047 .suppress_bind_attrs = true, 1048 .pm = &tmc_dev_pm_ops, 1049 }, 1050 }; 1051 1052 static int __init tmc_init(void) 1053 { 1054 return coresight_init_driver("tmc", &tmc_driver, &tmc_platform_driver, THIS_MODULE); 1055 } 1056 1057 static void __exit tmc_exit(void) 1058 { 1059 coresight_remove_driver(&tmc_driver, &tmc_platform_driver); 1060 } 1061 module_init(tmc_init); 1062 module_exit(tmc_exit); 1063 1064 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>"); 1065 MODULE_DESCRIPTION("Arm CoreSight Trace Memory Controller driver"); 1066 MODULE_LICENSE("GPL v2"); 1067