1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2012, The Linux Foundation. All rights reserved. 3 * 4 * Description: CoreSight Trace Memory Controller driver 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/types.h> 11 #include <linux/device.h> 12 #include <linux/idr.h> 13 #include <linux/io.h> 14 #include <linux/iommu.h> 15 #include <linux/err.h> 16 #include <linux/fs.h> 17 #include <linux/miscdevice.h> 18 #include <linux/mutex.h> 19 #include <linux/property.h> 20 #include <linux/uaccess.h> 21 #include <linux/slab.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/spinlock.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/of.h> 26 #include <linux/coresight.h> 27 #include <linux/amba/bus.h> 28 #include <linux/platform_device.h> 29 #include <linux/acpi.h> 30 31 #include "coresight-priv.h" 32 #include "coresight-tmc.h" 33 34 DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); 35 DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); 36 DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); 37 38 int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) 39 { 40 struct coresight_device *csdev = drvdata->csdev; 41 struct csdev_access *csa = &csdev->access; 42 43 /* Ensure formatter, unformatter and hardware fifo are empty */ 44 if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { 45 dev_err(&csdev->dev, 46 "timeout while waiting for TMC to be Ready\n"); 47 return -EBUSY; 48 } 49 return 0; 50 } 51 52 void tmc_flush_and_stop(struct tmc_drvdata *drvdata) 53 { 54 struct coresight_device *csdev = drvdata->csdev; 55 struct csdev_access *csa = &csdev->access; 56 u32 ffcr; 57 58 ffcr = readl_relaxed(drvdata->base + TMC_FFCR); 59 ffcr |= TMC_FFCR_STOP_ON_FLUSH; 60 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); 61 ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT); 62 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); 63 /* Ensure flush completes */ 64 if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { 65 dev_err(&csdev->dev, 66 "timeout while waiting for completion of Manual Flush\n"); 67 } 68 69 tmc_wait_for_tmcready(drvdata); 70 } 71 72 void tmc_enable_hw(struct tmc_drvdata *drvdata) 73 { 74 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL); 75 } 76 77 void tmc_disable_hw(struct tmc_drvdata *drvdata) 78 { 79 writel_relaxed(0x0, drvdata->base + TMC_CTL); 80 } 81 82 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata) 83 { 84 u32 mask = 0; 85 86 /* 87 * When moving RRP or an offset address forward, the new values must 88 * be byte-address aligned to the width of the trace memory databus 89 * _and_ to a frame boundary (16 byte), whichever is the biggest. For 90 * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four 91 * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must 92 * be 0s. 93 */ 94 switch (drvdata->memwidth) { 95 case TMC_MEM_INTF_WIDTH_32BITS: 96 case TMC_MEM_INTF_WIDTH_64BITS: 97 case TMC_MEM_INTF_WIDTH_128BITS: 98 mask = GENMASK(31, 4); 99 break; 100 case TMC_MEM_INTF_WIDTH_256BITS: 101 mask = GENMASK(31, 5); 102 break; 103 } 104 105 return mask; 106 } 107 108 static int tmc_read_prepare(struct tmc_drvdata *drvdata) 109 { 110 int ret = 0; 111 112 switch (drvdata->config_type) { 113 case TMC_CONFIG_TYPE_ETB: 114 case TMC_CONFIG_TYPE_ETF: 115 ret = tmc_read_prepare_etb(drvdata); 116 break; 117 case TMC_CONFIG_TYPE_ETR: 118 ret = tmc_read_prepare_etr(drvdata); 119 break; 120 default: 121 ret = -EINVAL; 122 } 123 124 if (!ret) 125 dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); 126 127 return ret; 128 } 129 130 static int tmc_read_unprepare(struct tmc_drvdata *drvdata) 131 { 132 int ret = 0; 133 134 switch (drvdata->config_type) { 135 case TMC_CONFIG_TYPE_ETB: 136 case TMC_CONFIG_TYPE_ETF: 137 ret = tmc_read_unprepare_etb(drvdata); 138 break; 139 case TMC_CONFIG_TYPE_ETR: 140 ret = tmc_read_unprepare_etr(drvdata); 141 break; 142 default: 143 ret = -EINVAL; 144 } 145 146 if (!ret) 147 dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); 148 149 return ret; 150 } 151 152 static int tmc_open(struct inode *inode, struct file *file) 153 { 154 int ret; 155 struct tmc_drvdata *drvdata = container_of(file->private_data, 156 struct tmc_drvdata, miscdev); 157 158 ret = tmc_read_prepare(drvdata); 159 if (ret) 160 return ret; 161 162 nonseekable_open(inode, file); 163 164 dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__); 165 return 0; 166 } 167 168 static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, 169 loff_t pos, size_t len, char **bufpp) 170 { 171 switch (drvdata->config_type) { 172 case TMC_CONFIG_TYPE_ETB: 173 case TMC_CONFIG_TYPE_ETF: 174 return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); 175 case TMC_CONFIG_TYPE_ETR: 176 return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); 177 } 178 179 return -EINVAL; 180 } 181 182 static ssize_t tmc_read(struct file *file, char __user *data, size_t len, 183 loff_t *ppos) 184 { 185 char *bufp; 186 ssize_t actual; 187 struct tmc_drvdata *drvdata = container_of(file->private_data, 188 struct tmc_drvdata, miscdev); 189 actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp); 190 if (actual <= 0) 191 return 0; 192 193 if (copy_to_user(data, bufp, actual)) { 194 dev_dbg(&drvdata->csdev->dev, 195 "%s: copy_to_user failed\n", __func__); 196 return -EFAULT; 197 } 198 199 *ppos += actual; 200 dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); 201 202 return actual; 203 } 204 205 static int tmc_release(struct inode *inode, struct file *file) 206 { 207 int ret; 208 struct tmc_drvdata *drvdata = container_of(file->private_data, 209 struct tmc_drvdata, miscdev); 210 211 ret = tmc_read_unprepare(drvdata); 212 if (ret) 213 return ret; 214 215 dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__); 216 return 0; 217 } 218 219 static const struct file_operations tmc_fops = { 220 .owner = THIS_MODULE, 221 .open = tmc_open, 222 .read = tmc_read, 223 .release = tmc_release, 224 .llseek = no_llseek, 225 }; 226 227 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid) 228 { 229 enum tmc_mem_intf_width memwidth; 230 231 /* 232 * Excerpt from the TRM: 233 * 234 * DEVID::MEMWIDTH[10:8] 235 * 0x2 Memory interface databus is 32 bits wide. 236 * 0x3 Memory interface databus is 64 bits wide. 237 * 0x4 Memory interface databus is 128 bits wide. 238 * 0x5 Memory interface databus is 256 bits wide. 239 */ 240 switch (BMVAL(devid, 8, 10)) { 241 case 0x2: 242 memwidth = TMC_MEM_INTF_WIDTH_32BITS; 243 break; 244 case 0x3: 245 memwidth = TMC_MEM_INTF_WIDTH_64BITS; 246 break; 247 case 0x4: 248 memwidth = TMC_MEM_INTF_WIDTH_128BITS; 249 break; 250 case 0x5: 251 memwidth = TMC_MEM_INTF_WIDTH_256BITS; 252 break; 253 default: 254 memwidth = 0; 255 } 256 257 return memwidth; 258 } 259 260 static struct attribute *coresight_tmc_mgmt_attrs[] = { 261 coresight_simple_reg32(rsz, TMC_RSZ), 262 coresight_simple_reg32(sts, TMC_STS), 263 coresight_simple_reg64(rrp, TMC_RRP, TMC_RRPHI), 264 coresight_simple_reg64(rwp, TMC_RWP, TMC_RWPHI), 265 coresight_simple_reg32(trg, TMC_TRG), 266 coresight_simple_reg32(ctl, TMC_CTL), 267 coresight_simple_reg32(ffsr, TMC_FFSR), 268 coresight_simple_reg32(ffcr, TMC_FFCR), 269 coresight_simple_reg32(mode, TMC_MODE), 270 coresight_simple_reg32(pscr, TMC_PSCR), 271 coresight_simple_reg32(devid, CORESIGHT_DEVID), 272 coresight_simple_reg64(dba, TMC_DBALO, TMC_DBAHI), 273 coresight_simple_reg32(axictl, TMC_AXICTL), 274 coresight_simple_reg32(authstatus, TMC_AUTHSTATUS), 275 NULL, 276 }; 277 278 static ssize_t trigger_cntr_show(struct device *dev, 279 struct device_attribute *attr, char *buf) 280 { 281 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 282 unsigned long val = drvdata->trigger_cntr; 283 284 return sprintf(buf, "%#lx\n", val); 285 } 286 287 static ssize_t trigger_cntr_store(struct device *dev, 288 struct device_attribute *attr, 289 const char *buf, size_t size) 290 { 291 int ret; 292 unsigned long val; 293 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 294 295 ret = kstrtoul(buf, 16, &val); 296 if (ret) 297 return ret; 298 299 drvdata->trigger_cntr = val; 300 return size; 301 } 302 static DEVICE_ATTR_RW(trigger_cntr); 303 304 static ssize_t buffer_size_show(struct device *dev, 305 struct device_attribute *attr, char *buf) 306 { 307 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 308 309 return sprintf(buf, "%#x\n", drvdata->size); 310 } 311 312 static ssize_t buffer_size_store(struct device *dev, 313 struct device_attribute *attr, 314 const char *buf, size_t size) 315 { 316 int ret; 317 unsigned long val; 318 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); 319 320 /* Only permitted for TMC-ETRs */ 321 if (drvdata->config_type != TMC_CONFIG_TYPE_ETR) 322 return -EPERM; 323 324 ret = kstrtoul(buf, 0, &val); 325 if (ret) 326 return ret; 327 /* The buffer size should be page aligned */ 328 if (val & (PAGE_SIZE - 1)) 329 return -EINVAL; 330 drvdata->size = val; 331 return size; 332 } 333 334 static DEVICE_ATTR_RW(buffer_size); 335 336 static struct attribute *coresight_tmc_attrs[] = { 337 &dev_attr_trigger_cntr.attr, 338 &dev_attr_buffer_size.attr, 339 NULL, 340 }; 341 342 static const struct attribute_group coresight_tmc_group = { 343 .attrs = coresight_tmc_attrs, 344 }; 345 346 static const struct attribute_group coresight_tmc_mgmt_group = { 347 .attrs = coresight_tmc_mgmt_attrs, 348 .name = "mgmt", 349 }; 350 351 static const struct attribute_group *coresight_etf_groups[] = { 352 &coresight_tmc_group, 353 &coresight_tmc_mgmt_group, 354 NULL, 355 }; 356 357 static const struct attribute_group *coresight_etr_groups[] = { 358 &coresight_etr_group, 359 &coresight_tmc_group, 360 &coresight_tmc_mgmt_group, 361 NULL, 362 }; 363 364 static inline bool tmc_etr_can_use_sg(struct device *dev) 365 { 366 int ret; 367 u8 val_u8; 368 369 /* 370 * Presence of the property 'arm,scatter-gather' is checked 371 * on the platform for the feature support, rather than its 372 * value. 373 */ 374 if (is_of_node(dev->fwnode)) { 375 return fwnode_property_present(dev->fwnode, "arm,scatter-gather"); 376 } else if (is_acpi_device_node(dev->fwnode)) { 377 /* 378 * TMC_DEVID_NOSCAT test in tmc_etr_setup_caps(), has already ensured 379 * this property is only checked for Coresight SoC 400 TMC configured 380 * as ETR. 381 */ 382 ret = fwnode_property_read_u8(dev->fwnode, "arm-armhc97c-sg-enable", &val_u8); 383 if (!ret) 384 return !!val_u8; 385 386 if (fwnode_property_present(dev->fwnode, "arm,scatter-gather")) { 387 pr_warn_once("Deprecated ACPI property - arm,scatter-gather\n"); 388 return true; 389 } 390 } 391 return false; 392 } 393 394 static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata) 395 { 396 u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS); 397 398 return (auth & TMC_AUTH_NSID_MASK) == 0x3; 399 } 400 401 static const struct amba_id tmc_ids[]; 402 403 /* Detect and initialise the capabilities of a TMC ETR */ 404 static int tmc_etr_setup_caps(struct device *parent, u32 devid, 405 struct csdev_access *access) 406 { 407 int rc; 408 u32 tmc_pid, dma_mask = 0; 409 struct tmc_drvdata *drvdata = dev_get_drvdata(parent); 410 void *dev_caps; 411 412 if (!tmc_etr_has_non_secure_access(drvdata)) 413 return -EACCES; 414 415 tmc_pid = coresight_get_pid(access); 416 dev_caps = coresight_get_uci_data_from_amba(tmc_ids, tmc_pid); 417 418 /* Set the unadvertised capabilities */ 419 tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps); 420 421 if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(parent)) 422 tmc_etr_set_cap(drvdata, TMC_ETR_SG); 423 424 /* Check if the AXI address width is available */ 425 if (devid & TMC_DEVID_AXIAW_VALID) 426 dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) & 427 TMC_DEVID_AXIAW_MASK); 428 429 /* 430 * Unless specified in the device configuration, ETR uses a 40-bit 431 * AXI master in place of the embedded SRAM of ETB/ETF. 432 */ 433 switch (dma_mask) { 434 case 32: 435 case 40: 436 case 44: 437 case 48: 438 case 52: 439 dev_info(parent, "Detected dma mask %dbits\n", dma_mask); 440 break; 441 default: 442 dma_mask = 40; 443 } 444 445 rc = dma_set_mask_and_coherent(parent, DMA_BIT_MASK(dma_mask)); 446 if (rc) 447 dev_err(parent, "Failed to setup DMA mask: %d\n", rc); 448 return rc; 449 } 450 451 static u32 tmc_etr_get_default_buffer_size(struct device *dev) 452 { 453 u32 size; 454 455 if (fwnode_property_read_u32(dev->fwnode, "arm,buffer-size", &size)) 456 size = SZ_1M; 457 return size; 458 } 459 460 static u32 tmc_etr_get_max_burst_size(struct device *dev) 461 { 462 u32 burst_size; 463 464 if (fwnode_property_read_u32(dev->fwnode, "arm,max-burst-size", 465 &burst_size)) 466 return TMC_AXICTL_WR_BURST_16; 467 468 /* Only permissible values are 0 to 15 */ 469 if (burst_size > 0xF) 470 burst_size = TMC_AXICTL_WR_BURST_16; 471 472 return burst_size; 473 } 474 475 static int __tmc_probe(struct device *dev, struct resource *res) 476 { 477 int ret = 0; 478 u32 devid; 479 void __iomem *base; 480 struct coresight_platform_data *pdata = NULL; 481 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 482 struct coresight_desc desc = { 0 }; 483 struct coresight_dev_list *dev_list = NULL; 484 485 ret = -ENOMEM; 486 487 /* Validity for the resource is already checked by the AMBA core */ 488 base = devm_ioremap_resource(dev, res); 489 if (IS_ERR(base)) { 490 ret = PTR_ERR(base); 491 goto out; 492 } 493 494 drvdata->base = base; 495 desc.access = CSDEV_ACCESS_IOMEM(base); 496 497 spin_lock_init(&drvdata->spinlock); 498 499 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); 500 drvdata->config_type = BMVAL(devid, 6, 7); 501 drvdata->memwidth = tmc_get_memwidth(devid); 502 /* This device is not associated with a session */ 503 drvdata->pid = -1; 504 drvdata->etr_mode = ETR_MODE_AUTO; 505 506 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { 507 drvdata->size = tmc_etr_get_default_buffer_size(dev); 508 drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev); 509 } else { 510 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; 511 } 512 513 desc.dev = dev; 514 515 switch (drvdata->config_type) { 516 case TMC_CONFIG_TYPE_ETB: 517 desc.groups = coresight_etf_groups; 518 desc.type = CORESIGHT_DEV_TYPE_SINK; 519 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 520 desc.ops = &tmc_etb_cs_ops; 521 dev_list = &etb_devs; 522 break; 523 case TMC_CONFIG_TYPE_ETR: 524 desc.groups = coresight_etr_groups; 525 desc.type = CORESIGHT_DEV_TYPE_SINK; 526 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; 527 desc.ops = &tmc_etr_cs_ops; 528 ret = tmc_etr_setup_caps(dev, devid, &desc.access); 529 if (ret) 530 goto out; 531 idr_init(&drvdata->idr); 532 mutex_init(&drvdata->idr_mutex); 533 dev_list = &etr_devs; 534 break; 535 case TMC_CONFIG_TYPE_ETF: 536 desc.groups = coresight_etf_groups; 537 desc.type = CORESIGHT_DEV_TYPE_LINKSINK; 538 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 539 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; 540 desc.ops = &tmc_etf_cs_ops; 541 dev_list = &etf_devs; 542 break; 543 default: 544 pr_err("%s: Unsupported TMC config\n", desc.name); 545 ret = -EINVAL; 546 goto out; 547 } 548 549 desc.name = coresight_alloc_device_name(dev_list, dev); 550 if (!desc.name) { 551 ret = -ENOMEM; 552 goto out; 553 } 554 555 pdata = coresight_get_platform_data(dev); 556 if (IS_ERR(pdata)) { 557 ret = PTR_ERR(pdata); 558 goto out; 559 } 560 dev->platform_data = pdata; 561 desc.pdata = pdata; 562 563 drvdata->csdev = coresight_register(&desc); 564 if (IS_ERR(drvdata->csdev)) { 565 ret = PTR_ERR(drvdata->csdev); 566 goto out; 567 } 568 569 drvdata->miscdev.name = desc.name; 570 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; 571 drvdata->miscdev.fops = &tmc_fops; 572 ret = misc_register(&drvdata->miscdev); 573 if (ret) 574 coresight_unregister(drvdata->csdev); 575 out: 576 return ret; 577 } 578 579 static int tmc_probe(struct amba_device *adev, const struct amba_id *id) 580 { 581 struct tmc_drvdata *drvdata; 582 int ret; 583 584 drvdata = devm_kzalloc(&adev->dev, sizeof(*drvdata), GFP_KERNEL); 585 if (!drvdata) 586 return -ENOMEM; 587 588 amba_set_drvdata(adev, drvdata); 589 ret = __tmc_probe(&adev->dev, &adev->res); 590 if (!ret) 591 pm_runtime_put(&adev->dev); 592 593 return ret; 594 } 595 596 static void tmc_shutdown(struct amba_device *adev) 597 { 598 unsigned long flags; 599 struct tmc_drvdata *drvdata = amba_get_drvdata(adev); 600 601 spin_lock_irqsave(&drvdata->spinlock, flags); 602 603 if (coresight_get_mode(drvdata->csdev) == CS_MODE_DISABLED) 604 goto out; 605 606 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) 607 tmc_etr_disable_hw(drvdata); 608 609 /* 610 * We do not care about coresight unregister here unlike remove 611 * callback which is required for making coresight modular since 612 * the system is going down after this. 613 */ 614 out: 615 spin_unlock_irqrestore(&drvdata->spinlock, flags); 616 } 617 618 static void __tmc_remove(struct device *dev) 619 { 620 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 621 622 /* 623 * Since misc_open() holds a refcount on the f_ops, which is 624 * etb fops in this case, device is there until last file 625 * handler to this device is closed. 626 */ 627 misc_deregister(&drvdata->miscdev); 628 coresight_unregister(drvdata->csdev); 629 } 630 631 static void tmc_remove(struct amba_device *adev) 632 { 633 __tmc_remove(&adev->dev); 634 } 635 636 static const struct amba_id tmc_ids[] = { 637 CS_AMBA_ID(0x000bb961), 638 /* Coresight SoC 600 TMC-ETR/ETS */ 639 CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS), 640 /* Coresight SoC 600 TMC-ETB */ 641 CS_AMBA_ID(0x000bb9e9), 642 /* Coresight SoC 600 TMC-ETF */ 643 CS_AMBA_ID(0x000bb9ea), 644 { 0, 0, NULL }, 645 }; 646 647 MODULE_DEVICE_TABLE(amba, tmc_ids); 648 649 static struct amba_driver tmc_driver = { 650 .drv = { 651 .name = "coresight-tmc", 652 .suppress_bind_attrs = true, 653 }, 654 .probe = tmc_probe, 655 .shutdown = tmc_shutdown, 656 .remove = tmc_remove, 657 .id_table = tmc_ids, 658 }; 659 660 static int tmc_platform_probe(struct platform_device *pdev) 661 { 662 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 663 struct tmc_drvdata *drvdata; 664 int ret = 0; 665 666 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); 667 if (!drvdata) 668 return -ENOMEM; 669 670 drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev); 671 if (IS_ERR(drvdata->pclk)) 672 return -ENODEV; 673 674 dev_set_drvdata(&pdev->dev, drvdata); 675 pm_runtime_get_noresume(&pdev->dev); 676 pm_runtime_set_active(&pdev->dev); 677 pm_runtime_enable(&pdev->dev); 678 679 ret = __tmc_probe(&pdev->dev, res); 680 pm_runtime_put(&pdev->dev); 681 if (ret) 682 pm_runtime_disable(&pdev->dev); 683 684 return ret; 685 } 686 687 static void tmc_platform_remove(struct platform_device *pdev) 688 { 689 struct tmc_drvdata *drvdata = dev_get_drvdata(&pdev->dev); 690 691 if (WARN_ON(!drvdata)) 692 return; 693 694 __tmc_remove(&pdev->dev); 695 pm_runtime_disable(&pdev->dev); 696 if (!IS_ERR_OR_NULL(drvdata->pclk)) 697 clk_put(drvdata->pclk); 698 } 699 700 #ifdef CONFIG_PM 701 static int tmc_runtime_suspend(struct device *dev) 702 { 703 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 704 705 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) 706 clk_disable_unprepare(drvdata->pclk); 707 return 0; 708 } 709 710 static int tmc_runtime_resume(struct device *dev) 711 { 712 struct tmc_drvdata *drvdata = dev_get_drvdata(dev); 713 714 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) 715 clk_prepare_enable(drvdata->pclk); 716 return 0; 717 } 718 #endif 719 720 static const struct dev_pm_ops tmc_dev_pm_ops = { 721 SET_RUNTIME_PM_OPS(tmc_runtime_suspend, tmc_runtime_resume, NULL) 722 }; 723 724 #ifdef CONFIG_ACPI 725 static const struct acpi_device_id tmc_acpi_ids[] = { 726 {"ARMHC501", 0, 0, 0}, /* ARM CoreSight ETR */ 727 {"ARMHC97C", 0, 0, 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */ 728 {}, 729 }; 730 MODULE_DEVICE_TABLE(acpi, tmc_acpi_ids); 731 #endif 732 733 static struct platform_driver tmc_platform_driver = { 734 .probe = tmc_platform_probe, 735 .remove_new = tmc_platform_remove, 736 .driver = { 737 .name = "coresight-tmc-platform", 738 .acpi_match_table = ACPI_PTR(tmc_acpi_ids), 739 .suppress_bind_attrs = true, 740 .pm = &tmc_dev_pm_ops, 741 }, 742 }; 743 744 static int __init tmc_init(void) 745 { 746 return coresight_init_driver("tmc", &tmc_driver, &tmc_platform_driver); 747 } 748 749 static void __exit tmc_exit(void) 750 { 751 coresight_remove_driver(&tmc_driver, &tmc_platform_driver); 752 } 753 module_init(tmc_init); 754 module_exit(tmc_exit); 755 756 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>"); 757 MODULE_DESCRIPTION("Arm CoreSight Trace Memory Controller driver"); 758 MODULE_LICENSE("GPL v2"); 759