1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _CORESIGHT_PRIV_H 7 #define _CORESIGHT_PRIV_H 8 9 #include <linux/bitops.h> 10 #include <linux/io.h> 11 #include <linux/coresight.h> 12 #include <linux/pm_runtime.h> 13 14 /* 15 * Coresight management registers (0xf00-0xfcc) 16 * 0xfa0 - 0xfa4: Management registers in PFTv1.0 17 * Trace registers in PFTv1.1 18 */ 19 #define CORESIGHT_ITCTRL 0xf00 20 #define CORESIGHT_CLAIMSET 0xfa0 21 #define CORESIGHT_CLAIMCLR 0xfa4 22 #define CORESIGHT_LAR 0xfb0 23 #define CORESIGHT_LSR 0xfb4 24 #define CORESIGHT_AUTHSTATUS 0xfb8 25 #define CORESIGHT_DEVID 0xfc8 26 #define CORESIGHT_DEVTYPE 0xfcc 27 28 #define TIMEOUT_US 100 29 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) 30 31 #define ETM_MODE_EXCL_KERN BIT(30) 32 #define ETM_MODE_EXCL_USER BIT(31) 33 34 typedef u32 (*coresight_read_fn)(const struct device *, u32 offset); 35 #define __coresight_simple_func(type, func, name, lo_off, hi_off) \ 36 static ssize_t name##_show(struct device *_dev, \ 37 struct device_attribute *attr, char *buf) \ 38 { \ 39 type *drvdata = dev_get_drvdata(_dev->parent); \ 40 coresight_read_fn fn = func; \ 41 u64 val; \ 42 pm_runtime_get_sync(_dev->parent); \ 43 if (fn) \ 44 val = (u64)fn(_dev->parent, lo_off); \ 45 else \ 46 val = coresight_read_reg_pair(drvdata->base, \ 47 lo_off, hi_off); \ 48 pm_runtime_put_sync(_dev->parent); \ 49 return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val); \ 50 } \ 51 static DEVICE_ATTR_RO(name) 52 53 #define coresight_simple_func(type, func, name, offset) \ 54 __coresight_simple_func(type, func, name, offset, -1) 55 #define coresight_simple_reg32(type, name, offset) \ 56 __coresight_simple_func(type, NULL, name, offset, -1) 57 #define coresight_simple_reg64(type, name, lo_off, hi_off) \ 58 __coresight_simple_func(type, NULL, name, lo_off, hi_off) 59 60 extern const u32 barrier_pkt[4]; 61 #define CORESIGHT_BARRIER_PKT_SIZE (sizeof(barrier_pkt)) 62 63 enum etm_addr_type { 64 ETM_ADDR_TYPE_NONE, 65 ETM_ADDR_TYPE_SINGLE, 66 ETM_ADDR_TYPE_RANGE, 67 ETM_ADDR_TYPE_START, 68 ETM_ADDR_TYPE_STOP, 69 }; 70 71 enum cs_mode { 72 CS_MODE_DISABLED, 73 CS_MODE_SYSFS, 74 CS_MODE_PERF, 75 }; 76 77 /** 78 * struct cs_buffer - keep track of a recording session' specifics 79 * @cur: index of the current buffer 80 * @nr_pages: max number of pages granted to us 81 * @offset: offset within the current buffer 82 * @data_size: how much we collected in this run 83 * @snapshot: is this run in snapshot mode 84 * @data_pages: a handle the ring buffer 85 */ 86 struct cs_buffers { 87 unsigned int cur; 88 unsigned int nr_pages; 89 unsigned long offset; 90 local_t data_size; 91 bool snapshot; 92 void **data_pages; 93 }; 94 95 static inline void coresight_insert_barrier_packet(void *buf) 96 { 97 if (buf) 98 memcpy(buf, barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE); 99 } 100 101 102 static inline void CS_LOCK(void __iomem *addr) 103 { 104 do { 105 /* Wait for things to settle */ 106 mb(); 107 writel_relaxed(0x0, addr + CORESIGHT_LAR); 108 } while (0); 109 } 110 111 static inline void CS_UNLOCK(void __iomem *addr) 112 { 113 do { 114 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR); 115 /* Make sure everyone has seen this */ 116 mb(); 117 } while (0); 118 } 119 120 static inline u64 121 coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset) 122 { 123 u64 val; 124 125 val = readl_relaxed(addr + lo_offset); 126 val |= (hi_offset < 0) ? 0 : 127 (u64)readl_relaxed(addr + hi_offset) << 32; 128 return val; 129 } 130 131 static inline void coresight_write_reg_pair(void __iomem *addr, u64 val, 132 s32 lo_offset, s32 hi_offset) 133 { 134 writel_relaxed((u32)val, addr + lo_offset); 135 if (hi_offset >= 0) 136 writel_relaxed((u32)(val >> 32), addr + hi_offset); 137 } 138 139 void coresight_disable_path(struct list_head *path); 140 int coresight_enable_path(struct list_head *path, u32 mode); 141 struct coresight_device *coresight_get_sink(struct list_head *path); 142 struct coresight_device *coresight_get_enabled_sink(bool reset); 143 struct list_head *coresight_build_path(struct coresight_device *csdev, 144 struct coresight_device *sink); 145 void coresight_release_path(struct list_head *path); 146 147 #ifdef CONFIG_CORESIGHT_SOURCE_ETM3X 148 extern int etm_readl_cp14(u32 off, unsigned int *val); 149 extern int etm_writel_cp14(u32 off, u32 val); 150 #else 151 static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } 152 static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } 153 #endif 154 155 #endif 156