1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _CORESIGHT_CORESIGHT_ETM_H 14 #define _CORESIGHT_CORESIGHT_ETM_H 15 16 #include <linux/spinlock.h> 17 #include "coresight-priv.h" 18 19 /* 20 * Device registers: 21 * 0x000 - 0x2FC: Trace registers 22 * 0x300 - 0x314: Management registers 23 * 0x318 - 0xEFC: Trace registers 24 * 0xF00: Management registers 25 * 0xFA0 - 0xFA4: Trace registers 26 * 0xFA8 - 0xFFC: Management registers 27 */ 28 /* Trace registers (0x000-0x2FC) */ 29 /* Main control and configuration registers */ 30 #define TRCPRGCTLR 0x004 31 #define TRCPROCSELR 0x008 32 #define TRCSTATR 0x00C 33 #define TRCCONFIGR 0x010 34 #define TRCAUXCTLR 0x018 35 #define TRCEVENTCTL0R 0x020 36 #define TRCEVENTCTL1R 0x024 37 #define TRCSTALLCTLR 0x02C 38 #define TRCTSCTLR 0x030 39 #define TRCSYNCPR 0x034 40 #define TRCCCCTLR 0x038 41 #define TRCBBCTLR 0x03C 42 #define TRCTRACEIDR 0x040 43 #define TRCQCTLR 0x044 44 /* Filtering control registers */ 45 #define TRCVICTLR 0x080 46 #define TRCVIIECTLR 0x084 47 #define TRCVISSCTLR 0x088 48 #define TRCVIPCSSCTLR 0x08C 49 #define TRCVDCTLR 0x0A0 50 #define TRCVDSACCTLR 0x0A4 51 #define TRCVDARCCTLR 0x0A8 52 /* Derived resources registers */ 53 #define TRCSEQEVRn(n) (0x100 + (n * 4)) 54 #define TRCSEQRSTEVR 0x118 55 #define TRCSEQSTR 0x11C 56 #define TRCEXTINSELR 0x120 57 #define TRCCNTRLDVRn(n) (0x140 + (n * 4)) 58 #define TRCCNTCTLRn(n) (0x150 + (n * 4)) 59 #define TRCCNTVRn(n) (0x160 + (n * 4)) 60 /* ID registers */ 61 #define TRCIDR8 0x180 62 #define TRCIDR9 0x184 63 #define TRCIDR10 0x188 64 #define TRCIDR11 0x18C 65 #define TRCIDR12 0x190 66 #define TRCIDR13 0x194 67 #define TRCIMSPEC0 0x1C0 68 #define TRCIMSPECn(n) (0x1C0 + (n * 4)) 69 #define TRCIDR0 0x1E0 70 #define TRCIDR1 0x1E4 71 #define TRCIDR2 0x1E8 72 #define TRCIDR3 0x1EC 73 #define TRCIDR4 0x1F0 74 #define TRCIDR5 0x1F4 75 #define TRCIDR6 0x1F8 76 #define TRCIDR7 0x1FC 77 /* Resource selection registers */ 78 #define TRCRSCTLRn(n) (0x200 + (n * 4)) 79 /* Single-shot comparator registers */ 80 #define TRCSSCCRn(n) (0x280 + (n * 4)) 81 #define TRCSSCSRn(n) (0x2A0 + (n * 4)) 82 #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) 83 /* Management registers (0x300-0x314) */ 84 #define TRCOSLAR 0x300 85 #define TRCOSLSR 0x304 86 #define TRCPDCR 0x310 87 #define TRCPDSR 0x314 88 /* Trace registers (0x318-0xEFC) */ 89 /* Comparator registers */ 90 #define TRCACVRn(n) (0x400 + (n * 8)) 91 #define TRCACATRn(n) (0x480 + (n * 8)) 92 #define TRCDVCVRn(n) (0x500 + (n * 16)) 93 #define TRCDVCMRn(n) (0x580 + (n * 16)) 94 #define TRCCIDCVRn(n) (0x600 + (n * 8)) 95 #define TRCVMIDCVRn(n) (0x640 + (n * 8)) 96 #define TRCCIDCCTLR0 0x680 97 #define TRCCIDCCTLR1 0x684 98 #define TRCVMIDCCTLR0 0x688 99 #define TRCVMIDCCTLR1 0x68C 100 /* Management register (0xF00) */ 101 /* Integration control registers */ 102 #define TRCITCTRL 0xF00 103 /* Trace registers (0xFA0-0xFA4) */ 104 /* Claim tag registers */ 105 #define TRCCLAIMSET 0xFA0 106 #define TRCCLAIMCLR 0xFA4 107 /* Management registers (0xFA8-0xFFC) */ 108 #define TRCDEVAFF0 0xFA8 109 #define TRCDEVAFF1 0xFAC 110 #define TRCLAR 0xFB0 111 #define TRCLSR 0xFB4 112 #define TRCAUTHSTATUS 0xFB8 113 #define TRCDEVARCH 0xFBC 114 #define TRCDEVID 0xFC8 115 #define TRCDEVTYPE 0xFCC 116 #define TRCPIDR4 0xFD0 117 #define TRCPIDR5 0xFD4 118 #define TRCPIDR6 0xFD8 119 #define TRCPIDR7 0xFDC 120 #define TRCPIDR0 0xFE0 121 #define TRCPIDR1 0xFE4 122 #define TRCPIDR2 0xFE8 123 #define TRCPIDR3 0xFEC 124 #define TRCCIDR0 0xFF0 125 #define TRCCIDR1 0xFF4 126 #define TRCCIDR2 0xFF8 127 #define TRCCIDR3 0xFFC 128 129 /* ETMv4 resources */ 130 #define ETM_MAX_NR_PE 8 131 #define ETMv4_MAX_CNTR 4 132 #define ETM_MAX_SEQ_STATES 4 133 #define ETM_MAX_EXT_INP_SEL 4 134 #define ETM_MAX_EXT_INP 256 135 #define ETM_MAX_EXT_OUT 4 136 #define ETM_MAX_SINGLE_ADDR_CMP 16 137 #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2) 138 #define ETM_MAX_DATA_VAL_CMP 8 139 #define ETMv4_MAX_CTXID_CMP 8 140 #define ETM_MAX_VMID_CMP 8 141 #define ETM_MAX_PE_CMP 8 142 #define ETM_MAX_RES_SEL 16 143 #define ETM_MAX_SS_CMP 8 144 145 #define ETM_ARCH_V4 0x40 146 #define ETMv4_SYNC_MASK 0x1F 147 #define ETM_CYC_THRESHOLD_MASK 0xFFF 148 #define ETMv4_EVENT_MASK 0xFF 149 #define ETM_CNTR_MAX_VAL 0xFFFF 150 #define ETM_TRACEID_MASK 0x3f 151 152 /* ETMv4 programming modes */ 153 #define ETM_MODE_EXCLUDE BIT(0) 154 #define ETM_MODE_LOAD BIT(1) 155 #define ETM_MODE_STORE BIT(2) 156 #define ETM_MODE_LOAD_STORE BIT(3) 157 #define ETM_MODE_BB BIT(4) 158 #define ETMv4_MODE_CYCACC BIT(5) 159 #define ETMv4_MODE_CTXID BIT(6) 160 #define ETM_MODE_VMID BIT(7) 161 #define ETM_MODE_COND(val) BMVAL(val, 8, 10) 162 #define ETMv4_MODE_TIMESTAMP BIT(11) 163 #define ETM_MODE_RETURNSTACK BIT(12) 164 #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14) 165 #define ETM_MODE_DATA_TRACE_ADDR BIT(15) 166 #define ETM_MODE_DATA_TRACE_VAL BIT(16) 167 #define ETM_MODE_ISTALL BIT(17) 168 #define ETM_MODE_DSTALL BIT(18) 169 #define ETM_MODE_ATB_TRIGGER BIT(19) 170 #define ETM_MODE_LPOVERRIDE BIT(20) 171 #define ETM_MODE_ISTALL_EN BIT(21) 172 #define ETM_MODE_DSTALL_EN BIT(22) 173 #define ETM_MODE_INSTPRIO BIT(23) 174 #define ETM_MODE_NOOVERFLOW BIT(24) 175 #define ETM_MODE_TRACE_RESET BIT(25) 176 #define ETM_MODE_TRACE_ERR BIT(26) 177 #define ETM_MODE_VIEWINST_STARTSTOP BIT(27) 178 #define ETMv4_MODE_ALL 0xFFFFFFF 179 180 #define TRCSTATR_IDLE_BIT 0 181 182 /** 183 * struct etm4_drvdata - specifics associated to an ETM component 184 * @base: Memory mapped base address for this component. 185 * @dev: The device entity associated to this component. 186 * @csdev: Component vitals needed by the framework. 187 * @spinlock: Only one at a time pls. 188 * @cpu: The cpu this component is affined to. 189 * @arch: ETM version number. 190 * @enable: Is this ETM currently tracing. 191 * @sticky_enable: true if ETM base configuration has been done. 192 * @boot_enable:True if we should start tracing at boot time. 193 * @os_unlock: True if access to management registers is allowed. 194 * @nr_pe: The number of processing entity available for tracing. 195 * @nr_pe_cmp: The number of processing entity comparator inputs that are 196 * available for tracing. 197 * @nr_addr_cmp:Number of pairs of address comparators available 198 * as found in ETMIDR4 0-3. 199 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. 200 * @nr_ext_inp: Number of external input. 201 * @numcidc: Number of contextID comparators. 202 * @numvmidc: Number of VMID comparators. 203 * @nrseqstate: The number of sequencer states that are implemented. 204 * @nr_event: Indicates how many events the trace unit support. 205 * @nr_resource:The number of resource selection pairs available for tracing. 206 * @nr_ss_cmp: Number of single-shot comparator controls that are available. 207 * @mode: Controls various modes supported by this ETM. 208 * @trcid: value of the current ID for this component. 209 * @trcid_size: Indicates the trace ID width. 210 * @instrp0: Tracing of load and store instructions 211 * as P0 elements is supported. 212 * @trccond: If the trace unit supports conditional 213 * instruction tracing. 214 * @retstack: Indicates if the implementation supports a return stack. 215 * @trc_error: Whether a trace unit can trace a system 216 * error exception. 217 * @atbtrig: If the implementation can support ATB triggers 218 * @lpoverride: If the implementation can support low-power state over. 219 * @pe_sel: Controls which PE to trace. 220 * @cfg: Controls the tracing options. 221 * @eventctrl0: Controls the tracing of arbitrary events. 222 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects. 223 * @stallctl: If functionality that prevents trace unit buffer overflows 224 * is available. 225 * @sysstall: Does the system support stall control of the PE? 226 * @nooverflow: Indicate if overflow prevention is supported. 227 * @stall_ctrl: Enables trace unit functionality that prevents trace 228 * unit buffer overflows. 229 * @ts_size: Global timestamp size field. 230 * @ts_ctrl: Controls the insertion of global timestamps in the 231 * trace streams. 232 * @syncpr: Indicates if an implementation has a fixed 233 * synchronization period. 234 * @syncfreq: Controls how often trace synchronization requests occur. 235 * @trccci: Indicates if the trace unit supports cycle counting 236 * for instruction. 237 * @ccsize: Indicates the size of the cycle counter in bits. 238 * @ccitmin: minimum value that can be programmed in 239 * the TRCCCCTLR register. 240 * @ccctlr: Sets the threshold value for cycle counting. 241 * @trcbb: Indicates if the trace unit supports branch broadcast tracing. 242 * @q_support: Q element support characteristics. 243 * @vinst_ctrl: Controls instruction trace filtering. 244 * @viiectlr: Set or read, the address range comparators. 245 * @vissctlr: Set, or read, the single address comparators that control the 246 * ViewInst start-stop logic. 247 * @vipcssctlr: Set, or read, which PE comparator inputs can control the 248 * ViewInst start-stop logic. 249 * @seq_idx: Sequencor index selector. 250 * @seq_ctrl: Control for the sequencer state transition control register. 251 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs. 252 * @seq_state: Set, or read the sequencer state. 253 * @cntr_idx: Counter index seletor. 254 * @cntrldvr: Sets or returns the reload count value for a counter. 255 * @cntr_ctrl: Controls the operation of a counter. 256 * @cntr_val: Sets or returns the value for a counter. 257 * @res_idx: Resource index selector. 258 * @res_ctrl: Controls the selection of the resources in the trace unit. 259 * @ss_ctrl: Controls the corresponding single-shot comparator resource. 260 * @ss_status: The status of the corresponding single-shot comparator. 261 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. 262 * @addr_idx: Address comparator index selector. 263 * @addr_val: Value for address comparator. 264 * @addr_acc: Address comparator access type. 265 * @addr_type: Current status of the comparator register. 266 * @ctxid_idx: Context ID index selector. 267 * @ctxid_size: Size of the context ID field to consider. 268 * @ctxid_pid: Value of the context ID comparator. 269 * @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise 270 * the same value of ctxid_pid. 271 * @ctxid_mask0:Context ID comparator mask for comparator 0-3. 272 * @ctxid_mask1:Context ID comparator mask for comparator 4-7. 273 * @vmid_idx: VM ID index selector. 274 * @vmid_size: Size of the VM ID comparator to consider. 275 * @vmid_val: Value of the VM ID comparator. 276 * @vmid_mask0: VM ID comparator mask for comparator 0-3. 277 * @vmid_mask1: VM ID comparator mask for comparator 4-7. 278 * @s_ex_level: In secure state, indicates whether instruction tracing is 279 * supported for the corresponding Exception level. 280 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is 281 * supported for the corresponding Exception level. 282 * @ext_inp: External input selection. 283 */ 284 struct etmv4_drvdata { 285 void __iomem *base; 286 struct device *dev; 287 struct coresight_device *csdev; 288 spinlock_t spinlock; 289 int cpu; 290 u8 arch; 291 bool enable; 292 bool sticky_enable; 293 bool boot_enable; 294 bool os_unlock; 295 u8 nr_pe; 296 u8 nr_pe_cmp; 297 u8 nr_addr_cmp; 298 u8 nr_cntr; 299 u8 nr_ext_inp; 300 u8 numcidc; 301 u8 numvmidc; 302 u8 nrseqstate; 303 u8 nr_event; 304 u8 nr_resource; 305 u8 nr_ss_cmp; 306 u32 mode; 307 u8 trcid; 308 u8 trcid_size; 309 bool instrp0; 310 bool trccond; 311 bool retstack; 312 bool trc_error; 313 bool atbtrig; 314 bool lpoverride; 315 u32 pe_sel; 316 u32 cfg; 317 u32 eventctrl0; 318 u32 eventctrl1; 319 bool stallctl; 320 bool sysstall; 321 bool nooverflow; 322 u32 stall_ctrl; 323 u8 ts_size; 324 u32 ts_ctrl; 325 bool syncpr; 326 u32 syncfreq; 327 bool trccci; 328 u8 ccsize; 329 u8 ccitmin; 330 u32 ccctlr; 331 bool trcbb; 332 u32 bb_ctrl; 333 bool q_support; 334 u32 vinst_ctrl; 335 u32 viiectlr; 336 u32 vissctlr; 337 u32 vipcssctlr; 338 u8 seq_idx; 339 u32 seq_ctrl[ETM_MAX_SEQ_STATES]; 340 u32 seq_rst; 341 u32 seq_state; 342 u8 cntr_idx; 343 u32 cntrldvr[ETMv4_MAX_CNTR]; 344 u32 cntr_ctrl[ETMv4_MAX_CNTR]; 345 u32 cntr_val[ETMv4_MAX_CNTR]; 346 u8 res_idx; 347 u32 res_ctrl[ETM_MAX_RES_SEL]; 348 u32 ss_ctrl[ETM_MAX_SS_CMP]; 349 u32 ss_status[ETM_MAX_SS_CMP]; 350 u32 ss_pe_cmp[ETM_MAX_SS_CMP]; 351 u8 addr_idx; 352 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP]; 353 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP]; 354 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP]; 355 u8 ctxid_idx; 356 u8 ctxid_size; 357 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP]; 358 u64 ctxid_vpid[ETMv4_MAX_CTXID_CMP]; 359 u32 ctxid_mask0; 360 u32 ctxid_mask1; 361 u8 vmid_idx; 362 u8 vmid_size; 363 u64 vmid_val[ETM_MAX_VMID_CMP]; 364 u32 vmid_mask0; 365 u32 vmid_mask1; 366 u8 s_ex_level; 367 u8 ns_ex_level; 368 u32 ext_inp; 369 }; 370 371 /* Address comparator access types */ 372 enum etm_addr_acctype { 373 ETM_INSTR_ADDR, 374 ETM_DATA_LOAD_ADDR, 375 ETM_DATA_STORE_ADDR, 376 ETM_DATA_LOAD_STORE_ADDR, 377 }; 378 379 /* Address comparator context types */ 380 enum etm_addr_ctxtype { 381 ETM_CTX_NONE, 382 ETM_CTX_CTXID, 383 ETM_CTX_VMID, 384 ETM_CTX_CTXID_VMID, 385 }; 386 387 enum etm_addr_type { 388 ETM_ADDR_TYPE_NONE, 389 ETM_ADDR_TYPE_SINGLE, 390 ETM_ADDR_TYPE_RANGE, 391 ETM_ADDR_TYPE_START, 392 ETM_ADDR_TYPE_STOP, 393 }; 394 #endif 395