1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _CORESIGHT_CORESIGHT_ETM_H 7 #define _CORESIGHT_CORESIGHT_ETM_H 8 9 #include <asm/local.h> 10 #include <linux/spinlock.h> 11 #include <linux/types.h> 12 #include "coresight-priv.h" 13 14 /* 15 * Device registers: 16 * 0x000 - 0x2FC: Trace registers 17 * 0x300 - 0x314: Management registers 18 * 0x318 - 0xEFC: Trace registers 19 * 0xF00: Management registers 20 * 0xFA0 - 0xFA4: Trace registers 21 * 0xFA8 - 0xFFC: Management registers 22 */ 23 /* Trace registers (0x000-0x2FC) */ 24 /* Main control and configuration registers */ 25 #define TRCPRGCTLR 0x004 26 #define TRCPROCSELR 0x008 27 #define TRCSTATR 0x00C 28 #define TRCCONFIGR 0x010 29 #define TRCAUXCTLR 0x018 30 #define TRCEVENTCTL0R 0x020 31 #define TRCEVENTCTL1R 0x024 32 #define TRCRSR 0x028 33 #define TRCSTALLCTLR 0x02C 34 #define TRCTSCTLR 0x030 35 #define TRCSYNCPR 0x034 36 #define TRCCCCTLR 0x038 37 #define TRCBBCTLR 0x03C 38 #define TRCTRACEIDR 0x040 39 #define TRCQCTLR 0x044 40 /* Filtering control registers */ 41 #define TRCVICTLR 0x080 42 #define TRCVIIECTLR 0x084 43 #define TRCVISSCTLR 0x088 44 #define TRCVIPCSSCTLR 0x08C 45 #define TRCVDCTLR 0x0A0 46 #define TRCVDSACCTLR 0x0A4 47 #define TRCVDARCCTLR 0x0A8 48 /* Derived resources registers */ 49 #define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ 50 #define TRCSEQRSTEVR 0x118 51 #define TRCSEQSTR 0x11C 52 #define TRCEXTINSELR 0x120 53 #define TRCEXTINSELRn(n) (0x120 + (n * 4)) /* n = 0-3 */ 54 #define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ 55 #define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ 56 #define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ 57 /* ID registers */ 58 #define TRCIDR8 0x180 59 #define TRCIDR9 0x184 60 #define TRCIDR10 0x188 61 #define TRCIDR11 0x18C 62 #define TRCIDR12 0x190 63 #define TRCIDR13 0x194 64 #define TRCIMSPEC0 0x1C0 65 #define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ 66 #define TRCIDR0 0x1E0 67 #define TRCIDR1 0x1E4 68 #define TRCIDR2 0x1E8 69 #define TRCIDR3 0x1EC 70 #define TRCIDR4 0x1F0 71 #define TRCIDR5 0x1F4 72 #define TRCIDR6 0x1F8 73 #define TRCIDR7 0x1FC 74 /* 75 * Resource selection registers, n = 2-31. 76 * First pair (regs 0, 1) is always present and is reserved. 77 */ 78 #define TRCRSCTLRn(n) (0x200 + (n * 4)) 79 /* Single-shot comparator registers, n = 0-7 */ 80 #define TRCSSCCRn(n) (0x280 + (n * 4)) 81 #define TRCSSCSRn(n) (0x2A0 + (n * 4)) 82 #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) 83 /* Management registers (0x300-0x314) */ 84 #define TRCOSLAR 0x300 85 #define TRCOSLSR 0x304 86 #define TRCPDCR 0x310 87 #define TRCPDSR 0x314 88 /* Trace registers (0x318-0xEFC) */ 89 /* Address Comparator registers n = 0-15 */ 90 #define TRCACVRn(n) (0x400 + (n * 8)) 91 #define TRCACATRn(n) (0x480 + (n * 8)) 92 /* Data Value Comparator Value registers, n = 0-7 */ 93 #define TRCDVCVRn(n) (0x500 + (n * 16)) 94 #define TRCDVCMRn(n) (0x580 + (n * 16)) 95 /* ContextID/Virtual ContextID comparators, n = 0-7 */ 96 #define TRCCIDCVRn(n) (0x600 + (n * 8)) 97 #define TRCVMIDCVRn(n) (0x640 + (n * 8)) 98 #define TRCCIDCCTLR0 0x680 99 #define TRCCIDCCTLR1 0x684 100 #define TRCVMIDCCTLR0 0x688 101 #define TRCVMIDCCTLR1 0x68C 102 /* Management register (0xF00) */ 103 /* Integration control registers */ 104 #define TRCITCTRL 0xF00 105 /* Trace registers (0xFA0-0xFA4) */ 106 /* Claim tag registers */ 107 #define TRCCLAIMSET 0xFA0 108 #define TRCCLAIMCLR 0xFA4 109 /* Management registers (0xFA8-0xFFC) */ 110 #define TRCDEVAFF0 0xFA8 111 #define TRCDEVAFF1 0xFAC 112 #define TRCLAR 0xFB0 113 #define TRCLSR 0xFB4 114 #define TRCAUTHSTATUS 0xFB8 115 #define TRCDEVARCH 0xFBC 116 #define TRCDEVID 0xFC8 117 #define TRCDEVTYPE 0xFCC 118 #define TRCPIDR4 0xFD0 119 #define TRCPIDR5 0xFD4 120 #define TRCPIDR6 0xFD8 121 #define TRCPIDR7 0xFDC 122 #define TRCPIDR0 0xFE0 123 #define TRCPIDR1 0xFE4 124 #define TRCPIDR2 0xFE8 125 #define TRCPIDR3 0xFEC 126 #define TRCCIDR0 0xFF0 127 #define TRCCIDR1 0xFF4 128 #define TRCCIDR2 0xFF8 129 #define TRCCIDR3 0xFFC 130 131 #define TRCRSR_TA BIT(12) 132 133 /* 134 * System instructions to access ETM registers. 135 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions 136 */ 137 #define ETM4x_OFFSET_TO_REG(x) ((x) >> 2) 138 139 #define ETM4x_CRn(n) (((n) >> 7) & 0x7) 140 #define ETM4x_Op2(n) (((n) >> 4) & 0x7) 141 #define ETM4x_CRm(n) ((n) & 0xf) 142 143 #include <asm/sysreg.h> 144 #define ETM4x_REG_NUM_TO_SYSREG(n) \ 145 sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n)) 146 147 #define READ_ETM4x_REG(reg) \ 148 read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg))) 149 #define WRITE_ETM4x_REG(val, reg) \ 150 write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg))) 151 152 #define read_etm4x_sysreg_const_offset(offset) \ 153 READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset)) 154 155 #define write_etm4x_sysreg_const_offset(val, offset) \ 156 WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset)) 157 158 #define CASE_READ(res, x) \ 159 case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; } 160 161 #define CASE_WRITE(val, x) \ 162 case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; } 163 164 #define CASE_NOP(__unused, x) \ 165 case (x): /* fall through */ 166 167 #define ETE_ONLY_SYSREG_LIST(op, val) \ 168 CASE_##op((val), TRCRSR) \ 169 CASE_##op((val), TRCEXTINSELRn(1)) \ 170 CASE_##op((val), TRCEXTINSELRn(2)) \ 171 CASE_##op((val), TRCEXTINSELRn(3)) 172 173 /* List of registers accessible via System instructions */ 174 #define ETM4x_ONLY_SYSREG_LIST(op, val) \ 175 CASE_##op((val), TRCPROCSELR) \ 176 CASE_##op((val), TRCVDCTLR) \ 177 CASE_##op((val), TRCVDSACCTLR) \ 178 CASE_##op((val), TRCVDARCCTLR) \ 179 CASE_##op((val), TRCOSLAR) 180 181 #define ETM_COMMON_SYSREG_LIST(op, val) \ 182 CASE_##op((val), TRCPRGCTLR) \ 183 CASE_##op((val), TRCSTATR) \ 184 CASE_##op((val), TRCCONFIGR) \ 185 CASE_##op((val), TRCAUXCTLR) \ 186 CASE_##op((val), TRCEVENTCTL0R) \ 187 CASE_##op((val), TRCEVENTCTL1R) \ 188 CASE_##op((val), TRCSTALLCTLR) \ 189 CASE_##op((val), TRCTSCTLR) \ 190 CASE_##op((val), TRCSYNCPR) \ 191 CASE_##op((val), TRCCCCTLR) \ 192 CASE_##op((val), TRCBBCTLR) \ 193 CASE_##op((val), TRCTRACEIDR) \ 194 CASE_##op((val), TRCQCTLR) \ 195 CASE_##op((val), TRCVICTLR) \ 196 CASE_##op((val), TRCVIIECTLR) \ 197 CASE_##op((val), TRCVISSCTLR) \ 198 CASE_##op((val), TRCVIPCSSCTLR) \ 199 CASE_##op((val), TRCSEQEVRn(0)) \ 200 CASE_##op((val), TRCSEQEVRn(1)) \ 201 CASE_##op((val), TRCSEQEVRn(2)) \ 202 CASE_##op((val), TRCSEQRSTEVR) \ 203 CASE_##op((val), TRCSEQSTR) \ 204 CASE_##op((val), TRCEXTINSELR) \ 205 CASE_##op((val), TRCCNTRLDVRn(0)) \ 206 CASE_##op((val), TRCCNTRLDVRn(1)) \ 207 CASE_##op((val), TRCCNTRLDVRn(2)) \ 208 CASE_##op((val), TRCCNTRLDVRn(3)) \ 209 CASE_##op((val), TRCCNTCTLRn(0)) \ 210 CASE_##op((val), TRCCNTCTLRn(1)) \ 211 CASE_##op((val), TRCCNTCTLRn(2)) \ 212 CASE_##op((val), TRCCNTCTLRn(3)) \ 213 CASE_##op((val), TRCCNTVRn(0)) \ 214 CASE_##op((val), TRCCNTVRn(1)) \ 215 CASE_##op((val), TRCCNTVRn(2)) \ 216 CASE_##op((val), TRCCNTVRn(3)) \ 217 CASE_##op((val), TRCIDR8) \ 218 CASE_##op((val), TRCIDR9) \ 219 CASE_##op((val), TRCIDR10) \ 220 CASE_##op((val), TRCIDR11) \ 221 CASE_##op((val), TRCIDR12) \ 222 CASE_##op((val), TRCIDR13) \ 223 CASE_##op((val), TRCIMSPECn(0)) \ 224 CASE_##op((val), TRCIMSPECn(1)) \ 225 CASE_##op((val), TRCIMSPECn(2)) \ 226 CASE_##op((val), TRCIMSPECn(3)) \ 227 CASE_##op((val), TRCIMSPECn(4)) \ 228 CASE_##op((val), TRCIMSPECn(5)) \ 229 CASE_##op((val), TRCIMSPECn(6)) \ 230 CASE_##op((val), TRCIMSPECn(7)) \ 231 CASE_##op((val), TRCIDR0) \ 232 CASE_##op((val), TRCIDR1) \ 233 CASE_##op((val), TRCIDR2) \ 234 CASE_##op((val), TRCIDR3) \ 235 CASE_##op((val), TRCIDR4) \ 236 CASE_##op((val), TRCIDR5) \ 237 CASE_##op((val), TRCIDR6) \ 238 CASE_##op((val), TRCIDR7) \ 239 CASE_##op((val), TRCRSCTLRn(2)) \ 240 CASE_##op((val), TRCRSCTLRn(3)) \ 241 CASE_##op((val), TRCRSCTLRn(4)) \ 242 CASE_##op((val), TRCRSCTLRn(5)) \ 243 CASE_##op((val), TRCRSCTLRn(6)) \ 244 CASE_##op((val), TRCRSCTLRn(7)) \ 245 CASE_##op((val), TRCRSCTLRn(8)) \ 246 CASE_##op((val), TRCRSCTLRn(9)) \ 247 CASE_##op((val), TRCRSCTLRn(10)) \ 248 CASE_##op((val), TRCRSCTLRn(11)) \ 249 CASE_##op((val), TRCRSCTLRn(12)) \ 250 CASE_##op((val), TRCRSCTLRn(13)) \ 251 CASE_##op((val), TRCRSCTLRn(14)) \ 252 CASE_##op((val), TRCRSCTLRn(15)) \ 253 CASE_##op((val), TRCRSCTLRn(16)) \ 254 CASE_##op((val), TRCRSCTLRn(17)) \ 255 CASE_##op((val), TRCRSCTLRn(18)) \ 256 CASE_##op((val), TRCRSCTLRn(19)) \ 257 CASE_##op((val), TRCRSCTLRn(20)) \ 258 CASE_##op((val), TRCRSCTLRn(21)) \ 259 CASE_##op((val), TRCRSCTLRn(22)) \ 260 CASE_##op((val), TRCRSCTLRn(23)) \ 261 CASE_##op((val), TRCRSCTLRn(24)) \ 262 CASE_##op((val), TRCRSCTLRn(25)) \ 263 CASE_##op((val), TRCRSCTLRn(26)) \ 264 CASE_##op((val), TRCRSCTLRn(27)) \ 265 CASE_##op((val), TRCRSCTLRn(28)) \ 266 CASE_##op((val), TRCRSCTLRn(29)) \ 267 CASE_##op((val), TRCRSCTLRn(30)) \ 268 CASE_##op((val), TRCRSCTLRn(31)) \ 269 CASE_##op((val), TRCSSCCRn(0)) \ 270 CASE_##op((val), TRCSSCCRn(1)) \ 271 CASE_##op((val), TRCSSCCRn(2)) \ 272 CASE_##op((val), TRCSSCCRn(3)) \ 273 CASE_##op((val), TRCSSCCRn(4)) \ 274 CASE_##op((val), TRCSSCCRn(5)) \ 275 CASE_##op((val), TRCSSCCRn(6)) \ 276 CASE_##op((val), TRCSSCCRn(7)) \ 277 CASE_##op((val), TRCSSCSRn(0)) \ 278 CASE_##op((val), TRCSSCSRn(1)) \ 279 CASE_##op((val), TRCSSCSRn(2)) \ 280 CASE_##op((val), TRCSSCSRn(3)) \ 281 CASE_##op((val), TRCSSCSRn(4)) \ 282 CASE_##op((val), TRCSSCSRn(5)) \ 283 CASE_##op((val), TRCSSCSRn(6)) \ 284 CASE_##op((val), TRCSSCSRn(7)) \ 285 CASE_##op((val), TRCSSPCICRn(0)) \ 286 CASE_##op((val), TRCSSPCICRn(1)) \ 287 CASE_##op((val), TRCSSPCICRn(2)) \ 288 CASE_##op((val), TRCSSPCICRn(3)) \ 289 CASE_##op((val), TRCSSPCICRn(4)) \ 290 CASE_##op((val), TRCSSPCICRn(5)) \ 291 CASE_##op((val), TRCSSPCICRn(6)) \ 292 CASE_##op((val), TRCSSPCICRn(7)) \ 293 CASE_##op((val), TRCOSLSR) \ 294 CASE_##op((val), TRCACVRn(0)) \ 295 CASE_##op((val), TRCACVRn(1)) \ 296 CASE_##op((val), TRCACVRn(2)) \ 297 CASE_##op((val), TRCACVRn(3)) \ 298 CASE_##op((val), TRCACVRn(4)) \ 299 CASE_##op((val), TRCACVRn(5)) \ 300 CASE_##op((val), TRCACVRn(6)) \ 301 CASE_##op((val), TRCACVRn(7)) \ 302 CASE_##op((val), TRCACVRn(8)) \ 303 CASE_##op((val), TRCACVRn(9)) \ 304 CASE_##op((val), TRCACVRn(10)) \ 305 CASE_##op((val), TRCACVRn(11)) \ 306 CASE_##op((val), TRCACVRn(12)) \ 307 CASE_##op((val), TRCACVRn(13)) \ 308 CASE_##op((val), TRCACVRn(14)) \ 309 CASE_##op((val), TRCACVRn(15)) \ 310 CASE_##op((val), TRCACATRn(0)) \ 311 CASE_##op((val), TRCACATRn(1)) \ 312 CASE_##op((val), TRCACATRn(2)) \ 313 CASE_##op((val), TRCACATRn(3)) \ 314 CASE_##op((val), TRCACATRn(4)) \ 315 CASE_##op((val), TRCACATRn(5)) \ 316 CASE_##op((val), TRCACATRn(6)) \ 317 CASE_##op((val), TRCACATRn(7)) \ 318 CASE_##op((val), TRCACATRn(8)) \ 319 CASE_##op((val), TRCACATRn(9)) \ 320 CASE_##op((val), TRCACATRn(10)) \ 321 CASE_##op((val), TRCACATRn(11)) \ 322 CASE_##op((val), TRCACATRn(12)) \ 323 CASE_##op((val), TRCACATRn(13)) \ 324 CASE_##op((val), TRCACATRn(14)) \ 325 CASE_##op((val), TRCACATRn(15)) \ 326 CASE_##op((val), TRCDVCVRn(0)) \ 327 CASE_##op((val), TRCDVCVRn(1)) \ 328 CASE_##op((val), TRCDVCVRn(2)) \ 329 CASE_##op((val), TRCDVCVRn(3)) \ 330 CASE_##op((val), TRCDVCVRn(4)) \ 331 CASE_##op((val), TRCDVCVRn(5)) \ 332 CASE_##op((val), TRCDVCVRn(6)) \ 333 CASE_##op((val), TRCDVCVRn(7)) \ 334 CASE_##op((val), TRCDVCMRn(0)) \ 335 CASE_##op((val), TRCDVCMRn(1)) \ 336 CASE_##op((val), TRCDVCMRn(2)) \ 337 CASE_##op((val), TRCDVCMRn(3)) \ 338 CASE_##op((val), TRCDVCMRn(4)) \ 339 CASE_##op((val), TRCDVCMRn(5)) \ 340 CASE_##op((val), TRCDVCMRn(6)) \ 341 CASE_##op((val), TRCDVCMRn(7)) \ 342 CASE_##op((val), TRCCIDCVRn(0)) \ 343 CASE_##op((val), TRCCIDCVRn(1)) \ 344 CASE_##op((val), TRCCIDCVRn(2)) \ 345 CASE_##op((val), TRCCIDCVRn(3)) \ 346 CASE_##op((val), TRCCIDCVRn(4)) \ 347 CASE_##op((val), TRCCIDCVRn(5)) \ 348 CASE_##op((val), TRCCIDCVRn(6)) \ 349 CASE_##op((val), TRCCIDCVRn(7)) \ 350 CASE_##op((val), TRCVMIDCVRn(0)) \ 351 CASE_##op((val), TRCVMIDCVRn(1)) \ 352 CASE_##op((val), TRCVMIDCVRn(2)) \ 353 CASE_##op((val), TRCVMIDCVRn(3)) \ 354 CASE_##op((val), TRCVMIDCVRn(4)) \ 355 CASE_##op((val), TRCVMIDCVRn(5)) \ 356 CASE_##op((val), TRCVMIDCVRn(6)) \ 357 CASE_##op((val), TRCVMIDCVRn(7)) \ 358 CASE_##op((val), TRCCIDCCTLR0) \ 359 CASE_##op((val), TRCCIDCCTLR1) \ 360 CASE_##op((val), TRCVMIDCCTLR0) \ 361 CASE_##op((val), TRCVMIDCCTLR1) \ 362 CASE_##op((val), TRCCLAIMSET) \ 363 CASE_##op((val), TRCCLAIMCLR) \ 364 CASE_##op((val), TRCAUTHSTATUS) \ 365 CASE_##op((val), TRCDEVARCH) \ 366 CASE_##op((val), TRCDEVID) 367 368 /* List of registers only accessible via memory-mapped interface */ 369 #define ETM_MMAP_LIST(op, val) \ 370 CASE_##op((val), TRCDEVTYPE) \ 371 CASE_##op((val), TRCPDCR) \ 372 CASE_##op((val), TRCPDSR) \ 373 CASE_##op((val), TRCDEVAFF0) \ 374 CASE_##op((val), TRCDEVAFF1) \ 375 CASE_##op((val), TRCLAR) \ 376 CASE_##op((val), TRCLSR) \ 377 CASE_##op((val), TRCITCTRL) \ 378 CASE_##op((val), TRCPIDR4) \ 379 CASE_##op((val), TRCPIDR0) \ 380 CASE_##op((val), TRCPIDR1) \ 381 CASE_##op((val), TRCPIDR2) \ 382 CASE_##op((val), TRCPIDR3) 383 384 #define ETM4x_READ_SYSREG_CASES(res) \ 385 ETM_COMMON_SYSREG_LIST(READ, (res)) \ 386 ETM4x_ONLY_SYSREG_LIST(READ, (res)) 387 388 #define ETM4x_WRITE_SYSREG_CASES(val) \ 389 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \ 390 ETM4x_ONLY_SYSREG_LIST(WRITE, (val)) 391 392 #define ETM_COMMON_SYSREG_LIST_CASES \ 393 ETM_COMMON_SYSREG_LIST(NOP, __unused) 394 395 #define ETM4x_ONLY_SYSREG_LIST_CASES \ 396 ETM4x_ONLY_SYSREG_LIST(NOP, __unused) 397 398 #define ETM4x_SYSREG_LIST_CASES \ 399 ETM_COMMON_SYSREG_LIST_CASES \ 400 ETM4x_ONLY_SYSREG_LIST(NOP, __unused) 401 402 #define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused) 403 404 /* ETE only supports system register access */ 405 #define ETE_READ_CASES(res) \ 406 ETM_COMMON_SYSREG_LIST(READ, (res)) \ 407 ETE_ONLY_SYSREG_LIST(READ, (res)) 408 409 #define ETE_WRITE_CASES(val) \ 410 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \ 411 ETE_ONLY_SYSREG_LIST(WRITE, (val)) 412 413 #define ETE_ONLY_SYSREG_LIST_CASES \ 414 ETE_ONLY_SYSREG_LIST(NOP, __unused) 415 416 #define read_etm4x_sysreg_offset(offset, _64bit) \ 417 ({ \ 418 u64 __val; \ 419 \ 420 if (__builtin_constant_p((offset))) \ 421 __val = read_etm4x_sysreg_const_offset((offset)); \ 422 else \ 423 __val = etm4x_sysreg_read((offset), true, (_64bit)); \ 424 __val; \ 425 }) 426 427 #define write_etm4x_sysreg_offset(val, offset, _64bit) \ 428 do { \ 429 if (__builtin_constant_p((offset))) \ 430 write_etm4x_sysreg_const_offset((val), \ 431 (offset)); \ 432 else \ 433 etm4x_sysreg_write((val), (offset), true, \ 434 (_64bit)); \ 435 } while (0) 436 437 438 #define etm4x_relaxed_read32(csa, offset) \ 439 ((u32)((csa)->io_mem ? \ 440 readl_relaxed((csa)->base + (offset)) : \ 441 read_etm4x_sysreg_offset((offset), false))) 442 443 #define etm4x_relaxed_read64(csa, offset) \ 444 ((u64)((csa)->io_mem ? \ 445 readq_relaxed((csa)->base + (offset)) : \ 446 read_etm4x_sysreg_offset((offset), true))) 447 448 #define etm4x_read32(csa, offset) \ 449 ({ \ 450 u32 __val = etm4x_relaxed_read32((csa), (offset)); \ 451 __iormb(__val); \ 452 __val; \ 453 }) 454 455 #define etm4x_read64(csa, offset) \ 456 ({ \ 457 u64 __val = etm4x_relaxed_read64((csa), (offset)); \ 458 __iormb(__val); \ 459 __val; \ 460 }) 461 462 #define etm4x_relaxed_write32(csa, val, offset) \ 463 do { \ 464 if ((csa)->io_mem) \ 465 writel_relaxed((val), (csa)->base + (offset)); \ 466 else \ 467 write_etm4x_sysreg_offset((val), (offset), \ 468 false); \ 469 } while (0) 470 471 #define etm4x_relaxed_write64(csa, val, offset) \ 472 do { \ 473 if ((csa)->io_mem) \ 474 writeq_relaxed((val), (csa)->base + (offset)); \ 475 else \ 476 write_etm4x_sysreg_offset((val), (offset), \ 477 true); \ 478 } while (0) 479 480 #define etm4x_write32(csa, val, offset) \ 481 do { \ 482 __iowmb(); \ 483 etm4x_relaxed_write32((csa), (val), (offset)); \ 484 } while (0) 485 486 #define etm4x_write64(csa, val, offset) \ 487 do { \ 488 __iowmb(); \ 489 etm4x_relaxed_write64((csa), (val), (offset)); \ 490 } while (0) 491 492 493 /* ETMv4 resources */ 494 #define ETM_MAX_NR_PE 8 495 #define ETMv4_MAX_CNTR 4 496 #define ETM_MAX_SEQ_STATES 4 497 #define ETM_MAX_EXT_INP_SEL 4 498 #define ETM_MAX_EXT_INP 256 499 #define ETM_MAX_EXT_OUT 4 500 #define ETM_MAX_SINGLE_ADDR_CMP 16 501 #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2) 502 #define ETM_MAX_DATA_VAL_CMP 8 503 #define ETMv4_MAX_CTXID_CMP 8 504 #define ETM_MAX_VMID_CMP 8 505 #define ETM_MAX_PE_CMP 8 506 #define ETM_MAX_RES_SEL 32 507 #define ETM_MAX_SS_CMP 8 508 509 #define ETMv4_SYNC_MASK 0x1F 510 #define ETM_CYC_THRESHOLD_MASK 0xFFF 511 #define ETM_CYC_THRESHOLD_DEFAULT 0x100 512 #define ETMv4_EVENT_MASK 0xFF 513 #define ETM_CNTR_MAX_VAL 0xFFFF 514 #define ETM_TRACEID_MASK 0x3f 515 516 /* ETMv4 programming modes */ 517 #define ETM_MODE_EXCLUDE BIT(0) 518 #define ETM_MODE_LOAD BIT(1) 519 #define ETM_MODE_STORE BIT(2) 520 #define ETM_MODE_LOAD_STORE BIT(3) 521 #define ETM_MODE_BB BIT(4) 522 #define ETMv4_MODE_CYCACC BIT(5) 523 #define ETMv4_MODE_CTXID BIT(6) 524 #define ETM_MODE_VMID BIT(7) 525 #define ETM_MODE_COND(val) BMVAL(val, 8, 10) 526 #define ETMv4_MODE_TIMESTAMP BIT(11) 527 #define ETM_MODE_RETURNSTACK BIT(12) 528 #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14) 529 #define ETM_MODE_DATA_TRACE_ADDR BIT(15) 530 #define ETM_MODE_DATA_TRACE_VAL BIT(16) 531 #define ETM_MODE_ISTALL BIT(17) 532 #define ETM_MODE_DSTALL BIT(18) 533 #define ETM_MODE_ATB_TRIGGER BIT(19) 534 #define ETM_MODE_LPOVERRIDE BIT(20) 535 #define ETM_MODE_ISTALL_EN BIT(21) 536 #define ETM_MODE_DSTALL_EN BIT(22) 537 #define ETM_MODE_INSTPRIO BIT(23) 538 #define ETM_MODE_NOOVERFLOW BIT(24) 539 #define ETM_MODE_TRACE_RESET BIT(25) 540 #define ETM_MODE_TRACE_ERR BIT(26) 541 #define ETM_MODE_VIEWINST_STARTSTOP BIT(27) 542 #define ETMv4_MODE_ALL (GENMASK(27, 0) | \ 543 ETM_MODE_EXCL_KERN | \ 544 ETM_MODE_EXCL_USER) 545 546 /* 547 * TRCOSLSR.OSLM advertises the OS Lock model. 548 * OSLM[2:0] = TRCOSLSR[4:3,0] 549 * 550 * 0b000 - Trace OS Lock is not implemented. 551 * 0b010 - Trace OS Lock is implemented. 552 * 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock. 553 */ 554 #define ETM_OSLOCK_NI 0b000 555 #define ETM_OSLOCK_PRESENT 0b010 556 #define ETM_OSLOCK_PE 0b100 557 558 #define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1)) 559 560 /* 561 * TRCDEVARCH Bit field definitions 562 * Bits[31:21] - ARCHITECT = Always Arm Ltd. 563 * * Bits[31:28] = 0x4 564 * * Bits[27:21] = 0b0111011 565 * Bit[20] - PRESENT, Indicates the presence of this register. 566 * 567 * Bit[19:16] - REVISION, Revision of the architecture. 568 * 569 * Bit[15:0] - ARCHID, Identifies this component as an ETM 570 * * Bits[15:12] - architecture version of ETM 571 * * = 4 for ETMv4 572 * * Bits[11:0] = 0xA13, architecture part number for ETM. 573 */ 574 #define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21) 575 #define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21)) 576 #define ETM_DEVARCH_PRESENT BIT(20) 577 #define ETM_DEVARCH_REVISION_SHIFT 16 578 #define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16) 579 #define ETM_DEVARCH_REVISION(x) \ 580 (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT) 581 #define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0) 582 #define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12 583 #define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12) 584 #define ETM_DEVARCH_ARCHID_ARCH_VER(x) \ 585 (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) 586 587 #define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \ 588 (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) 589 590 #define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL) 591 592 #define ETM_DEVARCH_MAKE_ARCHID(major) \ 593 ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13)) 594 595 #define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4) 596 #define ETM_DEVARCH_ARCHID_ETE ETM_DEVARCH_MAKE_ARCHID(0x5) 597 598 #define ETM_DEVARCH_ID_MASK \ 599 (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT) 600 #define ETM_DEVARCH_ETMv4x_ARCH \ 601 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT) 602 #define ETM_DEVARCH_ETE_ARCH \ 603 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT) 604 605 #define TRCSTATR_IDLE_BIT 0 606 #define TRCSTATR_PMSTABLE_BIT 1 607 #define ETM_DEFAULT_ADDR_COMP 0 608 609 #define TRCSSCSRn_PC BIT(3) 610 611 /* PowerDown Control Register bits */ 612 #define TRCPDCR_PU BIT(3) 613 614 #define TRCACATR_EXLEVEL_SHIFT 8 615 616 /* 617 * Exception level mask for Secure and Non-Secure ELs. 618 * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn). 619 * The Secure and Non-Secure ELs are always to gether. 620 * Non-secure EL3 is never implemented. 621 * We use the following generic mask as they appear in different 622 * registers and this can be shifted for the appropriate 623 * fields. 624 */ 625 #define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */ 626 #define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */ 627 #define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */ 628 #define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Monitor */ 629 #define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */ 630 #define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */ 631 #define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */ 632 633 #define ETM_EXLEVEL_MASK (GENMASK(6, 0)) 634 #define ETM_EXLEVEL_S_MASK (GENMASK(3, 0)) 635 #define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4)) 636 637 /* access level controls in TRCACATRn */ 638 #define TRCACATR_EXLEVEL_SHIFT 8 639 640 /* access level control in TRCVICTLR */ 641 #define TRCVICTLR_EXLEVEL_SHIFT 16 642 #define TRCVICTLR_EXLEVEL_S_SHIFT 16 643 #define TRCVICTLR_EXLEVEL_NS_SHIFT 20 644 645 /* secure / non secure masks - TRCVICTLR, IDR3 */ 646 #define TRCVICTLR_EXLEVEL_MASK (ETM_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHIFT) 647 #define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT) 648 #define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT) 649 650 #define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8 651 #define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT) 652 #define ETM_TRCIDR1_ARCH_MAJOR(x) \ 653 (((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT) 654 #define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4 655 #define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT) 656 #define ETM_TRCIDR1_ARCH_MINOR(x) \ 657 (((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT) 658 #define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT 659 #define ETM_TRCIDR1_ARCH_MASK \ 660 (ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK) 661 662 #define ETM_TRCIDR1_ARCH_ETMv4 0x4 663 664 /* 665 * Driver representation of the ETM architecture. 666 * The version of an ETM component can be detected from 667 * 668 * TRCDEVARCH - CoreSight architected register 669 * - Bits[15:12] - Major version 670 * - Bits[19:16] - Minor version 671 * TRCIDR1 - ETM architected register 672 * - Bits[11:8] - Major version 673 * - Bits[7:4] - Minor version 674 * We must rely on TRCDEVARCH for the version information, 675 * however we don't want to break the support for potential 676 * old implementations which might not implement it. Thus 677 * we fall back to TRCIDR1 if TRCDEVARCH is not implemented 678 * for memory mapped components. 679 * Now to make certain decisions easier based on the version 680 * we use an internal representation of the version in the 681 * driver, as follows : 682 * 683 * ETM_ARCH_VERSION[7:0], where : 684 * Bits[7:4] - Major version 685 * Bits[3:0] - Minro version 686 */ 687 #define ETM_ARCH_VERSION(major, minor) \ 688 ((((major) & 0xfU) << 4) | (((minor) & 0xfU))) 689 #define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU) 690 #define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU) 691 692 #define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0) 693 #define ETM_ARCH_ETE ETM_ARCH_VERSION(5, 0) 694 695 /* Interpretation of resource numbers change at ETM v4.3 architecture */ 696 #define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3) 697 698 static inline u8 etm_devarch_to_arch(u32 devarch) 699 { 700 return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch), 701 ETM_DEVARCH_REVISION(devarch)); 702 } 703 704 static inline u8 etm_trcidr_to_arch(u32 trcidr1) 705 { 706 return ETM_ARCH_VERSION(ETM_TRCIDR1_ARCH_MAJOR(trcidr1), 707 ETM_TRCIDR1_ARCH_MINOR(trcidr1)); 708 } 709 710 enum etm_impdef_type { 711 ETM4_IMPDEF_HISI_CORE_COMMIT, 712 ETM4_IMPDEF_FEATURE_MAX, 713 }; 714 715 /** 716 * struct etmv4_config - configuration information related to an ETMv4 717 * @mode: Controls various modes supported by this ETM. 718 * @pe_sel: Controls which PE to trace. 719 * @cfg: Controls the tracing options. 720 * @eventctrl0: Controls the tracing of arbitrary events. 721 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects. 722 * @stallctl: If functionality that prevents trace unit buffer overflows 723 * is available. 724 * @ts_ctrl: Controls the insertion of global timestamps in the 725 * trace streams. 726 * @syncfreq: Controls how often trace synchronization requests occur. 727 * the TRCCCCTLR register. 728 * @ccctlr: Sets the threshold value for cycle counting. 729 * @vinst_ctrl: Controls instruction trace filtering. 730 * @viiectlr: Set or read, the address range comparators. 731 * @vissctlr: Set, or read, the single address comparators that control the 732 * ViewInst start-stop logic. 733 * @vipcssctlr: Set, or read, which PE comparator inputs can control the 734 * ViewInst start-stop logic. 735 * @seq_idx: Sequencor index selector. 736 * @seq_ctrl: Control for the sequencer state transition control register. 737 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs. 738 * @seq_state: Set, or read the sequencer state. 739 * @cntr_idx: Counter index seletor. 740 * @cntrldvr: Sets or returns the reload count value for a counter. 741 * @cntr_ctrl: Controls the operation of a counter. 742 * @cntr_val: Sets or returns the value for a counter. 743 * @res_idx: Resource index selector. 744 * @res_ctrl: Controls the selection of the resources in the trace unit. 745 * @ss_idx: Single-shot index selector. 746 * @ss_ctrl: Controls the corresponding single-shot comparator resource. 747 * @ss_status: The status of the corresponding single-shot comparator. 748 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. 749 * @addr_idx: Address comparator index selector. 750 * @addr_val: Value for address comparator. 751 * @addr_acc: Address comparator access type. 752 * @addr_type: Current status of the comparator register. 753 * @ctxid_idx: Context ID index selector. 754 * @ctxid_pid: Value of the context ID comparator. 755 * @ctxid_mask0:Context ID comparator mask for comparator 0-3. 756 * @ctxid_mask1:Context ID comparator mask for comparator 4-7. 757 * @vmid_idx: VM ID index selector. 758 * @vmid_val: Value of the VM ID comparator. 759 * @vmid_mask0: VM ID comparator mask for comparator 0-3. 760 * @vmid_mask1: VM ID comparator mask for comparator 4-7. 761 * @ext_inp: External input selection. 762 * @s_ex_level: Secure ELs where tracing is supported. 763 */ 764 struct etmv4_config { 765 u32 mode; 766 u32 pe_sel; 767 u32 cfg; 768 u32 eventctrl0; 769 u32 eventctrl1; 770 u32 stall_ctrl; 771 u32 ts_ctrl; 772 u32 syncfreq; 773 u32 ccctlr; 774 u32 bb_ctrl; 775 u32 vinst_ctrl; 776 u32 viiectlr; 777 u32 vissctlr; 778 u32 vipcssctlr; 779 u8 seq_idx; 780 u32 seq_ctrl[ETM_MAX_SEQ_STATES]; 781 u32 seq_rst; 782 u32 seq_state; 783 u8 cntr_idx; 784 u32 cntrldvr[ETMv4_MAX_CNTR]; 785 u32 cntr_ctrl[ETMv4_MAX_CNTR]; 786 u32 cntr_val[ETMv4_MAX_CNTR]; 787 u8 res_idx; 788 u32 res_ctrl[ETM_MAX_RES_SEL]; 789 u8 ss_idx; 790 u32 ss_ctrl[ETM_MAX_SS_CMP]; 791 u32 ss_status[ETM_MAX_SS_CMP]; 792 u32 ss_pe_cmp[ETM_MAX_SS_CMP]; 793 u8 addr_idx; 794 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP]; 795 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP]; 796 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP]; 797 u8 ctxid_idx; 798 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP]; 799 u32 ctxid_mask0; 800 u32 ctxid_mask1; 801 u8 vmid_idx; 802 u64 vmid_val[ETM_MAX_VMID_CMP]; 803 u32 vmid_mask0; 804 u32 vmid_mask1; 805 u32 ext_inp; 806 u8 s_ex_level; 807 }; 808 809 /** 810 * struct etm4_save_state - state to be preserved when ETM is without power 811 */ 812 struct etmv4_save_state { 813 u32 trcprgctlr; 814 u32 trcprocselr; 815 u32 trcconfigr; 816 u32 trcauxctlr; 817 u32 trceventctl0r; 818 u32 trceventctl1r; 819 u32 trcstallctlr; 820 u32 trctsctlr; 821 u32 trcsyncpr; 822 u32 trcccctlr; 823 u32 trcbbctlr; 824 u32 trctraceidr; 825 u32 trcqctlr; 826 827 u32 trcvictlr; 828 u32 trcviiectlr; 829 u32 trcvissctlr; 830 u32 trcvipcssctlr; 831 u32 trcvdctlr; 832 u32 trcvdsacctlr; 833 u32 trcvdarcctlr; 834 835 u32 trcseqevr[ETM_MAX_SEQ_STATES]; 836 u32 trcseqrstevr; 837 u32 trcseqstr; 838 u32 trcextinselr; 839 u32 trccntrldvr[ETMv4_MAX_CNTR]; 840 u32 trccntctlr[ETMv4_MAX_CNTR]; 841 u32 trccntvr[ETMv4_MAX_CNTR]; 842 843 u32 trcrsctlr[ETM_MAX_RES_SEL]; 844 845 u32 trcssccr[ETM_MAX_SS_CMP]; 846 u32 trcsscsr[ETM_MAX_SS_CMP]; 847 u32 trcsspcicr[ETM_MAX_SS_CMP]; 848 849 u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP]; 850 u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP]; 851 u64 trccidcvr[ETMv4_MAX_CTXID_CMP]; 852 u64 trcvmidcvr[ETM_MAX_VMID_CMP]; 853 u32 trccidcctlr0; 854 u32 trccidcctlr1; 855 u32 trcvmidcctlr0; 856 u32 trcvmidcctlr1; 857 858 u32 trcclaimset; 859 860 u32 cntr_val[ETMv4_MAX_CNTR]; 861 u32 seq_state; 862 u32 vinst_ctrl; 863 u32 ss_status[ETM_MAX_SS_CMP]; 864 865 u32 trcpdcr; 866 }; 867 868 /** 869 * struct etm4_drvdata - specifics associated to an ETM component 870 * @base: Memory mapped base address for this component. 871 * @csdev: Component vitals needed by the framework. 872 * @spinlock: Only one at a time pls. 873 * @mode: This tracer's mode, i.e sysFS, Perf or disabled. 874 * @cpu: The cpu this component is affined to. 875 * @arch: ETM architecture version. 876 * @nr_pe: The number of processing entity available for tracing. 877 * @nr_pe_cmp: The number of processing entity comparator inputs that are 878 * available for tracing. 879 * @nr_addr_cmp:Number of pairs of address comparators available 880 * as found in ETMIDR4 0-3. 881 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. 882 * @nr_ext_inp: Number of external input. 883 * @numcidc: Number of contextID comparators. 884 * @numvmidc: Number of VMID comparators. 885 * @nrseqstate: The number of sequencer states that are implemented. 886 * @nr_event: Indicates how many events the trace unit support. 887 * @nr_resource:The number of resource selection pairs available for tracing. 888 * @nr_ss_cmp: Number of single-shot comparator controls that are available. 889 * @trcid: value of the current ID for this component. 890 * @trcid_size: Indicates the trace ID width. 891 * @ts_size: Global timestamp size field. 892 * @ctxid_size: Size of the context ID field to consider. 893 * @vmid_size: Size of the VM ID comparator to consider. 894 * @ccsize: Indicates the size of the cycle counter in bits. 895 * @ccitmin: minimum value that can be programmed in 896 * @s_ex_level: In secure state, indicates whether instruction tracing is 897 * supported for the corresponding Exception level. 898 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is 899 * supported for the corresponding Exception level. 900 * @sticky_enable: true if ETM base configuration has been done. 901 * @boot_enable:True if we should start tracing at boot time. 902 * @os_unlock: True if access to management registers is allowed. 903 * @instrp0: Tracing of load and store instructions 904 * as P0 elements is supported. 905 * @trcbb: Indicates if the trace unit supports branch broadcast tracing. 906 * @trccond: If the trace unit supports conditional 907 * instruction tracing. 908 * @retstack: Indicates if the implementation supports a return stack. 909 * @trccci: Indicates if the trace unit supports cycle counting 910 * for instruction. 911 * @q_support: Q element support characteristics. 912 * @trc_error: Whether a trace unit can trace a system 913 * error exception. 914 * @syncpr: Indicates if an implementation has a fixed 915 * synchronization period. 916 * @stall_ctrl: Enables trace unit functionality that prevents trace 917 * unit buffer overflows. 918 * @sysstall: Does the system support stall control of the PE? 919 * @nooverflow: Indicate if overflow prevention is supported. 920 * @atbtrig: If the implementation can support ATB triggers 921 * @lpoverride: If the implementation can support low-power state over. 922 * @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that 923 * allows tracing at all ELs. We don't want to compute this 924 * at runtime, due to the additional setting of TRFCR_CX when 925 * in EL2. Otherwise, 0. 926 * @config: structure holding configuration parameters. 927 * @save_trfcr: Saved TRFCR_EL1 register during a CPU PM event. 928 * @save_state: State to be preserved across power loss 929 * @state_needs_restore: True when there is context to restore after PM exit 930 * @skip_power_up: Indicates if an implementation can skip powering up 931 * the trace unit. 932 * @arch_features: Bitmap of arch features of etmv4 devices. 933 */ 934 struct etmv4_drvdata { 935 void __iomem *base; 936 struct coresight_device *csdev; 937 spinlock_t spinlock; 938 local_t mode; 939 int cpu; 940 u8 arch; 941 u8 nr_pe; 942 u8 nr_pe_cmp; 943 u8 nr_addr_cmp; 944 u8 nr_cntr; 945 u8 nr_ext_inp; 946 u8 numcidc; 947 u8 numvmidc; 948 u8 nrseqstate; 949 u8 nr_event; 950 u8 nr_resource; 951 u8 nr_ss_cmp; 952 u8 trcid; 953 u8 trcid_size; 954 u8 ts_size; 955 u8 ctxid_size; 956 u8 vmid_size; 957 u8 ccsize; 958 u8 ccitmin; 959 u8 s_ex_level; 960 u8 ns_ex_level; 961 u8 q_support; 962 u8 os_lock_model; 963 bool sticky_enable; 964 bool boot_enable; 965 bool os_unlock; 966 bool instrp0; 967 bool trcbb; 968 bool trccond; 969 bool retstack; 970 bool trccci; 971 bool trc_error; 972 bool syncpr; 973 bool stallctl; 974 bool sysstall; 975 bool nooverflow; 976 bool atbtrig; 977 bool lpoverride; 978 u64 trfcr; 979 struct etmv4_config config; 980 u64 save_trfcr; 981 struct etmv4_save_state *save_state; 982 bool state_needs_restore; 983 bool skip_power_up; 984 DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); 985 }; 986 987 /* Address comparator access types */ 988 enum etm_addr_acctype { 989 ETM_INSTR_ADDR, 990 ETM_DATA_LOAD_ADDR, 991 ETM_DATA_STORE_ADDR, 992 ETM_DATA_LOAD_STORE_ADDR, 993 }; 994 995 /* Address comparator context types */ 996 enum etm_addr_ctxtype { 997 ETM_CTX_NONE, 998 ETM_CTX_CTXID, 999 ETM_CTX_VMID, 1000 ETM_CTX_CTXID_VMID, 1001 }; 1002 1003 extern const struct attribute_group *coresight_etmv4_groups[]; 1004 void etm4_config_trace_mode(struct etmv4_config *config); 1005 1006 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); 1007 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit); 1008 1009 static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) 1010 { 1011 return drvdata->arch >= ETM_ARCH_ETE; 1012 } 1013 #endif 1014