1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 4 * 5 * Description: CoreSight Program Flow Trace driver 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/moduleparam.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/err.h> 15 #include <linux/fs.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/smp.h> 19 #include <linux/sysfs.h> 20 #include <linux/stat.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/cpu.h> 23 #include <linux/of.h> 24 #include <linux/coresight.h> 25 #include <linux/coresight-pmu.h> 26 #include <linux/amba/bus.h> 27 #include <linux/seq_file.h> 28 #include <linux/uaccess.h> 29 #include <linux/clk.h> 30 #include <linux/perf_event.h> 31 #include <asm/sections.h> 32 33 #include "coresight-etm.h" 34 #include "coresight-etm-perf.h" 35 #include "coresight-trace-id.h" 36 37 /* 38 * Not really modular but using module_param is the easiest way to 39 * remain consistent with existing use cases for now. 40 */ 41 static int boot_enable; 42 module_param_named(boot_enable, boot_enable, int, S_IRUGO); 43 44 static struct etm_drvdata *etmdrvdata[NR_CPUS]; 45 46 static enum cpuhp_state hp_online; 47 48 /* 49 * Memory mapped writes to clear os lock are not supported on some processors 50 * and OS lock must be unlocked before any memory mapped access on such 51 * processors, otherwise memory mapped reads/writes will be invalid. 52 */ 53 static void etm_os_unlock(struct etm_drvdata *drvdata) 54 { 55 /* Writing any value to ETMOSLAR unlocks the trace registers */ 56 etm_writel(drvdata, 0x0, ETMOSLAR); 57 drvdata->os_unlock = true; 58 isb(); 59 } 60 61 static void etm_set_pwrdwn(struct etm_drvdata *drvdata) 62 { 63 u32 etmcr; 64 65 /* Ensure pending cp14 accesses complete before setting pwrdwn */ 66 mb(); 67 isb(); 68 etmcr = etm_readl(drvdata, ETMCR); 69 etmcr |= ETMCR_PWD_DWN; 70 etm_writel(drvdata, etmcr, ETMCR); 71 } 72 73 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata) 74 { 75 u32 etmcr; 76 77 etmcr = etm_readl(drvdata, ETMCR); 78 etmcr &= ~ETMCR_PWD_DWN; 79 etm_writel(drvdata, etmcr, ETMCR); 80 /* Ensure pwrup completes before subsequent cp14 accesses */ 81 mb(); 82 isb(); 83 } 84 85 static void etm_set_pwrup(struct etm_drvdata *drvdata) 86 { 87 u32 etmpdcr; 88 89 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR); 90 etmpdcr |= ETMPDCR_PWD_UP; 91 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR); 92 /* Ensure pwrup completes before subsequent cp14 accesses */ 93 mb(); 94 isb(); 95 } 96 97 static void etm_clr_pwrup(struct etm_drvdata *drvdata) 98 { 99 u32 etmpdcr; 100 101 /* Ensure pending cp14 accesses complete before clearing pwrup */ 102 mb(); 103 isb(); 104 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR); 105 etmpdcr &= ~ETMPDCR_PWD_UP; 106 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR); 107 } 108 109 /** 110 * coresight_timeout_etm - loop until a bit has changed to a specific state. 111 * @drvdata: etm's private data structure. 112 * @offset: address of a register, starting from @addr. 113 * @position: the position of the bit of interest. 114 * @value: the value the bit should have. 115 * 116 * Basically the same as @coresight_timeout except for the register access 117 * method where we have to account for CP14 configurations. 118 * 119 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if 120 * TIMEOUT_US has elapsed, which ever happens first. 121 */ 122 123 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset, 124 int position, int value) 125 { 126 int i; 127 u32 val; 128 129 for (i = TIMEOUT_US; i > 0; i--) { 130 val = etm_readl(drvdata, offset); 131 /* Waiting on the bit to go from 0 to 1 */ 132 if (value) { 133 if (val & BIT(position)) 134 return 0; 135 /* Waiting on the bit to go from 1 to 0 */ 136 } else { 137 if (!(val & BIT(position))) 138 return 0; 139 } 140 141 /* 142 * Delay is arbitrary - the specification doesn't say how long 143 * we are expected to wait. Extra check required to make sure 144 * we don't wait needlessly on the last iteration. 145 */ 146 if (i - 1) 147 udelay(1); 148 } 149 150 return -EAGAIN; 151 } 152 153 154 static void etm_set_prog(struct etm_drvdata *drvdata) 155 { 156 u32 etmcr; 157 158 etmcr = etm_readl(drvdata, ETMCR); 159 etmcr |= ETMCR_ETM_PRG; 160 etm_writel(drvdata, etmcr, ETMCR); 161 /* 162 * Recommended by spec for cp14 accesses to ensure etmcr write is 163 * complete before polling etmsr 164 */ 165 isb(); 166 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) { 167 dev_err(&drvdata->csdev->dev, 168 "%s: timeout observed when probing at offset %#x\n", 169 __func__, ETMSR); 170 } 171 } 172 173 static void etm_clr_prog(struct etm_drvdata *drvdata) 174 { 175 u32 etmcr; 176 177 etmcr = etm_readl(drvdata, ETMCR); 178 etmcr &= ~ETMCR_ETM_PRG; 179 etm_writel(drvdata, etmcr, ETMCR); 180 /* 181 * Recommended by spec for cp14 accesses to ensure etmcr write is 182 * complete before polling etmsr 183 */ 184 isb(); 185 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) { 186 dev_err(&drvdata->csdev->dev, 187 "%s: timeout observed when probing at offset %#x\n", 188 __func__, ETMSR); 189 } 190 } 191 192 void etm_set_default(struct etm_config *config) 193 { 194 int i; 195 196 if (WARN_ON_ONCE(!config)) 197 return; 198 199 /* 200 * Taken verbatim from the TRM: 201 * 202 * To trace all memory: 203 * set bit [24] in register 0x009, the ETMTECR1, to 1 204 * set all other bits in register 0x009, the ETMTECR1, to 0 205 * set all bits in register 0x007, the ETMTECR2, to 0 206 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). 207 */ 208 config->enable_ctrl1 = ETMTECR1_INC_EXC; 209 config->enable_ctrl2 = 0x0; 210 config->enable_event = ETM_HARD_WIRE_RES_A; 211 212 config->trigger_event = ETM_DEFAULT_EVENT_VAL; 213 config->enable_event = ETM_HARD_WIRE_RES_A; 214 215 config->seq_12_event = ETM_DEFAULT_EVENT_VAL; 216 config->seq_21_event = ETM_DEFAULT_EVENT_VAL; 217 config->seq_23_event = ETM_DEFAULT_EVENT_VAL; 218 config->seq_31_event = ETM_DEFAULT_EVENT_VAL; 219 config->seq_32_event = ETM_DEFAULT_EVENT_VAL; 220 config->seq_13_event = ETM_DEFAULT_EVENT_VAL; 221 config->timestamp_event = ETM_DEFAULT_EVENT_VAL; 222 223 for (i = 0; i < ETM_MAX_CNTR; i++) { 224 config->cntr_rld_val[i] = 0x0; 225 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL; 226 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL; 227 config->cntr_val[i] = 0x0; 228 } 229 230 config->seq_curr_state = 0x0; 231 config->ctxid_idx = 0x0; 232 for (i = 0; i < ETM_MAX_CTXID_CMP; i++) 233 config->ctxid_pid[i] = 0x0; 234 235 config->ctxid_mask = 0x0; 236 /* Setting default to 1024 as per TRM recommendation */ 237 config->sync_freq = 0x400; 238 } 239 240 void etm_config_trace_mode(struct etm_config *config) 241 { 242 u32 flags, mode; 243 244 mode = config->mode; 245 246 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER); 247 248 /* excluding kernel AND user space doesn't make sense */ 249 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)) 250 return; 251 252 /* nothing to do if neither flags are set */ 253 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) 254 return; 255 256 flags = (1 << 0 | /* instruction execute */ 257 3 << 3 | /* ARM instruction */ 258 0 << 5 | /* No data value comparison */ 259 0 << 7 | /* No exact mach */ 260 0 << 8); /* Ignore context ID */ 261 262 /* No need to worry about single address comparators. */ 263 config->enable_ctrl2 = 0x0; 264 265 /* Bit 0 is address range comparator 1 */ 266 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1; 267 268 /* 269 * On ETMv3.5: 270 * ETMACTRn[13,11] == Non-secure state comparison control 271 * ETMACTRn[12,10] == Secure state comparison control 272 * 273 * b00 == Match in all modes in this state 274 * b01 == Do not match in any more in this state 275 * b10 == Match in all modes excepts user mode in this state 276 * b11 == Match only in user mode in this state 277 */ 278 279 /* Tracing in secure mode is not supported at this time */ 280 flags |= (0 << 12 | 1 << 10); 281 282 if (mode & ETM_MODE_EXCL_USER) { 283 /* exclude user, match all modes except user mode */ 284 flags |= (1 << 13 | 0 << 11); 285 } else { 286 /* exclude kernel, match only in user mode */ 287 flags |= (1 << 13 | 1 << 11); 288 } 289 290 /* 291 * The ETMEEVR register is already set to "hard wire A". As such 292 * all there is to do is setup an address comparator that spans 293 * the entire address range and configure the state and mode bits. 294 */ 295 config->addr_val[0] = (u32) 0x0; 296 config->addr_val[1] = (u32) ~0x0; 297 config->addr_acctype[0] = flags; 298 config->addr_acctype[1] = flags; 299 config->addr_type[0] = ETM_ADDR_TYPE_RANGE; 300 config->addr_type[1] = ETM_ADDR_TYPE_RANGE; 301 } 302 303 #define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | \ 304 ETMCR_TIMESTAMP_EN | \ 305 ETMCR_RETURN_STACK) 306 307 static int etm_parse_event_config(struct etm_drvdata *drvdata, 308 struct perf_event *event) 309 { 310 struct etm_config *config = &drvdata->config; 311 struct perf_event_attr *attr = &event->attr; 312 313 if (!attr) 314 return -EINVAL; 315 316 /* Clear configuration from previous run */ 317 memset(config, 0, sizeof(struct etm_config)); 318 319 if (attr->exclude_kernel) 320 config->mode = ETM_MODE_EXCL_KERN; 321 322 if (attr->exclude_user) 323 config->mode = ETM_MODE_EXCL_USER; 324 325 /* Always start from the default config */ 326 etm_set_default(config); 327 328 /* 329 * By default the tracers are configured to trace the whole address 330 * range. Narrow the field only if requested by user space. 331 */ 332 if (config->mode) 333 etm_config_trace_mode(config); 334 335 /* 336 * At this time only cycle accurate, return stack and timestamp 337 * options are available. 338 */ 339 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS) 340 return -EINVAL; 341 342 config->ctrl = attr->config; 343 344 /* Don't trace contextID when runs in non-root PID namespace */ 345 if (!task_is_in_init_pid_ns(current)) 346 config->ctrl &= ~ETMCR_CTXID_SIZE; 347 348 /* 349 * Possible to have cores with PTM (supports ret stack) and ETM 350 * (never has ret stack) on the same SoC. So if we have a request 351 * for return stack that can't be honoured on this core then 352 * clear the bit - trace will still continue normally 353 */ 354 if ((config->ctrl & ETMCR_RETURN_STACK) && 355 !(drvdata->etmccer & ETMCCER_RETSTACK)) 356 config->ctrl &= ~ETMCR_RETURN_STACK; 357 358 return 0; 359 } 360 361 static int etm_enable_hw(struct etm_drvdata *drvdata) 362 { 363 int i, rc; 364 u32 etmcr; 365 struct etm_config *config = &drvdata->config; 366 struct coresight_device *csdev = drvdata->csdev; 367 368 CS_UNLOCK(drvdata->base); 369 370 rc = coresight_claim_device_unlocked(csdev); 371 if (rc) 372 goto done; 373 374 /* Turn engine on */ 375 etm_clr_pwrdwn(drvdata); 376 /* Apply power to trace registers */ 377 etm_set_pwrup(drvdata); 378 /* Make sure all registers are accessible */ 379 etm_os_unlock(drvdata); 380 381 etm_set_prog(drvdata); 382 383 etmcr = etm_readl(drvdata, ETMCR); 384 /* Clear setting from a previous run if need be */ 385 etmcr &= ~ETM3X_SUPPORTED_OPTIONS; 386 etmcr |= drvdata->port_size; 387 etmcr |= ETMCR_ETM_EN; 388 etm_writel(drvdata, config->ctrl | etmcr, ETMCR); 389 etm_writel(drvdata, config->trigger_event, ETMTRIGGER); 390 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR); 391 etm_writel(drvdata, config->enable_event, ETMTEEVR); 392 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1); 393 etm_writel(drvdata, config->fifofull_level, ETMFFLR); 394 for (i = 0; i < drvdata->nr_addr_cmp; i++) { 395 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i)); 396 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i)); 397 } 398 for (i = 0; i < drvdata->nr_cntr; i++) { 399 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i)); 400 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i)); 401 etm_writel(drvdata, config->cntr_rld_event[i], 402 ETMCNTRLDEVRn(i)); 403 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i)); 404 } 405 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR); 406 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR); 407 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR); 408 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR); 409 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR); 410 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR); 411 etm_writel(drvdata, config->seq_curr_state, ETMSQR); 412 for (i = 0; i < drvdata->nr_ext_out; i++) 413 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i)); 414 for (i = 0; i < drvdata->nr_ctxid_cmp; i++) 415 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i)); 416 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR); 417 etm_writel(drvdata, config->sync_freq, ETMSYNCFR); 418 /* No external input selected */ 419 etm_writel(drvdata, 0x0, ETMEXTINSELR); 420 etm_writel(drvdata, config->timestamp_event, ETMTSEVR); 421 /* No auxiliary control selected */ 422 etm_writel(drvdata, 0x0, ETMAUXCR); 423 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR); 424 /* No VMID comparator value selected */ 425 etm_writel(drvdata, 0x0, ETMVMIDCVR); 426 427 etm_clr_prog(drvdata); 428 429 done: 430 CS_LOCK(drvdata->base); 431 432 dev_dbg(&drvdata->csdev->dev, "cpu: %d enable smp call done: %d\n", 433 drvdata->cpu, rc); 434 return rc; 435 } 436 437 struct etm_enable_arg { 438 struct etm_drvdata *drvdata; 439 int rc; 440 }; 441 442 static void etm_enable_hw_smp_call(void *info) 443 { 444 struct etm_enable_arg *arg = info; 445 446 if (WARN_ON(!arg)) 447 return; 448 arg->rc = etm_enable_hw(arg->drvdata); 449 } 450 451 static int etm_cpu_id(struct coresight_device *csdev) 452 { 453 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 454 455 return drvdata->cpu; 456 } 457 458 void etm_release_trace_id(struct etm_drvdata *drvdata) 459 { 460 coresight_trace_id_put_cpu_id(drvdata->cpu); 461 } 462 463 static int etm_enable_perf(struct coresight_device *csdev, 464 struct perf_event *event, 465 struct coresight_path *path) 466 { 467 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 468 469 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) 470 return -EINVAL; 471 472 /* Configure the tracer based on the session's specifics */ 473 etm_parse_event_config(drvdata, event); 474 drvdata->traceid = path->trace_id; 475 476 /* And enable it */ 477 return etm_enable_hw(drvdata); 478 } 479 480 static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path) 481 { 482 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 483 struct etm_enable_arg arg = { }; 484 int ret; 485 486 spin_lock(&drvdata->spinlock); 487 488 drvdata->traceid = path->trace_id; 489 490 /* 491 * Configure the ETM only if the CPU is online. If it isn't online 492 * hw configuration will take place on the local CPU during bring up. 493 */ 494 if (cpu_online(drvdata->cpu)) { 495 arg.drvdata = drvdata; 496 ret = smp_call_function_single(drvdata->cpu, 497 etm_enable_hw_smp_call, &arg, 1); 498 if (!ret) 499 ret = arg.rc; 500 if (!ret) 501 drvdata->sticky_enable = true; 502 } else { 503 ret = -ENODEV; 504 } 505 506 if (ret) 507 etm_release_trace_id(drvdata); 508 509 spin_unlock(&drvdata->spinlock); 510 511 if (!ret) 512 dev_dbg(&csdev->dev, "ETM tracing enabled\n"); 513 return ret; 514 } 515 516 static int etm_enable(struct coresight_device *csdev, struct perf_event *event, 517 enum cs_mode mode, struct coresight_path *path) 518 { 519 int ret; 520 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 521 522 if (!coresight_take_mode(csdev, mode)) { 523 /* Someone is already using the tracer */ 524 return -EBUSY; 525 } 526 527 switch (mode) { 528 case CS_MODE_SYSFS: 529 ret = etm_enable_sysfs(csdev, path); 530 break; 531 case CS_MODE_PERF: 532 ret = etm_enable_perf(csdev, event, path); 533 break; 534 default: 535 ret = -EINVAL; 536 } 537 538 /* The tracer didn't start */ 539 if (ret) 540 coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); 541 542 return ret; 543 } 544 545 static void etm_disable_hw(void *info) 546 { 547 int i; 548 struct etm_drvdata *drvdata = info; 549 struct etm_config *config = &drvdata->config; 550 struct coresight_device *csdev = drvdata->csdev; 551 552 CS_UNLOCK(drvdata->base); 553 etm_set_prog(drvdata); 554 555 /* Read back sequencer and counters for post trace analysis */ 556 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK); 557 558 for (i = 0; i < drvdata->nr_cntr; i++) 559 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i)); 560 561 etm_set_pwrdwn(drvdata); 562 coresight_disclaim_device_unlocked(csdev); 563 564 CS_LOCK(drvdata->base); 565 566 dev_dbg(&drvdata->csdev->dev, 567 "cpu: %d disable smp call done\n", drvdata->cpu); 568 } 569 570 static void etm_disable_perf(struct coresight_device *csdev) 571 { 572 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 573 574 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) 575 return; 576 577 CS_UNLOCK(drvdata->base); 578 579 /* Setting the prog bit disables tracing immediately */ 580 etm_set_prog(drvdata); 581 582 /* 583 * There is no way to know when the tracer will be used again so 584 * power down the tracer. 585 */ 586 etm_set_pwrdwn(drvdata); 587 coresight_disclaim_device_unlocked(csdev); 588 589 CS_LOCK(drvdata->base); 590 591 /* 592 * perf will release trace ids when _free_aux() 593 * is called at the end of the session 594 */ 595 596 } 597 598 static void etm_disable_sysfs(struct coresight_device *csdev) 599 { 600 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 601 602 /* 603 * Taking hotplug lock here protects from clocks getting disabled 604 * with tracing being left on (crash scenario) if user disable occurs 605 * after cpu online mask indicates the cpu is offline but before the 606 * DYING hotplug callback is serviced by the ETM driver. 607 */ 608 cpus_read_lock(); 609 spin_lock(&drvdata->spinlock); 610 611 /* 612 * Executing etm_disable_hw on the cpu whose ETM is being disabled 613 * ensures that register writes occur when cpu is powered. 614 */ 615 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1); 616 617 spin_unlock(&drvdata->spinlock); 618 cpus_read_unlock(); 619 620 /* 621 * we only release trace IDs when resetting sysfs. 622 * This permits sysfs users to read the trace ID after the trace 623 * session has completed. This maintains operational behaviour with 624 * prior trace id allocation method 625 */ 626 627 dev_dbg(&csdev->dev, "ETM tracing disabled\n"); 628 } 629 630 static void etm_disable(struct coresight_device *csdev, 631 struct perf_event *event) 632 { 633 enum cs_mode mode; 634 635 /* 636 * For as long as the tracer isn't disabled another entity can't 637 * change its status. As such we can read the status here without 638 * fearing it will change under us. 639 */ 640 mode = coresight_get_mode(csdev); 641 642 switch (mode) { 643 case CS_MODE_DISABLED: 644 break; 645 case CS_MODE_SYSFS: 646 etm_disable_sysfs(csdev); 647 break; 648 case CS_MODE_PERF: 649 etm_disable_perf(csdev); 650 break; 651 default: 652 WARN_ON_ONCE(mode); 653 return; 654 } 655 656 if (mode) 657 coresight_set_mode(csdev, CS_MODE_DISABLED); 658 } 659 660 static const struct coresight_ops_source etm_source_ops = { 661 .cpu_id = etm_cpu_id, 662 .enable = etm_enable, 663 .disable = etm_disable, 664 }; 665 666 static const struct coresight_ops etm_cs_ops = { 667 .trace_id = coresight_etm_get_trace_id, 668 .source_ops = &etm_source_ops, 669 }; 670 671 static int etm_online_cpu(unsigned int cpu) 672 { 673 if (!etmdrvdata[cpu]) 674 return 0; 675 676 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) 677 coresight_enable_sysfs(etmdrvdata[cpu]->csdev); 678 return 0; 679 } 680 681 static int etm_starting_cpu(unsigned int cpu) 682 { 683 if (!etmdrvdata[cpu]) 684 return 0; 685 686 spin_lock(&etmdrvdata[cpu]->spinlock); 687 if (!etmdrvdata[cpu]->os_unlock) { 688 etm_os_unlock(etmdrvdata[cpu]); 689 etmdrvdata[cpu]->os_unlock = true; 690 } 691 692 if (coresight_get_mode(etmdrvdata[cpu]->csdev)) 693 etm_enable_hw(etmdrvdata[cpu]); 694 spin_unlock(&etmdrvdata[cpu]->spinlock); 695 return 0; 696 } 697 698 static int etm_dying_cpu(unsigned int cpu) 699 { 700 if (!etmdrvdata[cpu]) 701 return 0; 702 703 spin_lock(&etmdrvdata[cpu]->spinlock); 704 if (coresight_get_mode(etmdrvdata[cpu]->csdev)) 705 etm_disable_hw(etmdrvdata[cpu]); 706 spin_unlock(&etmdrvdata[cpu]->spinlock); 707 return 0; 708 } 709 710 static bool etm_arch_supported(u8 arch) 711 { 712 switch (arch) { 713 case ETM_ARCH_V3_3: 714 break; 715 case ETM_ARCH_V3_5: 716 break; 717 case PFT_ARCH_V1_0: 718 break; 719 case PFT_ARCH_V1_1: 720 break; 721 default: 722 return false; 723 } 724 return true; 725 } 726 727 static void etm_init_arch_data(void *info) 728 { 729 u32 etmidr; 730 u32 etmccr; 731 struct etm_drvdata *drvdata = info; 732 733 /* Make sure all registers are accessible */ 734 etm_os_unlock(drvdata); 735 736 CS_UNLOCK(drvdata->base); 737 738 /* First dummy read */ 739 (void)etm_readl(drvdata, ETMPDSR); 740 /* Provide power to ETM: ETMPDCR[3] == 1 */ 741 etm_set_pwrup(drvdata); 742 /* 743 * Clear power down bit since when this bit is set writes to 744 * certain registers might be ignored. 745 */ 746 etm_clr_pwrdwn(drvdata); 747 /* 748 * Set prog bit. It will be set from reset but this is included to 749 * ensure it is set 750 */ 751 etm_set_prog(drvdata); 752 753 /* Find all capabilities */ 754 etmidr = etm_readl(drvdata, ETMIDR); 755 drvdata->arch = BMVAL(etmidr, 4, 11); 756 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK; 757 758 drvdata->etmccer = etm_readl(drvdata, ETMCCER); 759 etmccr = etm_readl(drvdata, ETMCCR); 760 drvdata->etmccr = etmccr; 761 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2; 762 drvdata->nr_cntr = BMVAL(etmccr, 13, 15); 763 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19); 764 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22); 765 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25); 766 767 etm_set_pwrdwn(drvdata); 768 etm_clr_pwrup(drvdata); 769 CS_LOCK(drvdata->base); 770 } 771 772 static int __init etm_hp_setup(void) 773 { 774 int ret; 775 776 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING, 777 "arm/coresight:starting", 778 etm_starting_cpu, etm_dying_cpu); 779 780 if (ret) 781 return ret; 782 783 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, 784 "arm/coresight:online", 785 etm_online_cpu, NULL); 786 787 /* HP dyn state ID returned in ret on success */ 788 if (ret > 0) { 789 hp_online = ret; 790 return 0; 791 } 792 793 /* failed dyn state - remove others */ 794 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); 795 796 return ret; 797 } 798 799 static void etm_hp_clear(void) 800 { 801 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); 802 if (hp_online) { 803 cpuhp_remove_state_nocalls(hp_online); 804 hp_online = 0; 805 } 806 } 807 808 static int etm_probe(struct amba_device *adev, const struct amba_id *id) 809 { 810 int ret; 811 void __iomem *base; 812 struct device *dev = &adev->dev; 813 struct coresight_platform_data *pdata = NULL; 814 struct etm_drvdata *drvdata; 815 struct resource *res = &adev->res; 816 struct coresight_desc desc = { 0 }; 817 818 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 819 if (!drvdata) 820 return -ENOMEM; 821 822 drvdata->use_cp14 = fwnode_property_read_bool(dev->fwnode, "arm,cp14"); 823 dev_set_drvdata(dev, drvdata); 824 825 /* Validity for the resource is already checked by the AMBA core */ 826 base = devm_ioremap_resource(dev, res); 827 if (IS_ERR(base)) 828 return PTR_ERR(base); 829 830 drvdata->base = base; 831 desc.access = CSDEV_ACCESS_IOMEM(base); 832 833 spin_lock_init(&drvdata->spinlock); 834 835 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 836 if (!IS_ERR(drvdata->atclk)) { 837 ret = clk_prepare_enable(drvdata->atclk); 838 if (ret) 839 return ret; 840 } 841 842 drvdata->cpu = coresight_get_cpu(dev); 843 if (drvdata->cpu < 0) 844 return drvdata->cpu; 845 846 desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu); 847 if (!desc.name) 848 return -ENOMEM; 849 850 if (smp_call_function_single(drvdata->cpu, 851 etm_init_arch_data, drvdata, 1)) 852 dev_err(dev, "ETM arch init failed\n"); 853 854 if (etm_arch_supported(drvdata->arch) == false) 855 return -EINVAL; 856 857 etm_set_default(&drvdata->config); 858 859 pdata = coresight_get_platform_data(dev); 860 if (IS_ERR(pdata)) 861 return PTR_ERR(pdata); 862 863 adev->dev.platform_data = pdata; 864 865 desc.type = CORESIGHT_DEV_TYPE_SOURCE; 866 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; 867 desc.ops = &etm_cs_ops; 868 desc.pdata = pdata; 869 desc.dev = dev; 870 desc.groups = coresight_etm_groups; 871 drvdata->csdev = coresight_register(&desc); 872 if (IS_ERR(drvdata->csdev)) 873 return PTR_ERR(drvdata->csdev); 874 875 ret = etm_perf_symlink(drvdata->csdev, true); 876 if (ret) { 877 coresight_unregister(drvdata->csdev); 878 return ret; 879 } 880 881 etmdrvdata[drvdata->cpu] = drvdata; 882 883 pm_runtime_put(&adev->dev); 884 dev_info(&drvdata->csdev->dev, 885 "%s initialized\n", (char *)coresight_get_uci_data(id)); 886 if (boot_enable) { 887 coresight_enable_sysfs(drvdata->csdev); 888 drvdata->boot_enable = true; 889 } 890 891 return 0; 892 } 893 894 static void clear_etmdrvdata(void *info) 895 { 896 int cpu = *(int *)info; 897 898 etmdrvdata[cpu] = NULL; 899 } 900 901 static void etm_remove(struct amba_device *adev) 902 { 903 struct etm_drvdata *drvdata = dev_get_drvdata(&adev->dev); 904 905 etm_perf_symlink(drvdata->csdev, false); 906 907 /* 908 * Taking hotplug lock here to avoid racing between etm_remove and 909 * CPU hotplug call backs. 910 */ 911 cpus_read_lock(); 912 /* 913 * The readers for etmdrvdata[] are CPU hotplug call backs 914 * and PM notification call backs. Change etmdrvdata[i] on 915 * CPU i ensures these call backs has consistent view 916 * inside one call back function. 917 */ 918 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) 919 etmdrvdata[drvdata->cpu] = NULL; 920 921 cpus_read_unlock(); 922 923 coresight_unregister(drvdata->csdev); 924 } 925 926 #ifdef CONFIG_PM 927 static int etm_runtime_suspend(struct device *dev) 928 { 929 struct etm_drvdata *drvdata = dev_get_drvdata(dev); 930 931 if (drvdata && !IS_ERR(drvdata->atclk)) 932 clk_disable_unprepare(drvdata->atclk); 933 934 return 0; 935 } 936 937 static int etm_runtime_resume(struct device *dev) 938 { 939 struct etm_drvdata *drvdata = dev_get_drvdata(dev); 940 941 if (drvdata && !IS_ERR(drvdata->atclk)) 942 clk_prepare_enable(drvdata->atclk); 943 944 return 0; 945 } 946 #endif 947 948 static const struct dev_pm_ops etm_dev_pm_ops = { 949 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL) 950 }; 951 952 static const struct amba_id etm_ids[] = { 953 /* ETM 3.3 */ 954 CS_AMBA_ID_DATA(0x000bb921, "ETM 3.3"), 955 /* ETM 3.5 - Cortex-A5 */ 956 CS_AMBA_ID_DATA(0x000bb955, "ETM 3.5"), 957 /* ETM 3.5 */ 958 CS_AMBA_ID_DATA(0x000bb956, "ETM 3.5"), 959 /* PTM 1.0 */ 960 CS_AMBA_ID_DATA(0x000bb950, "PTM 1.0"), 961 /* PTM 1.1 */ 962 CS_AMBA_ID_DATA(0x000bb95f, "PTM 1.1"), 963 /* PTM 1.1 Qualcomm */ 964 CS_AMBA_ID_DATA(0x000b006f, "PTM 1.1"), 965 { 0, 0, NULL}, 966 }; 967 968 MODULE_DEVICE_TABLE(amba, etm_ids); 969 970 static struct amba_driver etm_driver = { 971 .drv = { 972 .name = "coresight-etm3x", 973 .pm = &etm_dev_pm_ops, 974 .suppress_bind_attrs = true, 975 }, 976 .probe = etm_probe, 977 .remove = etm_remove, 978 .id_table = etm_ids, 979 }; 980 981 static int __init etm_init(void) 982 { 983 int ret; 984 985 ret = etm_hp_setup(); 986 987 /* etm_hp_setup() does its own cleanup - exit on error */ 988 if (ret) 989 return ret; 990 991 ret = amba_driver_register(&etm_driver); 992 if (ret) { 993 pr_err("Error registering etm3x driver\n"); 994 etm_hp_clear(); 995 } 996 997 return ret; 998 } 999 1000 static void __exit etm_exit(void) 1001 { 1002 amba_driver_unregister(&etm_driver); 1003 etm_hp_clear(); 1004 } 1005 1006 module_init(etm_init); 1007 module_exit(etm_exit); 1008 1009 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>"); 1010 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>"); 1011 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace driver"); 1012 MODULE_LICENSE("GPL v2"); 1013