1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _CORESIGHT_CORESIGHT_ETM_H 14 #define _CORESIGHT_CORESIGHT_ETM_H 15 16 #include <asm/local.h> 17 #include <linux/spinlock.h> 18 #include "coresight-priv.h" 19 20 /* 21 * Device registers: 22 * 0x000 - 0x2FC: Trace registers 23 * 0x300 - 0x314: Management registers 24 * 0x318 - 0xEFC: Trace registers 25 * 26 * Coresight registers 27 * 0xF00 - 0xF9C: Management registers 28 * 0xFA0 - 0xFA4: Management registers in PFTv1.0 29 * Trace registers in PFTv1.1 30 * 0xFA8 - 0xFFC: Management registers 31 */ 32 33 /* Trace registers (0x000-0x2FC) */ 34 #define ETMCR 0x000 35 #define ETMCCR 0x004 36 #define ETMTRIGGER 0x008 37 #define ETMSR 0x010 38 #define ETMSCR 0x014 39 #define ETMTSSCR 0x018 40 #define ETMTECR2 0x01c 41 #define ETMTEEVR 0x020 42 #define ETMTECR1 0x024 43 #define ETMFFLR 0x02c 44 #define ETMACVRn(n) (0x040 + (n * 4)) 45 #define ETMACTRn(n) (0x080 + (n * 4)) 46 #define ETMCNTRLDVRn(n) (0x140 + (n * 4)) 47 #define ETMCNTENRn(n) (0x150 + (n * 4)) 48 #define ETMCNTRLDEVRn(n) (0x160 + (n * 4)) 49 #define ETMCNTVRn(n) (0x170 + (n * 4)) 50 #define ETMSQ12EVR 0x180 51 #define ETMSQ21EVR 0x184 52 #define ETMSQ23EVR 0x188 53 #define ETMSQ31EVR 0x18c 54 #define ETMSQ32EVR 0x190 55 #define ETMSQ13EVR 0x194 56 #define ETMSQR 0x19c 57 #define ETMEXTOUTEVRn(n) (0x1a0 + (n * 4)) 58 #define ETMCIDCVRn(n) (0x1b0 + (n * 4)) 59 #define ETMCIDCMR 0x1bc 60 #define ETMIMPSPEC0 0x1c0 61 #define ETMIMPSPEC1 0x1c4 62 #define ETMIMPSPEC2 0x1c8 63 #define ETMIMPSPEC3 0x1cc 64 #define ETMIMPSPEC4 0x1d0 65 #define ETMIMPSPEC5 0x1d4 66 #define ETMIMPSPEC6 0x1d8 67 #define ETMIMPSPEC7 0x1dc 68 #define ETMSYNCFR 0x1e0 69 #define ETMIDR 0x1e4 70 #define ETMCCER 0x1e8 71 #define ETMEXTINSELR 0x1ec 72 #define ETMTESSEICR 0x1f0 73 #define ETMEIBCR 0x1f4 74 #define ETMTSEVR 0x1f8 75 #define ETMAUXCR 0x1fc 76 #define ETMTRACEIDR 0x200 77 #define ETMVMIDCVR 0x240 78 /* Management registers (0x300-0x314) */ 79 #define ETMOSLAR 0x300 80 #define ETMOSLSR 0x304 81 #define ETMOSSRR 0x308 82 #define ETMPDCR 0x310 83 #define ETMPDSR 0x314 84 #define ETM_MAX_ADDR_CMP 16 85 #define ETM_MAX_CNTR 4 86 #define ETM_MAX_CTXID_CMP 3 87 88 /* Register definition */ 89 /* ETMCR - 0x00 */ 90 #define ETMCR_PWD_DWN BIT(0) 91 #define ETMCR_STALL_MODE BIT(7) 92 #define ETMCR_BRANCH_BROADCAST BIT(8) 93 #define ETMCR_ETM_PRG BIT(10) 94 #define ETMCR_ETM_EN BIT(11) 95 #define ETMCR_CYC_ACC BIT(12) 96 #define ETMCR_CTXID_SIZE (BIT(14)|BIT(15)) 97 #define ETMCR_TIMESTAMP_EN BIT(28) 98 #define ETMCR_RETURN_STACK BIT(29) 99 /* ETMCCR - 0x04 */ 100 #define ETMCCR_FIFOFULL BIT(23) 101 /* ETMPDCR - 0x310 */ 102 #define ETMPDCR_PWD_UP BIT(3) 103 /* ETMTECR1 - 0x024 */ 104 #define ETMTECR1_ADDR_COMP_1 BIT(0) 105 #define ETMTECR1_INC_EXC BIT(24) 106 #define ETMTECR1_START_STOP BIT(25) 107 /* ETMCCER - 0x1E8 */ 108 #define ETMCCER_TIMESTAMP BIT(22) 109 110 #define ETM_MODE_EXCLUDE BIT(0) 111 #define ETM_MODE_CYCACC BIT(1) 112 #define ETM_MODE_STALL BIT(2) 113 #define ETM_MODE_TIMESTAMP BIT(3) 114 #define ETM_MODE_CTXID BIT(4) 115 #define ETM_MODE_BBROAD BIT(5) 116 #define ETM_MODE_RET_STACK BIT(6) 117 #define ETM_MODE_ALL (ETM_MODE_EXCLUDE | ETM_MODE_CYCACC | \ 118 ETM_MODE_STALL | ETM_MODE_TIMESTAMP | \ 119 ETM_MODE_BBROAD | ETM_MODE_RET_STACK | \ 120 ETM_MODE_CTXID | ETM_MODE_EXCL_KERN | \ 121 ETM_MODE_EXCL_USER) 122 123 #define ETM_SQR_MASK 0x3 124 #define ETM_TRACEID_MASK 0x3f 125 #define ETM_EVENT_MASK 0x1ffff 126 #define ETM_SYNC_MASK 0xfff 127 #define ETM_ALL_MASK 0xffffffff 128 129 #define ETMSR_PROG_BIT 1 130 #define ETM_SEQ_STATE_MAX_VAL (0x2) 131 #define PORT_SIZE_MASK (GENMASK(21, 21) | GENMASK(6, 4)) 132 133 #define ETM_HARD_WIRE_RES_A /* Hard wired, always true */ \ 134 ((0x0f << 0) | \ 135 /* Resource index A */ \ 136 (0x06 << 4)) 137 138 #define ETM_ADD_COMP_0 /* Single addr comparator 1 */ \ 139 ((0x00 << 7) | \ 140 /* Resource index B */ \ 141 (0x00 << 11)) 142 143 #define ETM_EVENT_NOT_A BIT(14) /* NOT(A) */ 144 145 #define ETM_DEFAULT_EVENT_VAL (ETM_HARD_WIRE_RES_A | \ 146 ETM_ADD_COMP_0 | \ 147 ETM_EVENT_NOT_A) 148 149 /** 150 * struct etm_config - configuration information related to an ETM 151 * @mode: controls various modes supported by this ETM/PTM. 152 * @ctrl: used in conjunction with @mode. 153 * @trigger_event: setting for register ETMTRIGGER. 154 * @startstop_ctrl: setting for register ETMTSSCR. 155 * @enable_event: setting for register ETMTEEVR. 156 * @enable_ctrl1: setting for register ETMTECR1. 157 * @enable_ctrl2: setting for register ETMTECR2. 158 * @fifofull_level: setting for register ETMFFLR. 159 * @addr_idx: index for the address comparator selection. 160 * @addr_val: value for address comparator register. 161 * @addr_acctype: access type for address comparator register. 162 * @addr_type: current status of the comparator register. 163 * @cntr_idx: index for the counter register selection. 164 * @cntr_rld_val: reload value of a counter register. 165 * @cntr_event: control for counter enable register. 166 * @cntr_rld_event: value for counter reload event register. 167 * @cntr_val: counter value register. 168 * @seq_12_event: event causing the transition from 1 to 2. 169 * @seq_21_event: event causing the transition from 2 to 1. 170 * @seq_23_event: event causing the transition from 2 to 3. 171 * @seq_31_event: event causing the transition from 3 to 1. 172 * @seq_32_event: event causing the transition from 3 to 2. 173 * @seq_13_event: event causing the transition from 1 to 3. 174 * @seq_curr_state: current value of the sequencer register. 175 * @ctxid_idx: index for the context ID registers. 176 * @ctxid_pid: value for the context ID to trigger on. 177 * @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise 178 * the same value of ctxid_pid. 179 * @ctxid_mask: mask applicable to all the context IDs. 180 * @sync_freq: Synchronisation frequency. 181 * @timestamp_event: Defines an event that requests the insertion 182 * of a timestamp into the trace stream. 183 */ 184 struct etm_config { 185 u32 mode; 186 u32 ctrl; 187 u32 trigger_event; 188 u32 startstop_ctrl; 189 u32 enable_event; 190 u32 enable_ctrl1; 191 u32 enable_ctrl2; 192 u32 fifofull_level; 193 u8 addr_idx; 194 u32 addr_val[ETM_MAX_ADDR_CMP]; 195 u32 addr_acctype[ETM_MAX_ADDR_CMP]; 196 u32 addr_type[ETM_MAX_ADDR_CMP]; 197 u8 cntr_idx; 198 u32 cntr_rld_val[ETM_MAX_CNTR]; 199 u32 cntr_event[ETM_MAX_CNTR]; 200 u32 cntr_rld_event[ETM_MAX_CNTR]; 201 u32 cntr_val[ETM_MAX_CNTR]; 202 u32 seq_12_event; 203 u32 seq_21_event; 204 u32 seq_23_event; 205 u32 seq_31_event; 206 u32 seq_32_event; 207 u32 seq_13_event; 208 u32 seq_curr_state; 209 u8 ctxid_idx; 210 u32 ctxid_pid[ETM_MAX_CTXID_CMP]; 211 u32 ctxid_vpid[ETM_MAX_CTXID_CMP]; 212 u32 ctxid_mask; 213 u32 sync_freq; 214 u32 timestamp_event; 215 }; 216 217 /** 218 * struct etm_drvdata - specifics associated to an ETM component 219 * @base: memory mapped base address for this component. 220 * @dev: the device entity associated to this component. 221 * @atclk: optional clock for the core parts of the ETM. 222 * @csdev: component vitals needed by the framework. 223 * @spinlock: only one at a time pls. 224 * @cpu: the cpu this component is affined to. 225 * @port_size: port size as reported by ETMCR bit 4-6 and 21. 226 * @arch: ETM/PTM version number. 227 * @use_cpu14: true if management registers need to be accessed via CP14. 228 * @mode: this tracer's mode, i.e sysFS, Perf or disabled. 229 * @sticky_enable: true if ETM base configuration has been done. 230 * @boot_enable:true if we should start tracing at boot time. 231 * @os_unlock: true if access to management registers is allowed. 232 * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR. 233 * @nr_cntr: Number of counters as found in ETMCCR bit 13-15. 234 * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19. 235 * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22. 236 * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25. 237 * @etmccr: value of register ETMCCR. 238 * @etmccer: value of register ETMCCER. 239 * @traceid: value of the current ID for this component. 240 * @config: structure holding configuration parameters. 241 */ 242 struct etm_drvdata { 243 void __iomem *base; 244 struct device *dev; 245 struct clk *atclk; 246 struct coresight_device *csdev; 247 spinlock_t spinlock; 248 int cpu; 249 int port_size; 250 u8 arch; 251 bool use_cp14; 252 local_t mode; 253 bool sticky_enable; 254 bool boot_enable; 255 bool os_unlock; 256 u8 nr_addr_cmp; 257 u8 nr_cntr; 258 u8 nr_ext_inp; 259 u8 nr_ext_out; 260 u8 nr_ctxid_cmp; 261 u32 etmccr; 262 u32 etmccer; 263 u32 traceid; 264 struct etm_config config; 265 }; 266 267 static inline void etm_writel(struct etm_drvdata *drvdata, 268 u32 val, u32 off) 269 { 270 if (drvdata->use_cp14) { 271 if (etm_writel_cp14(off, val)) { 272 dev_err(drvdata->dev, 273 "invalid CP14 access to ETM reg: %#x", off); 274 } 275 } else { 276 writel_relaxed(val, drvdata->base + off); 277 } 278 } 279 280 static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off) 281 { 282 u32 val; 283 284 if (drvdata->use_cp14) { 285 if (etm_readl_cp14(off, &val)) { 286 dev_err(drvdata->dev, 287 "invalid CP14 access to ETM reg: %#x", off); 288 } 289 } else { 290 val = readl_relaxed(drvdata->base + off); 291 } 292 293 return val; 294 } 295 296 extern const struct attribute_group *coresight_etm_groups[]; 297 int etm_get_trace_id(struct etm_drvdata *drvdata); 298 void etm_set_default(struct etm_config *config); 299 void etm_config_trace_mode(struct etm_config *config); 300 struct etm_config *get_etm_config(struct etm_drvdata *drvdata); 301 #endif 302