1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Coresight configuration 4# 5menuconfig CORESIGHT 6 bool "CoreSight Tracing Support" 7 depends on ARM || ARM64 8 depends on OF || ACPI 9 select ARM_AMBA 10 select PERF_EVENTS 11 help 12 This framework provides a kernel interface for the CoreSight debug 13 and trace drivers to register themselves with. It's intended to build 14 a topological view of the CoreSight components based on a DT 15 specification and configure the right series of components when a 16 trace source gets enabled. 17 18if CORESIGHT 19config CORESIGHT_LINKS_AND_SINKS 20 bool "CoreSight Link and Sink drivers" 21 help 22 This enables support for CoreSight link and sink drivers that are 23 responsible for transporting and collecting the trace data 24 respectively. Link and sinks are dynamically aggregated with a trace 25 entity at run time to form a complete trace path. 26 27config CORESIGHT_LINK_AND_SINK_TMC 28 bool "Coresight generic TMC driver" 29 depends on CORESIGHT_LINKS_AND_SINKS 30 help 31 This enables support for the Trace Memory Controller driver. 32 Depending on its configuration the device can act as a link (embedded 33 trace router - ETR) or sink (embedded trace FIFO). The driver 34 complies with the generic implementation of the component without 35 special enhancement or added features. 36 37config CORESIGHT_CATU 38 bool "Coresight Address Translation Unit (CATU) driver" 39 depends on CORESIGHT_LINK_AND_SINK_TMC 40 help 41 Enable support for the Coresight Address Translation Unit (CATU). 42 CATU supports a scatter gather table of 4K pages, with forward/backward 43 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace 44 buffer by translating the addresses used by ETR to the physical address 45 by looking up the provided table. CATU can also be used in pass-through 46 mode where the address is not translated. 47 48config CORESIGHT_SINK_TPIU 49 bool "Coresight generic TPIU driver" 50 depends on CORESIGHT_LINKS_AND_SINKS 51 help 52 This enables support for the Trace Port Interface Unit driver, 53 responsible for bridging the gap between the on-chip coresight 54 components and a trace for bridging the gap between the on-chip 55 coresight components and a trace port collection engine, typically 56 connected to an external host for use case capturing more traces than 57 the on-board coresight memory can handle. 58 59config CORESIGHT_SINK_ETBV10 60 bool "Coresight ETBv1.0 driver" 61 depends on CORESIGHT_LINKS_AND_SINKS 62 help 63 This enables support for the Embedded Trace Buffer version 1.0 driver 64 that complies with the generic implementation of the component without 65 special enhancement or added features. 66 67config CORESIGHT_SOURCE_ETM3X 68 bool "CoreSight Embedded Trace Macrocell 3.x driver" 69 depends on !ARM64 70 select CORESIGHT_LINKS_AND_SINKS 71 help 72 This driver provides support for processor ETM3.x and PTM1.x modules, 73 which allows tracing the instructions that a processor is executing 74 This is primarily useful for instruction level tracing. Depending 75 the ETM version data tracing may also be available. 76 77config CORESIGHT_SOURCE_ETM4X 78 bool "CoreSight Embedded Trace Macrocell 4.x driver" 79 depends on ARM64 80 select CORESIGHT_LINKS_AND_SINKS 81 select PID_IN_CONTEXTIDR 82 help 83 This driver provides support for the ETM4.x tracer module, tracing the 84 instructions that a processor is executing. This is primarily useful 85 for instruction level tracing. Depending on the implemented version 86 data tracing may also be available. 87 88config CORESIGHT_STM 89 bool "CoreSight System Trace Macrocell driver" 90 depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 91 select CORESIGHT_LINKS_AND_SINKS 92 select STM 93 help 94 This driver provides support for hardware assisted software 95 instrumentation based tracing. This is primarily used for 96 logging useful software events or data coming from various entities 97 in the system, possibly running different OSs 98 99config CORESIGHT_CPU_DEBUG 100 tristate "CoreSight CPU Debug driver" 101 depends on ARM || ARM64 102 depends on DEBUG_FS 103 help 104 This driver provides support for coresight debugging module. This 105 is primarily used to dump sample-based profiling registers when 106 system triggers panic, the driver will parse context registers so 107 can quickly get to know program counter (PC), secure state, 108 exception level, etc. Before use debugging functionality, platform 109 needs to ensure the clock domain and power domain are enabled 110 properly, please refer Documentation/trace/coresight/coresight-cpu-debug.rst 111 for detailed description and the example for usage. 112 113config CORESIGHT_CTI 114 bool "CoreSight Cross Trigger Interface (CTI) driver" 115 depends on ARM || ARM64 116 help 117 This driver provides support for CoreSight CTI and CTM components. 118 These provide hardware triggering events between CoreSight trace 119 source and sink components. These can be used to halt trace or 120 inject events into the trace stream. CTI also provides a software 121 control to trigger the same halt events. This can provide fast trace 122 halt compared to disabling sources and sinks normally in driver 123 software. 124 125config CORESIGHT_CTI_INTEGRATION_REGS 126 bool "Access CTI CoreSight Integration Registers" 127 depends on CORESIGHT_CTI 128 help 129 This option adds support for the CoreSight integration registers on 130 this device. The integration registers allow the exploration of the 131 CTI trigger connections between this and other devices.These 132 registers are not used in normal operation and can leave devices in 133 an inconsistent state. 134endif 135