xref: /linux/drivers/hwspinlock/stm32_hwspinlock.c (revision f24fcff1d267da08c4bbb3869e7f4b36ce916b76)
1*f24fcff1SBenjamin Gaignard // SPDX-License-Identifier: GPL-2.0
2*f24fcff1SBenjamin Gaignard /*
3*f24fcff1SBenjamin Gaignard  * Copyright (C) STMicroelectronics SA 2018
4*f24fcff1SBenjamin Gaignard  * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
5*f24fcff1SBenjamin Gaignard  */
6*f24fcff1SBenjamin Gaignard 
7*f24fcff1SBenjamin Gaignard #include <linux/clk.h>
8*f24fcff1SBenjamin Gaignard #include <linux/hwspinlock.h>
9*f24fcff1SBenjamin Gaignard #include <linux/io.h>
10*f24fcff1SBenjamin Gaignard #include <linux/kernel.h>
11*f24fcff1SBenjamin Gaignard #include <linux/module.h>
12*f24fcff1SBenjamin Gaignard #include <linux/of.h>
13*f24fcff1SBenjamin Gaignard #include <linux/platform_device.h>
14*f24fcff1SBenjamin Gaignard #include <linux/pm_runtime.h>
15*f24fcff1SBenjamin Gaignard 
16*f24fcff1SBenjamin Gaignard #include "hwspinlock_internal.h"
17*f24fcff1SBenjamin Gaignard 
18*f24fcff1SBenjamin Gaignard #define STM32_MUTEX_COREID	BIT(8)
19*f24fcff1SBenjamin Gaignard #define STM32_MUTEX_LOCK_BIT	BIT(31)
20*f24fcff1SBenjamin Gaignard #define STM32_MUTEX_NUM_LOCKS	32
21*f24fcff1SBenjamin Gaignard 
22*f24fcff1SBenjamin Gaignard struct stm32_hwspinlock {
23*f24fcff1SBenjamin Gaignard 	struct clk *clk;
24*f24fcff1SBenjamin Gaignard 	struct hwspinlock_device bank;
25*f24fcff1SBenjamin Gaignard };
26*f24fcff1SBenjamin Gaignard 
27*f24fcff1SBenjamin Gaignard static int stm32_hwspinlock_trylock(struct hwspinlock *lock)
28*f24fcff1SBenjamin Gaignard {
29*f24fcff1SBenjamin Gaignard 	void __iomem *lock_addr = lock->priv;
30*f24fcff1SBenjamin Gaignard 	u32 status;
31*f24fcff1SBenjamin Gaignard 
32*f24fcff1SBenjamin Gaignard 	writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, lock_addr);
33*f24fcff1SBenjamin Gaignard 	status = readl(lock_addr);
34*f24fcff1SBenjamin Gaignard 
35*f24fcff1SBenjamin Gaignard 	return status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID);
36*f24fcff1SBenjamin Gaignard }
37*f24fcff1SBenjamin Gaignard 
38*f24fcff1SBenjamin Gaignard static void stm32_hwspinlock_unlock(struct hwspinlock *lock)
39*f24fcff1SBenjamin Gaignard {
40*f24fcff1SBenjamin Gaignard 	void __iomem *lock_addr = lock->priv;
41*f24fcff1SBenjamin Gaignard 
42*f24fcff1SBenjamin Gaignard 	writel(STM32_MUTEX_COREID, lock_addr);
43*f24fcff1SBenjamin Gaignard }
44*f24fcff1SBenjamin Gaignard 
45*f24fcff1SBenjamin Gaignard static const struct hwspinlock_ops stm32_hwspinlock_ops = {
46*f24fcff1SBenjamin Gaignard 	.trylock	= stm32_hwspinlock_trylock,
47*f24fcff1SBenjamin Gaignard 	.unlock		= stm32_hwspinlock_unlock,
48*f24fcff1SBenjamin Gaignard };
49*f24fcff1SBenjamin Gaignard 
50*f24fcff1SBenjamin Gaignard static int stm32_hwspinlock_probe(struct platform_device *pdev)
51*f24fcff1SBenjamin Gaignard {
52*f24fcff1SBenjamin Gaignard 	struct stm32_hwspinlock *hw;
53*f24fcff1SBenjamin Gaignard 	void __iomem *io_base;
54*f24fcff1SBenjamin Gaignard 	struct resource *res;
55*f24fcff1SBenjamin Gaignard 	size_t array_size;
56*f24fcff1SBenjamin Gaignard 	int i, ret;
57*f24fcff1SBenjamin Gaignard 
58*f24fcff1SBenjamin Gaignard 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
59*f24fcff1SBenjamin Gaignard 	io_base = devm_ioremap_resource(&pdev->dev, res);
60*f24fcff1SBenjamin Gaignard 	if (!io_base)
61*f24fcff1SBenjamin Gaignard 		return -ENOMEM;
62*f24fcff1SBenjamin Gaignard 
63*f24fcff1SBenjamin Gaignard 	array_size = STM32_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock);
64*f24fcff1SBenjamin Gaignard 	hw = devm_kzalloc(&pdev->dev, sizeof(*hw) + array_size, GFP_KERNEL);
65*f24fcff1SBenjamin Gaignard 	if (!hw)
66*f24fcff1SBenjamin Gaignard 		return -ENOMEM;
67*f24fcff1SBenjamin Gaignard 
68*f24fcff1SBenjamin Gaignard 	hw->clk = devm_clk_get(&pdev->dev, "hsem");
69*f24fcff1SBenjamin Gaignard 	if (IS_ERR(hw->clk))
70*f24fcff1SBenjamin Gaignard 		return PTR_ERR(hw->clk);
71*f24fcff1SBenjamin Gaignard 
72*f24fcff1SBenjamin Gaignard 	for (i = 0; i < STM32_MUTEX_NUM_LOCKS; i++)
73*f24fcff1SBenjamin Gaignard 		hw->bank.lock[i].priv = io_base + i * sizeof(u32);
74*f24fcff1SBenjamin Gaignard 
75*f24fcff1SBenjamin Gaignard 	platform_set_drvdata(pdev, hw);
76*f24fcff1SBenjamin Gaignard 	pm_runtime_enable(&pdev->dev);
77*f24fcff1SBenjamin Gaignard 
78*f24fcff1SBenjamin Gaignard 	ret = hwspin_lock_register(&hw->bank, &pdev->dev, &stm32_hwspinlock_ops,
79*f24fcff1SBenjamin Gaignard 				   0, STM32_MUTEX_NUM_LOCKS);
80*f24fcff1SBenjamin Gaignard 
81*f24fcff1SBenjamin Gaignard 	if (ret)
82*f24fcff1SBenjamin Gaignard 		pm_runtime_disable(&pdev->dev);
83*f24fcff1SBenjamin Gaignard 
84*f24fcff1SBenjamin Gaignard 	return ret;
85*f24fcff1SBenjamin Gaignard }
86*f24fcff1SBenjamin Gaignard 
87*f24fcff1SBenjamin Gaignard static int stm32_hwspinlock_remove(struct platform_device *pdev)
88*f24fcff1SBenjamin Gaignard {
89*f24fcff1SBenjamin Gaignard 	struct stm32_hwspinlock *hw = platform_get_drvdata(pdev);
90*f24fcff1SBenjamin Gaignard 	int ret;
91*f24fcff1SBenjamin Gaignard 
92*f24fcff1SBenjamin Gaignard 	ret = hwspin_lock_unregister(&hw->bank);
93*f24fcff1SBenjamin Gaignard 	if (ret)
94*f24fcff1SBenjamin Gaignard 		dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret);
95*f24fcff1SBenjamin Gaignard 
96*f24fcff1SBenjamin Gaignard 	pm_runtime_disable(&pdev->dev);
97*f24fcff1SBenjamin Gaignard 
98*f24fcff1SBenjamin Gaignard 	return 0;
99*f24fcff1SBenjamin Gaignard }
100*f24fcff1SBenjamin Gaignard 
101*f24fcff1SBenjamin Gaignard static int __maybe_unused stm32_hwspinlock_runtime_suspend(struct device *dev)
102*f24fcff1SBenjamin Gaignard {
103*f24fcff1SBenjamin Gaignard 	struct stm32_hwspinlock *hw = dev_get_drvdata(dev);
104*f24fcff1SBenjamin Gaignard 
105*f24fcff1SBenjamin Gaignard 	clk_disable_unprepare(hw->clk);
106*f24fcff1SBenjamin Gaignard 
107*f24fcff1SBenjamin Gaignard 	return 0;
108*f24fcff1SBenjamin Gaignard }
109*f24fcff1SBenjamin Gaignard 
110*f24fcff1SBenjamin Gaignard static int __maybe_unused stm32_hwspinlock_runtime_resume(struct device *dev)
111*f24fcff1SBenjamin Gaignard {
112*f24fcff1SBenjamin Gaignard 	struct stm32_hwspinlock *hw = dev_get_drvdata(dev);
113*f24fcff1SBenjamin Gaignard 
114*f24fcff1SBenjamin Gaignard 	clk_prepare_enable(hw->clk);
115*f24fcff1SBenjamin Gaignard 
116*f24fcff1SBenjamin Gaignard 	return 0;
117*f24fcff1SBenjamin Gaignard }
118*f24fcff1SBenjamin Gaignard 
119*f24fcff1SBenjamin Gaignard static const struct dev_pm_ops stm32_hwspinlock_pm_ops = {
120*f24fcff1SBenjamin Gaignard 	SET_RUNTIME_PM_OPS(stm32_hwspinlock_runtime_suspend,
121*f24fcff1SBenjamin Gaignard 			   stm32_hwspinlock_runtime_resume,
122*f24fcff1SBenjamin Gaignard 			   NULL)
123*f24fcff1SBenjamin Gaignard };
124*f24fcff1SBenjamin Gaignard 
125*f24fcff1SBenjamin Gaignard static const struct of_device_id stm32_hwpinlock_ids[] = {
126*f24fcff1SBenjamin Gaignard 	{ .compatible = "st,stm32-hwspinlock", },
127*f24fcff1SBenjamin Gaignard 	{},
128*f24fcff1SBenjamin Gaignard };
129*f24fcff1SBenjamin Gaignard MODULE_DEVICE_TABLE(of, stm32_hwpinlock_ids);
130*f24fcff1SBenjamin Gaignard 
131*f24fcff1SBenjamin Gaignard static struct platform_driver stm32_hwspinlock_driver = {
132*f24fcff1SBenjamin Gaignard 	.probe		= stm32_hwspinlock_probe,
133*f24fcff1SBenjamin Gaignard 	.remove		= stm32_hwspinlock_remove,
134*f24fcff1SBenjamin Gaignard 	.driver		= {
135*f24fcff1SBenjamin Gaignard 		.name	= "stm32_hwspinlock",
136*f24fcff1SBenjamin Gaignard 		.of_match_table = stm32_hwpinlock_ids,
137*f24fcff1SBenjamin Gaignard 		.pm	= &stm32_hwspinlock_pm_ops,
138*f24fcff1SBenjamin Gaignard 	},
139*f24fcff1SBenjamin Gaignard };
140*f24fcff1SBenjamin Gaignard 
141*f24fcff1SBenjamin Gaignard static int __init stm32_hwspinlock_init(void)
142*f24fcff1SBenjamin Gaignard {
143*f24fcff1SBenjamin Gaignard 	return platform_driver_register(&stm32_hwspinlock_driver);
144*f24fcff1SBenjamin Gaignard }
145*f24fcff1SBenjamin Gaignard /* board init code might need to reserve hwspinlocks for predefined purposes */
146*f24fcff1SBenjamin Gaignard postcore_initcall(stm32_hwspinlock_init);
147*f24fcff1SBenjamin Gaignard 
148*f24fcff1SBenjamin Gaignard static void __exit stm32_hwspinlock_exit(void)
149*f24fcff1SBenjamin Gaignard {
150*f24fcff1SBenjamin Gaignard 	platform_driver_unregister(&stm32_hwspinlock_driver);
151*f24fcff1SBenjamin Gaignard }
152*f24fcff1SBenjamin Gaignard module_exit(stm32_hwspinlock_exit);
153*f24fcff1SBenjamin Gaignard 
154*f24fcff1SBenjamin Gaignard MODULE_LICENSE("GPL v2");
155*f24fcff1SBenjamin Gaignard MODULE_DESCRIPTION("Hardware spinlock driver for STM32 SoCs");
156*f24fcff1SBenjamin Gaignard MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
157