1f24fcff1SBenjamin Gaignard // SPDX-License-Identifier: GPL-2.0 2f24fcff1SBenjamin Gaignard /* 3f24fcff1SBenjamin Gaignard * Copyright (C) STMicroelectronics SA 2018 4f24fcff1SBenjamin Gaignard * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics. 5f24fcff1SBenjamin Gaignard */ 6f24fcff1SBenjamin Gaignard 7f24fcff1SBenjamin Gaignard #include <linux/clk.h> 85cd69f13SFabien Dessenne #include <linux/delay.h> 9f24fcff1SBenjamin Gaignard #include <linux/hwspinlock.h> 10f24fcff1SBenjamin Gaignard #include <linux/io.h> 11f24fcff1SBenjamin Gaignard #include <linux/kernel.h> 12f24fcff1SBenjamin Gaignard #include <linux/module.h> 13f24fcff1SBenjamin Gaignard #include <linux/of.h> 14f24fcff1SBenjamin Gaignard #include <linux/platform_device.h> 15f24fcff1SBenjamin Gaignard #include <linux/pm_runtime.h> 16f24fcff1SBenjamin Gaignard 17f24fcff1SBenjamin Gaignard #include "hwspinlock_internal.h" 18f24fcff1SBenjamin Gaignard 19f24fcff1SBenjamin Gaignard #define STM32_MUTEX_COREID BIT(8) 20f24fcff1SBenjamin Gaignard #define STM32_MUTEX_LOCK_BIT BIT(31) 21f24fcff1SBenjamin Gaignard #define STM32_MUTEX_NUM_LOCKS 32 22f24fcff1SBenjamin Gaignard 23f24fcff1SBenjamin Gaignard struct stm32_hwspinlock { 24f24fcff1SBenjamin Gaignard struct clk *clk; 25f24fcff1SBenjamin Gaignard struct hwspinlock_device bank; 26f24fcff1SBenjamin Gaignard }; 27f24fcff1SBenjamin Gaignard 28f24fcff1SBenjamin Gaignard static int stm32_hwspinlock_trylock(struct hwspinlock *lock) 29f24fcff1SBenjamin Gaignard { 30f24fcff1SBenjamin Gaignard void __iomem *lock_addr = lock->priv; 31f24fcff1SBenjamin Gaignard u32 status; 32f24fcff1SBenjamin Gaignard 33f24fcff1SBenjamin Gaignard writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, lock_addr); 34f24fcff1SBenjamin Gaignard status = readl(lock_addr); 35f24fcff1SBenjamin Gaignard 36f24fcff1SBenjamin Gaignard return status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID); 37f24fcff1SBenjamin Gaignard } 38f24fcff1SBenjamin Gaignard 39f24fcff1SBenjamin Gaignard static void stm32_hwspinlock_unlock(struct hwspinlock *lock) 40f24fcff1SBenjamin Gaignard { 41f24fcff1SBenjamin Gaignard void __iomem *lock_addr = lock->priv; 42f24fcff1SBenjamin Gaignard 43f24fcff1SBenjamin Gaignard writel(STM32_MUTEX_COREID, lock_addr); 44f24fcff1SBenjamin Gaignard } 45f24fcff1SBenjamin Gaignard 465cd69f13SFabien Dessenne static void stm32_hwspinlock_relax(struct hwspinlock *lock) 475cd69f13SFabien Dessenne { 485cd69f13SFabien Dessenne ndelay(50); 495cd69f13SFabien Dessenne } 505cd69f13SFabien Dessenne 51f24fcff1SBenjamin Gaignard static const struct hwspinlock_ops stm32_hwspinlock_ops = { 52f24fcff1SBenjamin Gaignard .trylock = stm32_hwspinlock_trylock, 53f24fcff1SBenjamin Gaignard .unlock = stm32_hwspinlock_unlock, 545cd69f13SFabien Dessenne .relax = stm32_hwspinlock_relax, 55f24fcff1SBenjamin Gaignard }; 56f24fcff1SBenjamin Gaignard 57*60630924SFabien Dessenne static void stm32_hwspinlock_disable_clk(void *data) 58*60630924SFabien Dessenne { 59*60630924SFabien Dessenne struct platform_device *pdev = data; 60*60630924SFabien Dessenne struct stm32_hwspinlock *hw = platform_get_drvdata(pdev); 61*60630924SFabien Dessenne struct device *dev = &pdev->dev; 62*60630924SFabien Dessenne 63*60630924SFabien Dessenne pm_runtime_get_sync(dev); 64*60630924SFabien Dessenne pm_runtime_disable(dev); 65*60630924SFabien Dessenne pm_runtime_set_suspended(dev); 66*60630924SFabien Dessenne pm_runtime_put_noidle(dev); 67*60630924SFabien Dessenne 68*60630924SFabien Dessenne clk_disable_unprepare(hw->clk); 69*60630924SFabien Dessenne } 70*60630924SFabien Dessenne 71f24fcff1SBenjamin Gaignard static int stm32_hwspinlock_probe(struct platform_device *pdev) 72f24fcff1SBenjamin Gaignard { 73*60630924SFabien Dessenne struct device *dev = &pdev->dev; 74f24fcff1SBenjamin Gaignard struct stm32_hwspinlock *hw; 75f24fcff1SBenjamin Gaignard void __iomem *io_base; 76f24fcff1SBenjamin Gaignard size_t array_size; 77f24fcff1SBenjamin Gaignard int i, ret; 78f24fcff1SBenjamin Gaignard 79d4824486SYangtao Li io_base = devm_platform_ioremap_resource(pdev, 0); 804d5a91fdSWei Yongjun if (IS_ERR(io_base)) 814d5a91fdSWei Yongjun return PTR_ERR(io_base); 82f24fcff1SBenjamin Gaignard 83f24fcff1SBenjamin Gaignard array_size = STM32_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); 84*60630924SFabien Dessenne hw = devm_kzalloc(dev, sizeof(*hw) + array_size, GFP_KERNEL); 85f24fcff1SBenjamin Gaignard if (!hw) 86f24fcff1SBenjamin Gaignard return -ENOMEM; 87f24fcff1SBenjamin Gaignard 88*60630924SFabien Dessenne hw->clk = devm_clk_get(dev, "hsem"); 89f24fcff1SBenjamin Gaignard if (IS_ERR(hw->clk)) 90f24fcff1SBenjamin Gaignard return PTR_ERR(hw->clk); 91f24fcff1SBenjamin Gaignard 92*60630924SFabien Dessenne ret = clk_prepare_enable(hw->clk); 93*60630924SFabien Dessenne if (ret) { 94*60630924SFabien Dessenne dev_err(dev, "Failed to prepare_enable clock\n"); 95*60630924SFabien Dessenne return ret; 96*60630924SFabien Dessenne } 97*60630924SFabien Dessenne 98*60630924SFabien Dessenne platform_set_drvdata(pdev, hw); 99*60630924SFabien Dessenne 100*60630924SFabien Dessenne pm_runtime_get_noresume(dev); 101*60630924SFabien Dessenne pm_runtime_set_active(dev); 102*60630924SFabien Dessenne pm_runtime_enable(dev); 103*60630924SFabien Dessenne pm_runtime_put(dev); 104*60630924SFabien Dessenne 105*60630924SFabien Dessenne ret = devm_add_action_or_reset(dev, stm32_hwspinlock_disable_clk, pdev); 106*60630924SFabien Dessenne if (ret) { 107*60630924SFabien Dessenne dev_err(dev, "Failed to register action\n"); 108*60630924SFabien Dessenne return ret; 109*60630924SFabien Dessenne } 110*60630924SFabien Dessenne 111f24fcff1SBenjamin Gaignard for (i = 0; i < STM32_MUTEX_NUM_LOCKS; i++) 112f24fcff1SBenjamin Gaignard hw->bank.lock[i].priv = io_base + i * sizeof(u32); 113f24fcff1SBenjamin Gaignard 114*60630924SFabien Dessenne ret = devm_hwspin_lock_register(dev, &hw->bank, &stm32_hwspinlock_ops, 115f24fcff1SBenjamin Gaignard 0, STM32_MUTEX_NUM_LOCKS); 116f24fcff1SBenjamin Gaignard 117f24fcff1SBenjamin Gaignard if (ret) 118*60630924SFabien Dessenne dev_err(dev, "Failed to register hwspinlock\n"); 119f24fcff1SBenjamin Gaignard 120f24fcff1SBenjamin Gaignard return ret; 121f24fcff1SBenjamin Gaignard } 122f24fcff1SBenjamin Gaignard 123f24fcff1SBenjamin Gaignard static int __maybe_unused stm32_hwspinlock_runtime_suspend(struct device *dev) 124f24fcff1SBenjamin Gaignard { 125f24fcff1SBenjamin Gaignard struct stm32_hwspinlock *hw = dev_get_drvdata(dev); 126f24fcff1SBenjamin Gaignard 127f24fcff1SBenjamin Gaignard clk_disable_unprepare(hw->clk); 128f24fcff1SBenjamin Gaignard 129f24fcff1SBenjamin Gaignard return 0; 130f24fcff1SBenjamin Gaignard } 131f24fcff1SBenjamin Gaignard 132f24fcff1SBenjamin Gaignard static int __maybe_unused stm32_hwspinlock_runtime_resume(struct device *dev) 133f24fcff1SBenjamin Gaignard { 134f24fcff1SBenjamin Gaignard struct stm32_hwspinlock *hw = dev_get_drvdata(dev); 135f24fcff1SBenjamin Gaignard 136f24fcff1SBenjamin Gaignard clk_prepare_enable(hw->clk); 137f24fcff1SBenjamin Gaignard 138f24fcff1SBenjamin Gaignard return 0; 139f24fcff1SBenjamin Gaignard } 140f24fcff1SBenjamin Gaignard 141f24fcff1SBenjamin Gaignard static const struct dev_pm_ops stm32_hwspinlock_pm_ops = { 142f24fcff1SBenjamin Gaignard SET_RUNTIME_PM_OPS(stm32_hwspinlock_runtime_suspend, 143f24fcff1SBenjamin Gaignard stm32_hwspinlock_runtime_resume, 144f24fcff1SBenjamin Gaignard NULL) 145f24fcff1SBenjamin Gaignard }; 146f24fcff1SBenjamin Gaignard 147f24fcff1SBenjamin Gaignard static const struct of_device_id stm32_hwpinlock_ids[] = { 148f24fcff1SBenjamin Gaignard { .compatible = "st,stm32-hwspinlock", }, 149f24fcff1SBenjamin Gaignard {}, 150f24fcff1SBenjamin Gaignard }; 151f24fcff1SBenjamin Gaignard MODULE_DEVICE_TABLE(of, stm32_hwpinlock_ids); 152f24fcff1SBenjamin Gaignard 153f24fcff1SBenjamin Gaignard static struct platform_driver stm32_hwspinlock_driver = { 154f24fcff1SBenjamin Gaignard .probe = stm32_hwspinlock_probe, 155f24fcff1SBenjamin Gaignard .driver = { 156f24fcff1SBenjamin Gaignard .name = "stm32_hwspinlock", 157f24fcff1SBenjamin Gaignard .of_match_table = stm32_hwpinlock_ids, 158f24fcff1SBenjamin Gaignard .pm = &stm32_hwspinlock_pm_ops, 159f24fcff1SBenjamin Gaignard }, 160f24fcff1SBenjamin Gaignard }; 161f24fcff1SBenjamin Gaignard 162f24fcff1SBenjamin Gaignard static int __init stm32_hwspinlock_init(void) 163f24fcff1SBenjamin Gaignard { 164f24fcff1SBenjamin Gaignard return platform_driver_register(&stm32_hwspinlock_driver); 165f24fcff1SBenjamin Gaignard } 166f24fcff1SBenjamin Gaignard /* board init code might need to reserve hwspinlocks for predefined purposes */ 167f24fcff1SBenjamin Gaignard postcore_initcall(stm32_hwspinlock_init); 168f24fcff1SBenjamin Gaignard 169f24fcff1SBenjamin Gaignard static void __exit stm32_hwspinlock_exit(void) 170f24fcff1SBenjamin Gaignard { 171f24fcff1SBenjamin Gaignard platform_driver_unregister(&stm32_hwspinlock_driver); 172f24fcff1SBenjamin Gaignard } 173f24fcff1SBenjamin Gaignard module_exit(stm32_hwspinlock_exit); 174f24fcff1SBenjamin Gaignard 175f24fcff1SBenjamin Gaignard MODULE_LICENSE("GPL v2"); 176f24fcff1SBenjamin Gaignard MODULE_DESCRIPTION("Hardware spinlock driver for STM32 SoCs"); 177f24fcff1SBenjamin Gaignard MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 178