1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Jedec 5118 compliant temperature sensors 4 * 5 * Derived from https://github.com/Steve-Tech/SPD5118-DKMS 6 * Originally from T/2 driver at https://t2sde.org/packages/linux 7 * Copyright (c) 2023 René Rebe, ExactCODE GmbH; Germany. 8 * 9 * Copyright (c) 2024 Guenter Roeck 10 * 11 * Inspired by ee1004.c and jc42.c. 12 * 13 * SPD5118 compliant temperature sensors are typically used on DDR5 14 * memory modules. 15 */ 16 17 #include <linux/bitops.h> 18 #include <linux/bits.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/hwmon.h> 22 #include <linux/module.h> 23 #include <linux/pm.h> 24 #include <linux/regmap.h> 25 #include <linux/units.h> 26 27 /* Addresses to scan */ 28 static const unsigned short normal_i2c[] = { 29 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, I2C_CLIENT_END }; 30 31 /* SPD5118 registers. */ 32 #define SPD5118_REG_TYPE 0x00 /* MR0:MR1 */ 33 #define SPD5118_REG_REVISION 0x02 /* MR2 */ 34 #define SPD5118_REG_VENDOR 0x03 /* MR3:MR4 */ 35 #define SPD5118_REG_CAPABILITY 0x05 /* MR5 */ 36 #define SPD5118_REG_I2C_LEGACY_MODE 0x0B /* MR11 */ 37 #define SPD5118_REG_TEMP_CLR 0x13 /* MR19 */ 38 #define SPD5118_REG_ERROR_CLR 0x14 /* MR20 */ 39 #define SPD5118_REG_TEMP_CONFIG 0x1A /* MR26 */ 40 #define SPD5118_REG_TEMP_MAX 0x1c /* MR28:MR29 */ 41 #define SPD5118_REG_TEMP_MIN 0x1e /* MR30:MR31 */ 42 #define SPD5118_REG_TEMP_CRIT 0x20 /* MR32:MR33 */ 43 #define SPD5118_REG_TEMP_LCRIT 0x22 /* MR34:MR35 */ 44 #define SPD5118_REG_TEMP 0x31 /* MR49:MR50 */ 45 #define SPD5118_REG_TEMP_STATUS 0x33 /* MR51 */ 46 47 #define SPD5118_TEMP_STATUS_HIGH BIT(0) 48 #define SPD5118_TEMP_STATUS_LOW BIT(1) 49 #define SPD5118_TEMP_STATUS_CRIT BIT(2) 50 #define SPD5118_TEMP_STATUS_LCRIT BIT(3) 51 52 #define SPD5118_CAP_TS_SUPPORT BIT(1) /* temperature sensor support */ 53 54 #define SPD5118_TS_DISABLE BIT(0) /* temperature sensor disable */ 55 56 /* Temperature unit in millicelsius */ 57 #define SPD5118_TEMP_UNIT (MILLIDEGREE_PER_DEGREE / 4) 58 /* Representable temperature range in millicelsius */ 59 #define SPD5118_TEMP_RANGE_MIN -256000 60 #define SPD5118_TEMP_RANGE_MAX 255750 61 62 static int spd5118_temp_from_reg(u16 reg) 63 { 64 int temp = sign_extend32(reg >> 2, 10); 65 66 return temp * SPD5118_TEMP_UNIT; 67 } 68 69 static u16 spd5118_temp_to_reg(long temp) 70 { 71 temp = clamp_val(temp, SPD5118_TEMP_RANGE_MIN, SPD5118_TEMP_RANGE_MAX); 72 return (DIV_ROUND_CLOSEST(temp, SPD5118_TEMP_UNIT) & 0x7ff) << 2; 73 } 74 75 static int spd5118_read_temp(struct regmap *regmap, u32 attr, long *val) 76 { 77 int reg, err; 78 u8 regval[2]; 79 u16 temp; 80 81 switch (attr) { 82 case hwmon_temp_input: 83 reg = SPD5118_REG_TEMP; 84 break; 85 case hwmon_temp_max: 86 reg = SPD5118_REG_TEMP_MAX; 87 break; 88 case hwmon_temp_min: 89 reg = SPD5118_REG_TEMP_MIN; 90 break; 91 case hwmon_temp_crit: 92 reg = SPD5118_REG_TEMP_CRIT; 93 break; 94 case hwmon_temp_lcrit: 95 reg = SPD5118_REG_TEMP_LCRIT; 96 break; 97 default: 98 return -EOPNOTSUPP; 99 } 100 101 err = regmap_bulk_read(regmap, reg, regval, 2); 102 if (err) 103 return err; 104 105 temp = (regval[1] << 8) | regval[0]; 106 107 *val = spd5118_temp_from_reg(temp); 108 return 0; 109 } 110 111 static int spd5118_read_alarm(struct regmap *regmap, u32 attr, long *val) 112 { 113 unsigned int mask, regval; 114 int err; 115 116 switch (attr) { 117 case hwmon_temp_max_alarm: 118 mask = SPD5118_TEMP_STATUS_HIGH; 119 break; 120 case hwmon_temp_min_alarm: 121 mask = SPD5118_TEMP_STATUS_LOW; 122 break; 123 case hwmon_temp_crit_alarm: 124 mask = SPD5118_TEMP_STATUS_CRIT; 125 break; 126 case hwmon_temp_lcrit_alarm: 127 mask = SPD5118_TEMP_STATUS_LCRIT; 128 break; 129 default: 130 return -EOPNOTSUPP; 131 } 132 133 err = regmap_read(regmap, SPD5118_REG_TEMP_STATUS, ®val); 134 if (err < 0) 135 return err; 136 *val = !!(regval & mask); 137 if (*val) 138 return regmap_write(regmap, SPD5118_REG_TEMP_CLR, mask); 139 return 0; 140 } 141 142 static int spd5118_read_enable(struct regmap *regmap, long *val) 143 { 144 u32 regval; 145 int err; 146 147 err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, ®val); 148 if (err < 0) 149 return err; 150 *val = !(regval & SPD5118_TS_DISABLE); 151 return 0; 152 } 153 154 static int spd5118_read(struct device *dev, enum hwmon_sensor_types type, 155 u32 attr, int channel, long *val) 156 { 157 struct regmap *regmap = dev_get_drvdata(dev); 158 159 if (type != hwmon_temp) 160 return -EOPNOTSUPP; 161 162 switch (attr) { 163 case hwmon_temp_input: 164 case hwmon_temp_max: 165 case hwmon_temp_min: 166 case hwmon_temp_crit: 167 case hwmon_temp_lcrit: 168 return spd5118_read_temp(regmap, attr, val); 169 case hwmon_temp_max_alarm: 170 case hwmon_temp_min_alarm: 171 case hwmon_temp_crit_alarm: 172 case hwmon_temp_lcrit_alarm: 173 return spd5118_read_alarm(regmap, attr, val); 174 case hwmon_temp_enable: 175 return spd5118_read_enable(regmap, val); 176 default: 177 return -EOPNOTSUPP; 178 } 179 } 180 181 static int spd5118_write_temp(struct regmap *regmap, u32 attr, long val) 182 { 183 u8 regval[2]; 184 u16 temp; 185 int reg; 186 187 switch (attr) { 188 case hwmon_temp_max: 189 reg = SPD5118_REG_TEMP_MAX; 190 break; 191 case hwmon_temp_min: 192 reg = SPD5118_REG_TEMP_MIN; 193 break; 194 case hwmon_temp_crit: 195 reg = SPD5118_REG_TEMP_CRIT; 196 break; 197 case hwmon_temp_lcrit: 198 reg = SPD5118_REG_TEMP_LCRIT; 199 break; 200 default: 201 return -EOPNOTSUPP; 202 } 203 204 temp = spd5118_temp_to_reg(val); 205 regval[0] = temp & 0xff; 206 regval[1] = temp >> 8; 207 208 return regmap_bulk_write(regmap, reg, regval, 2); 209 } 210 211 static int spd5118_write_enable(struct regmap *regmap, long val) 212 { 213 if (val && val != 1) 214 return -EINVAL; 215 216 return regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG, 217 SPD5118_TS_DISABLE, 218 val ? 0 : SPD5118_TS_DISABLE); 219 } 220 221 static int spd5118_temp_write(struct regmap *regmap, u32 attr, long val) 222 { 223 switch (attr) { 224 case hwmon_temp_max: 225 case hwmon_temp_min: 226 case hwmon_temp_crit: 227 case hwmon_temp_lcrit: 228 return spd5118_write_temp(regmap, attr, val); 229 case hwmon_temp_enable: 230 return spd5118_write_enable(regmap, val); 231 default: 232 return -EOPNOTSUPP; 233 } 234 } 235 236 static int spd5118_write(struct device *dev, enum hwmon_sensor_types type, 237 u32 attr, int channel, long val) 238 { 239 struct regmap *regmap = dev_get_drvdata(dev); 240 241 switch (type) { 242 case hwmon_temp: 243 return spd5118_temp_write(regmap, attr, val); 244 default: 245 return -EOPNOTSUPP; 246 } 247 } 248 249 static umode_t spd5118_is_visible(const void *_data, enum hwmon_sensor_types type, 250 u32 attr, int channel) 251 { 252 if (type != hwmon_temp) 253 return 0; 254 255 switch (attr) { 256 case hwmon_temp_input: 257 return 0444; 258 case hwmon_temp_min: 259 case hwmon_temp_max: 260 case hwmon_temp_lcrit: 261 case hwmon_temp_crit: 262 case hwmon_temp_enable: 263 return 0644; 264 case hwmon_temp_min_alarm: 265 case hwmon_temp_max_alarm: 266 case hwmon_temp_crit_alarm: 267 case hwmon_temp_lcrit_alarm: 268 return 0444; 269 default: 270 return 0; 271 } 272 } 273 274 static inline bool spd5118_parity8(u8 w) 275 { 276 w ^= w >> 4; 277 return (0x6996 >> (w & 0xf)) & 1; 278 } 279 280 /* 281 * Bank and vendor id are 8-bit fields with seven data bits and odd parity. 282 * Vendor IDs 0 and 0x7f are invalid. 283 * See Jedec standard JEP106BJ for details and a list of assigned vendor IDs. 284 */ 285 static bool spd5118_vendor_valid(u8 bank, u8 id) 286 { 287 if (!spd5118_parity8(bank) || !spd5118_parity8(id)) 288 return false; 289 290 id &= 0x7f; 291 return id && id != 0x7f; 292 } 293 294 /* Return 0 if detection is successful, -ENODEV otherwise */ 295 static int spd5118_detect(struct i2c_client *client, struct i2c_board_info *info) 296 { 297 struct i2c_adapter *adapter = client->adapter; 298 int regval; 299 300 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | 301 I2C_FUNC_SMBUS_WORD_DATA)) 302 return -ENODEV; 303 304 regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); 305 if (regval != 0x5118) 306 return -ENODEV; 307 308 regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR); 309 if (regval < 0 || !spd5118_vendor_valid(regval & 0xff, regval >> 8)) 310 return -ENODEV; 311 312 regval = i2c_smbus_read_byte_data(client, SPD5118_REG_CAPABILITY); 313 if (regval < 0) 314 return -ENODEV; 315 if (!(regval & SPD5118_CAP_TS_SUPPORT) || (regval & 0xfc)) 316 return -ENODEV; 317 318 regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CLR); 319 if (regval) 320 return -ENODEV; 321 regval = i2c_smbus_read_byte_data(client, SPD5118_REG_ERROR_CLR); 322 if (regval) 323 return -ENODEV; 324 325 regval = i2c_smbus_read_byte_data(client, SPD5118_REG_REVISION); 326 if (regval < 0 || (regval & 0xc1)) 327 return -ENODEV; 328 329 regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CONFIG); 330 if (regval < 0) 331 return -ENODEV; 332 if (regval & ~SPD5118_TS_DISABLE) 333 return -ENODEV; 334 335 strscpy(info->type, "spd5118", I2C_NAME_SIZE); 336 return 0; 337 } 338 339 static const struct hwmon_channel_info *spd5118_info[] = { 340 HWMON_CHANNEL_INFO(chip, 341 HWMON_C_REGISTER_TZ), 342 HWMON_CHANNEL_INFO(temp, 343 HWMON_T_INPUT | 344 HWMON_T_LCRIT | HWMON_T_LCRIT_ALARM | 345 HWMON_T_MIN | HWMON_T_MIN_ALARM | 346 HWMON_T_MAX | HWMON_T_MAX_ALARM | 347 HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 348 HWMON_T_ENABLE), 349 NULL 350 }; 351 352 static const struct hwmon_ops spd5118_hwmon_ops = { 353 .is_visible = spd5118_is_visible, 354 .read = spd5118_read, 355 .write = spd5118_write, 356 }; 357 358 static const struct hwmon_chip_info spd5118_chip_info = { 359 .ops = &spd5118_hwmon_ops, 360 .info = spd5118_info, 361 }; 362 363 static bool spd5118_writeable_reg(struct device *dev, unsigned int reg) 364 { 365 switch (reg) { 366 case SPD5118_REG_TEMP_CLR: 367 case SPD5118_REG_TEMP_CONFIG: 368 case SPD5118_REG_TEMP_MAX: 369 case SPD5118_REG_TEMP_MAX + 1: 370 case SPD5118_REG_TEMP_MIN: 371 case SPD5118_REG_TEMP_MIN + 1: 372 case SPD5118_REG_TEMP_CRIT: 373 case SPD5118_REG_TEMP_CRIT + 1: 374 case SPD5118_REG_TEMP_LCRIT: 375 case SPD5118_REG_TEMP_LCRIT + 1: 376 return true; 377 default: 378 return false; 379 } 380 } 381 382 static bool spd5118_volatile_reg(struct device *dev, unsigned int reg) 383 { 384 switch (reg) { 385 case SPD5118_REG_TEMP_CLR: 386 case SPD5118_REG_ERROR_CLR: 387 case SPD5118_REG_TEMP: 388 case SPD5118_REG_TEMP + 1: 389 case SPD5118_REG_TEMP_STATUS: 390 return true; 391 default: 392 return false; 393 } 394 } 395 396 static const struct regmap_config spd5118_regmap_config = { 397 .reg_bits = 8, 398 .val_bits = 8, 399 .max_register = SPD5118_REG_TEMP_STATUS, 400 .writeable_reg = spd5118_writeable_reg, 401 .volatile_reg = spd5118_volatile_reg, 402 .cache_type = REGCACHE_MAPLE, 403 }; 404 405 static int spd5118_probe(struct i2c_client *client) 406 { 407 struct device *dev = &client->dev; 408 unsigned int regval, revision, vendor, bank; 409 struct device *hwmon_dev; 410 struct regmap *regmap; 411 int err; 412 413 regmap = devm_regmap_init_i2c(client, &spd5118_regmap_config); 414 if (IS_ERR(regmap)) 415 return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n"); 416 417 err = regmap_read(regmap, SPD5118_REG_CAPABILITY, ®val); 418 if (err) 419 return err; 420 if (!(regval & SPD5118_CAP_TS_SUPPORT)) 421 return -ENODEV; 422 423 err = regmap_read(regmap, SPD5118_REG_REVISION, &revision); 424 if (err) 425 return err; 426 427 err = regmap_read(regmap, SPD5118_REG_VENDOR, &bank); 428 if (err) 429 return err; 430 err = regmap_read(regmap, SPD5118_REG_VENDOR + 1, &vendor); 431 if (err) 432 return err; 433 if (!spd5118_vendor_valid(bank, vendor)) 434 return -ENODEV; 435 436 dev_set_drvdata(dev, regmap); 437 438 hwmon_dev = devm_hwmon_device_register_with_info(dev, "spd5118", 439 regmap, &spd5118_chip_info, 440 NULL); 441 if (IS_ERR(hwmon_dev)) 442 return PTR_ERR(hwmon_dev); 443 444 /* 445 * From JESD300-5B 446 * MR2 bits [5:4]: Major revision, 1..4 447 * MR2 bits [3:1]: Minor revision, 0..8? Probably a typo, assume 1..8 448 */ 449 dev_info(dev, "DDR5 temperature sensor: vendor 0x%02x:0x%02x revision %d.%d\n", 450 bank & 0x7f, vendor, ((revision >> 4) & 0x03) + 1, ((revision >> 1) & 0x07) + 1); 451 452 return 0; 453 } 454 455 static int spd5118_suspend(struct device *dev) 456 { 457 struct regmap *regmap = dev_get_drvdata(dev); 458 u32 regval; 459 int err; 460 461 /* 462 * Make sure the configuration register in the regmap cache is current 463 * before bypassing it. 464 */ 465 err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, ®val); 466 if (err < 0) 467 return err; 468 469 regcache_cache_bypass(regmap, true); 470 regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG, SPD5118_TS_DISABLE, 471 SPD5118_TS_DISABLE); 472 regcache_cache_bypass(regmap, false); 473 474 regcache_cache_only(regmap, true); 475 regcache_mark_dirty(regmap); 476 477 return 0; 478 } 479 480 static int spd5118_resume(struct device *dev) 481 { 482 struct regmap *regmap = dev_get_drvdata(dev); 483 484 regcache_cache_only(regmap, false); 485 return regcache_sync(regmap); 486 } 487 488 static DEFINE_SIMPLE_DEV_PM_OPS(spd5118_pm_ops, spd5118_suspend, spd5118_resume); 489 490 static const struct i2c_device_id spd5118_id[] = { 491 { "spd5118", 0 }, 492 { } 493 }; 494 MODULE_DEVICE_TABLE(i2c, spd5118_id); 495 496 static const struct of_device_id spd5118_of_ids[] = { 497 { .compatible = "jedec,spd5118", }, 498 { } 499 }; 500 MODULE_DEVICE_TABLE(of, spd5118_of_ids); 501 502 static struct i2c_driver spd5118_driver = { 503 .class = I2C_CLASS_HWMON, 504 .driver = { 505 .name = "spd5118", 506 .of_match_table = spd5118_of_ids, 507 .pm = pm_sleep_ptr(&spd5118_pm_ops), 508 }, 509 .probe = spd5118_probe, 510 .id_table = spd5118_id, 511 .detect = spd5118_detect, 512 .address_list = normal_i2c, 513 }; 514 515 module_i2c_driver(spd5118_driver); 516 517 MODULE_AUTHOR("René Rebe <rene@exactcode.de>"); 518 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>"); 519 MODULE_DESCRIPTION("SPD 5118 driver"); 520 MODULE_LICENSE("GPL"); 521