1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Jedec 5118 compliant temperature sensors 4 * 5 * Derived from https://github.com/Steve-Tech/SPD5118-DKMS 6 * Originally from T/2 driver at https://t2sde.org/packages/linux 7 * Copyright (c) 2023 René Rebe, ExactCODE GmbH; Germany. 8 * 9 * Copyright (c) 2024 Guenter Roeck 10 * 11 * Inspired by ee1004.c and jc42.c. 12 * 13 * SPD5118 compliant temperature sensors are typically used on DDR5 14 * memory modules. 15 */ 16 17 #include <linux/bitops.h> 18 #include <linux/bits.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/i3c/device.h> 22 #include <linux/hwmon.h> 23 #include <linux/module.h> 24 #include <linux/mutex.h> 25 #include <linux/nvmem-provider.h> 26 #include <linux/pm.h> 27 #include <linux/regmap.h> 28 #include <linux/units.h> 29 30 /* Addresses to scan */ 31 static const unsigned short normal_i2c[] = { 32 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, I2C_CLIENT_END }; 33 34 /* SPD5118 registers. */ 35 #define SPD5118_REG_TYPE 0x00 /* MR0:MR1 */ 36 #define SPD5118_REG_REVISION 0x02 /* MR2 */ 37 #define SPD5118_REG_VENDOR 0x03 /* MR3:MR4 */ 38 #define SPD5118_REG_CAPABILITY 0x05 /* MR5 */ 39 #define SPD5118_REG_I2C_LEGACY_MODE 0x0B /* MR11 */ 40 #define SPD5118_REG_TEMP_CLR 0x13 /* MR19 */ 41 #define SPD5118_REG_ERROR_CLR 0x14 /* MR20 */ 42 #define SPD5118_REG_TEMP_CONFIG 0x1A /* MR26 */ 43 #define SPD5118_REG_TEMP_MAX 0x1c /* MR28:MR29 */ 44 #define SPD5118_REG_TEMP_MIN 0x1e /* MR30:MR31 */ 45 #define SPD5118_REG_TEMP_CRIT 0x20 /* MR32:MR33 */ 46 #define SPD5118_REG_TEMP_LCRIT 0x22 /* MR34:MR35 */ 47 #define SPD5118_REG_TEMP 0x31 /* MR49:MR50 */ 48 #define SPD5118_REG_TEMP_STATUS 0x33 /* MR51 */ 49 50 #define SPD5118_TEMP_STATUS_HIGH BIT(0) 51 #define SPD5118_TEMP_STATUS_LOW BIT(1) 52 #define SPD5118_TEMP_STATUS_CRIT BIT(2) 53 #define SPD5118_TEMP_STATUS_LCRIT BIT(3) 54 55 #define SPD5118_CAP_TS_SUPPORT BIT(1) /* temperature sensor support */ 56 57 #define SPD5118_TS_DISABLE BIT(0) /* temperature sensor disable */ 58 59 #define SPD5118_LEGACY_MODE_ADDR BIT(3) 60 #define SPD5118_LEGACY_PAGE_MASK GENMASK(2, 0) 61 #define SPD5118_LEGACY_MODE_MASK (SPD5118_LEGACY_MODE_ADDR | SPD5118_LEGACY_PAGE_MASK) 62 63 #define SPD5118_NUM_PAGES 8 64 #define SPD5118_PAGE_SIZE 128 65 #define SPD5118_PAGE_SHIFT 7 66 #define SPD5118_PAGE_MASK GENMASK(6, 0) 67 #define SPD5118_EEPROM_BASE 0x80 68 #define SPD5118_EEPROM_SIZE (SPD5118_PAGE_SIZE * SPD5118_NUM_PAGES) 69 70 /* Temperature unit in millicelsius */ 71 #define SPD5118_TEMP_UNIT (MILLIDEGREE_PER_DEGREE / 4) 72 /* Representable temperature range in millicelsius */ 73 #define SPD5118_TEMP_RANGE_MIN -256000 74 #define SPD5118_TEMP_RANGE_MAX 255750 75 76 struct spd5118_data { 77 struct regmap *regmap; 78 struct mutex nvmem_lock; 79 }; 80 81 /* hwmon */ 82 83 static int spd5118_temp_from_reg(u16 reg) 84 { 85 int temp = sign_extend32(reg >> 2, 10); 86 87 return temp * SPD5118_TEMP_UNIT; 88 } 89 90 static u16 spd5118_temp_to_reg(long temp) 91 { 92 temp = clamp_val(temp, SPD5118_TEMP_RANGE_MIN, SPD5118_TEMP_RANGE_MAX); 93 return (DIV_ROUND_CLOSEST(temp, SPD5118_TEMP_UNIT) & 0x7ff) << 2; 94 } 95 96 static int spd5118_read_temp(struct regmap *regmap, u32 attr, long *val) 97 { 98 int reg, err; 99 u8 regval[2]; 100 u16 temp; 101 102 switch (attr) { 103 case hwmon_temp_input: 104 reg = SPD5118_REG_TEMP; 105 break; 106 case hwmon_temp_max: 107 reg = SPD5118_REG_TEMP_MAX; 108 break; 109 case hwmon_temp_min: 110 reg = SPD5118_REG_TEMP_MIN; 111 break; 112 case hwmon_temp_crit: 113 reg = SPD5118_REG_TEMP_CRIT; 114 break; 115 case hwmon_temp_lcrit: 116 reg = SPD5118_REG_TEMP_LCRIT; 117 break; 118 default: 119 return -EOPNOTSUPP; 120 } 121 122 err = regmap_bulk_read(regmap, reg, regval, 2); 123 if (err) 124 return err; 125 126 temp = (regval[1] << 8) | regval[0]; 127 128 *val = spd5118_temp_from_reg(temp); 129 return 0; 130 } 131 132 static int spd5118_read_alarm(struct regmap *regmap, u32 attr, long *val) 133 { 134 unsigned int mask, regval; 135 int err; 136 137 switch (attr) { 138 case hwmon_temp_max_alarm: 139 mask = SPD5118_TEMP_STATUS_HIGH; 140 break; 141 case hwmon_temp_min_alarm: 142 mask = SPD5118_TEMP_STATUS_LOW; 143 break; 144 case hwmon_temp_crit_alarm: 145 mask = SPD5118_TEMP_STATUS_CRIT; 146 break; 147 case hwmon_temp_lcrit_alarm: 148 mask = SPD5118_TEMP_STATUS_LCRIT; 149 break; 150 default: 151 return -EOPNOTSUPP; 152 } 153 154 err = regmap_read(regmap, SPD5118_REG_TEMP_STATUS, ®val); 155 if (err < 0) 156 return err; 157 *val = !!(regval & mask); 158 if (*val) 159 return regmap_write(regmap, SPD5118_REG_TEMP_CLR, mask); 160 return 0; 161 } 162 163 static int spd5118_read_enable(struct regmap *regmap, long *val) 164 { 165 u32 regval; 166 int err; 167 168 err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, ®val); 169 if (err < 0) 170 return err; 171 *val = !(regval & SPD5118_TS_DISABLE); 172 return 0; 173 } 174 175 static int spd5118_read(struct device *dev, enum hwmon_sensor_types type, 176 u32 attr, int channel, long *val) 177 { 178 struct regmap *regmap = dev_get_drvdata(dev); 179 180 if (type != hwmon_temp) 181 return -EOPNOTSUPP; 182 183 switch (attr) { 184 case hwmon_temp_input: 185 case hwmon_temp_max: 186 case hwmon_temp_min: 187 case hwmon_temp_crit: 188 case hwmon_temp_lcrit: 189 return spd5118_read_temp(regmap, attr, val); 190 case hwmon_temp_max_alarm: 191 case hwmon_temp_min_alarm: 192 case hwmon_temp_crit_alarm: 193 case hwmon_temp_lcrit_alarm: 194 return spd5118_read_alarm(regmap, attr, val); 195 case hwmon_temp_enable: 196 return spd5118_read_enable(regmap, val); 197 default: 198 return -EOPNOTSUPP; 199 } 200 } 201 202 static int spd5118_write_temp(struct regmap *regmap, u32 attr, long val) 203 { 204 u8 regval[2]; 205 u16 temp; 206 int reg; 207 208 switch (attr) { 209 case hwmon_temp_max: 210 reg = SPD5118_REG_TEMP_MAX; 211 break; 212 case hwmon_temp_min: 213 reg = SPD5118_REG_TEMP_MIN; 214 break; 215 case hwmon_temp_crit: 216 reg = SPD5118_REG_TEMP_CRIT; 217 break; 218 case hwmon_temp_lcrit: 219 reg = SPD5118_REG_TEMP_LCRIT; 220 break; 221 default: 222 return -EOPNOTSUPP; 223 } 224 225 temp = spd5118_temp_to_reg(val); 226 regval[0] = temp & 0xff; 227 regval[1] = temp >> 8; 228 229 return regmap_bulk_write(regmap, reg, regval, 2); 230 } 231 232 static int spd5118_write_enable(struct regmap *regmap, long val) 233 { 234 if (val && val != 1) 235 return -EINVAL; 236 237 return regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG, 238 SPD5118_TS_DISABLE, 239 val ? 0 : SPD5118_TS_DISABLE); 240 } 241 242 static int spd5118_temp_write(struct regmap *regmap, u32 attr, long val) 243 { 244 switch (attr) { 245 case hwmon_temp_max: 246 case hwmon_temp_min: 247 case hwmon_temp_crit: 248 case hwmon_temp_lcrit: 249 return spd5118_write_temp(regmap, attr, val); 250 case hwmon_temp_enable: 251 return spd5118_write_enable(regmap, val); 252 default: 253 return -EOPNOTSUPP; 254 } 255 } 256 257 static int spd5118_write(struct device *dev, enum hwmon_sensor_types type, 258 u32 attr, int channel, long val) 259 { 260 struct regmap *regmap = dev_get_drvdata(dev); 261 262 switch (type) { 263 case hwmon_temp: 264 return spd5118_temp_write(regmap, attr, val); 265 default: 266 return -EOPNOTSUPP; 267 } 268 } 269 270 static umode_t spd5118_is_visible(const void *_data, enum hwmon_sensor_types type, 271 u32 attr, int channel) 272 { 273 if (type != hwmon_temp) 274 return 0; 275 276 switch (attr) { 277 case hwmon_temp_input: 278 return 0444; 279 case hwmon_temp_min: 280 case hwmon_temp_max: 281 case hwmon_temp_lcrit: 282 case hwmon_temp_crit: 283 case hwmon_temp_enable: 284 return 0644; 285 case hwmon_temp_min_alarm: 286 case hwmon_temp_max_alarm: 287 case hwmon_temp_crit_alarm: 288 case hwmon_temp_lcrit_alarm: 289 return 0444; 290 default: 291 return 0; 292 } 293 } 294 295 /* 296 * Bank and vendor id are 8-bit fields with seven data bits and odd parity. 297 * Vendor IDs 0 and 0x7f are invalid. 298 * See Jedec standard JEP106BJ for details and a list of assigned vendor IDs. 299 */ 300 static bool spd5118_vendor_valid(u8 bank, u8 id) 301 { 302 if (parity8(bank) == 0 || parity8(id) == 0) 303 return false; 304 305 id &= 0x7f; 306 return id && id != 0x7f; 307 } 308 309 static const struct hwmon_channel_info *spd5118_info[] = { 310 HWMON_CHANNEL_INFO(chip, 311 HWMON_C_REGISTER_TZ), 312 HWMON_CHANNEL_INFO(temp, 313 HWMON_T_INPUT | 314 HWMON_T_LCRIT | HWMON_T_LCRIT_ALARM | 315 HWMON_T_MIN | HWMON_T_MIN_ALARM | 316 HWMON_T_MAX | HWMON_T_MAX_ALARM | 317 HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 318 HWMON_T_ENABLE), 319 NULL 320 }; 321 322 static const struct hwmon_ops spd5118_hwmon_ops = { 323 .is_visible = spd5118_is_visible, 324 .read = spd5118_read, 325 .write = spd5118_write, 326 }; 327 328 static const struct hwmon_chip_info spd5118_chip_info = { 329 .ops = &spd5118_hwmon_ops, 330 .info = spd5118_info, 331 }; 332 333 /* nvmem */ 334 335 static ssize_t spd5118_nvmem_read_page(struct spd5118_data *data, char *buf, 336 unsigned int offset, size_t count) 337 { 338 int page = offset >> SPD5118_PAGE_SHIFT; 339 struct regmap *regmap = data->regmap; 340 int err, addr; 341 342 offset &= SPD5118_PAGE_MASK; 343 344 /* Can't cross page boundaries */ 345 if (offset + count > SPD5118_PAGE_SIZE) 346 count = SPD5118_PAGE_SIZE - offset; 347 348 addr = page * 0x100 + SPD5118_EEPROM_BASE; 349 err = regmap_bulk_read(regmap, addr + offset, buf, count); 350 if (err) 351 return err; 352 353 return count; 354 } 355 356 static int spd5118_nvmem_read(void *priv, unsigned int off, void *val, size_t count) 357 { 358 struct spd5118_data *data = priv; 359 char *buf = val; 360 int ret; 361 362 if (unlikely(!count)) 363 return count; 364 365 if (off + count > SPD5118_EEPROM_SIZE) 366 return -EINVAL; 367 368 mutex_lock(&data->nvmem_lock); 369 370 while (count) { 371 ret = spd5118_nvmem_read_page(data, buf, off, count); 372 if (ret < 0) { 373 mutex_unlock(&data->nvmem_lock); 374 return ret; 375 } 376 buf += ret; 377 off += ret; 378 count -= ret; 379 } 380 mutex_unlock(&data->nvmem_lock); 381 return 0; 382 } 383 384 static int spd5118_nvmem_init(struct device *dev, struct spd5118_data *data) 385 { 386 struct nvmem_config nvmem_config = { 387 .type = NVMEM_TYPE_EEPROM, 388 .name = dev_name(dev), 389 .id = NVMEM_DEVID_NONE, 390 .dev = dev, 391 .base_dev = dev, 392 .read_only = true, 393 .root_only = false, 394 .owner = THIS_MODULE, 395 .compat = true, 396 .reg_read = spd5118_nvmem_read, 397 .priv = data, 398 .stride = 1, 399 .word_size = 1, 400 .size = SPD5118_EEPROM_SIZE, 401 }; 402 struct nvmem_device *nvmem; 403 404 nvmem = devm_nvmem_register(dev, &nvmem_config); 405 return PTR_ERR_OR_ZERO(nvmem); 406 } 407 408 /* regmap */ 409 410 static bool spd5118_writeable_reg(struct device *dev, unsigned int reg) 411 { 412 switch (reg) { 413 case SPD5118_REG_I2C_LEGACY_MODE: 414 case SPD5118_REG_TEMP_CLR: 415 case SPD5118_REG_TEMP_CONFIG: 416 case SPD5118_REG_TEMP_MAX: 417 case SPD5118_REG_TEMP_MAX + 1: 418 case SPD5118_REG_TEMP_MIN: 419 case SPD5118_REG_TEMP_MIN + 1: 420 case SPD5118_REG_TEMP_CRIT: 421 case SPD5118_REG_TEMP_CRIT + 1: 422 case SPD5118_REG_TEMP_LCRIT: 423 case SPD5118_REG_TEMP_LCRIT + 1: 424 return true; 425 default: 426 return false; 427 } 428 } 429 430 static bool spd5118_volatile_reg(struct device *dev, unsigned int reg) 431 { 432 switch (reg) { 433 case SPD5118_REG_TEMP_CLR: 434 case SPD5118_REG_ERROR_CLR: 435 case SPD5118_REG_TEMP: 436 case SPD5118_REG_TEMP + 1: 437 case SPD5118_REG_TEMP_STATUS: 438 return true; 439 default: 440 return false; 441 } 442 } 443 444 static const struct regmap_range_cfg spd5118_i2c_regmap_range_cfg[] = { 445 { 446 .selector_reg = SPD5118_REG_I2C_LEGACY_MODE, 447 .selector_mask = SPD5118_LEGACY_PAGE_MASK, 448 .selector_shift = 0, 449 .window_start = 0, 450 .window_len = 0x100, 451 .range_min = 0, 452 .range_max = 0x7ff, 453 }, 454 }; 455 456 static const struct regmap_config spd5118_regmap8_config = { 457 .reg_bits = 8, 458 .val_bits = 8, 459 .max_register = 0x7ff, 460 .writeable_reg = spd5118_writeable_reg, 461 .volatile_reg = spd5118_volatile_reg, 462 .cache_type = REGCACHE_MAPLE, 463 464 .ranges = spd5118_i2c_regmap_range_cfg, 465 .num_ranges = ARRAY_SIZE(spd5118_i2c_regmap_range_cfg), 466 }; 467 468 /* 469 * SPD5118 2-byte register address format (JESD300-5, Tables 7 & 20): 470 * Byte 1 (on wire first): MemReg | BlkAddr[0] | Address[5:0] 471 * Byte 2 (on wire second): 0000 | BlkAddr[4:1] 472 * 473 * The address byte (with MemReg and lower address bits) must be sent first, 474 * followed by the upper block address byte. With regmap 16-bit register 475 * format, this maps to little-endian: the low byte of the 16-bit value is 476 * transmitted first. No range config is needed since I3C does not use MR11 477 * page switching. 478 */ 479 static const struct regmap_config spd5118_regmap_i3c_config = { 480 .reg_bits = 16, 481 .val_bits = 8, 482 .max_register = 0x7ff, 483 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 484 .writeable_reg = spd5118_writeable_reg, 485 .volatile_reg = spd5118_volatile_reg, 486 .cache_type = REGCACHE_MAPLE, 487 }; 488 489 static int spd5118_suspend(struct device *dev) 490 { 491 struct spd5118_data *data = dev_get_drvdata(dev); 492 struct regmap *regmap = data->regmap; 493 u32 regval; 494 int err; 495 496 /* 497 * Make sure the configuration register in the regmap cache is current 498 * before bypassing it. 499 */ 500 err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, ®val); 501 if (err < 0) 502 return err; 503 504 regcache_cache_bypass(regmap, true); 505 regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG, SPD5118_TS_DISABLE, 506 SPD5118_TS_DISABLE); 507 regcache_cache_bypass(regmap, false); 508 509 regcache_cache_only(regmap, true); 510 regcache_mark_dirty(regmap); 511 512 return 0; 513 } 514 515 static int spd5118_resume(struct device *dev) 516 { 517 struct spd5118_data *data = dev_get_drvdata(dev); 518 struct regmap *regmap = data->regmap; 519 520 regcache_cache_only(regmap, false); 521 return regcache_sync(regmap); 522 } 523 524 static DEFINE_SIMPLE_DEV_PM_OPS(spd5118_pm_ops, spd5118_suspend, spd5118_resume); 525 526 static int spd5118_common_probe(struct device *dev, struct regmap *regmap) 527 { 528 unsigned int capability, revision, vendor, bank; 529 struct spd5118_data *data; 530 struct device *hwmon_dev; 531 int err; 532 533 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 534 if (!data) 535 return -ENOMEM; 536 537 err = regmap_read(regmap, SPD5118_REG_CAPABILITY, &capability); 538 if (err) 539 return err; 540 if (!(capability & SPD5118_CAP_TS_SUPPORT)) 541 return -ENODEV; 542 543 err = regmap_read(regmap, SPD5118_REG_REVISION, &revision); 544 if (err) 545 return err; 546 547 err = regmap_read(regmap, SPD5118_REG_VENDOR, &bank); 548 if (err) 549 return err; 550 err = regmap_read(regmap, SPD5118_REG_VENDOR + 1, &vendor); 551 if (err) 552 return err; 553 if (!spd5118_vendor_valid(bank, vendor)) 554 return -ENODEV; 555 556 data->regmap = regmap; 557 mutex_init(&data->nvmem_lock); 558 dev_set_drvdata(dev, data); 559 560 err = spd5118_nvmem_init(dev, data); 561 /* Ignore if NVMEM support is disabled */ 562 if (err && err != -EOPNOTSUPP) { 563 dev_err_probe(dev, err, "failed to register nvmem\n"); 564 return err; 565 } 566 567 hwmon_dev = devm_hwmon_device_register_with_info(dev, "spd5118", 568 regmap, &spd5118_chip_info, 569 NULL); 570 if (IS_ERR(hwmon_dev)) 571 return PTR_ERR(hwmon_dev); 572 573 /* 574 * From JESD300-5B 575 * MR2 bits [5:4]: Major revision, 1..4 576 * MR2 bits [3:1]: Minor revision, 0..8? Probably a typo, assume 1..8 577 */ 578 dev_info(dev, "DDR5 temperature sensor: vendor 0x%02x:0x%02x revision %d.%d\n", 579 bank & 0x7f, vendor, ((revision >> 4) & 0x03) + 1, ((revision >> 1) & 0x07) + 1); 580 581 return 0; 582 } 583 584 /* I2C */ 585 586 /* Return 0 if detection is successful, -ENODEV otherwise */ 587 static int spd5118_detect(struct i2c_client *client, struct i2c_board_info *info) 588 { 589 struct i2c_adapter *adapter = client->adapter; 590 int regval; 591 592 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | 593 I2C_FUNC_SMBUS_WORD_DATA)) 594 return -ENODEV; 595 596 regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); 597 if (regval != 0x5118) 598 return -ENODEV; 599 600 regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR); 601 if (regval < 0 || !spd5118_vendor_valid(regval & 0xff, regval >> 8)) 602 return -ENODEV; 603 604 regval = i2c_smbus_read_byte_data(client, SPD5118_REG_CAPABILITY); 605 if (regval < 0) 606 return -ENODEV; 607 if (!(regval & SPD5118_CAP_TS_SUPPORT) || (regval & 0xfc)) 608 return -ENODEV; 609 610 regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CLR); 611 if (regval) 612 return -ENODEV; 613 regval = i2c_smbus_read_byte_data(client, SPD5118_REG_ERROR_CLR); 614 if (regval) 615 return -ENODEV; 616 617 regval = i2c_smbus_read_byte_data(client, SPD5118_REG_REVISION); 618 if (regval < 0 || (regval & 0xc1)) 619 return -ENODEV; 620 621 regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CONFIG); 622 if (regval < 0) 623 return -ENODEV; 624 if (regval & ~SPD5118_TS_DISABLE) 625 return -ENODEV; 626 627 strscpy(info->type, "spd5118", I2C_NAME_SIZE); 628 return 0; 629 } 630 631 static int spd5118_i2c_init(struct i2c_client *client) 632 { 633 struct i2c_adapter *adapter = client->adapter; 634 int err, regval, mode; 635 636 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | 637 I2C_FUNC_SMBUS_WORD_DATA)) 638 return -ENODEV; 639 640 regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); 641 if (regval < 0 || (regval && regval != 0x5118)) 642 return -ENODEV; 643 644 /* 645 * If the device type registers return 0, it is possible that the chip 646 * has a non-zero page selected and takes the specification literally, 647 * i.e. disables access to volatile registers besides the page register 648 * if the page is not 0. The Renesas/ITD SPD5118 Hub Controller is known 649 * to show this behavior. Try to identify such chips. 650 */ 651 if (!regval) { 652 /* Vendor ID registers must also be 0 */ 653 regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR); 654 if (regval) 655 return -ENODEV; 656 657 /* The selected page in MR11 must not be 0 */ 658 mode = i2c_smbus_read_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE); 659 if (mode < 0 || (mode & ~SPD5118_LEGACY_MODE_MASK) || 660 !(mode & SPD5118_LEGACY_PAGE_MASK)) 661 return -ENODEV; 662 663 err = i2c_smbus_write_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE, 664 mode & SPD5118_LEGACY_MODE_ADDR); 665 if (err) 666 return -ENODEV; 667 668 /* 669 * If the device type registers are still bad after selecting 670 * page 0, this is not a SPD5118 device. Restore original 671 * legacy mode register value and abort. 672 */ 673 regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); 674 if (regval != 0x5118) { 675 i2c_smbus_write_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE, mode); 676 return -ENODEV; 677 } 678 } 679 680 /* We are reasonably sure that this is really a SPD5118 hub controller */ 681 return 0; 682 } 683 684 static int spd5118_i2c_probe(struct i2c_client *client) 685 { 686 struct device *dev = &client->dev; 687 struct regmap *regmap; 688 int err; 689 690 err = spd5118_i2c_init(client); 691 if (err) 692 return err; 693 694 regmap = devm_regmap_init_i2c(client, &spd5118_regmap8_config); 695 if (IS_ERR(regmap)) 696 return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n"); 697 698 return spd5118_common_probe(dev, regmap); 699 } 700 701 static const struct i2c_device_id spd5118_i2c_id[] = { 702 { .name = "spd5118" }, 703 { } 704 }; 705 MODULE_DEVICE_TABLE(i2c, spd5118_i2c_id); 706 707 static const struct of_device_id spd5118_of_ids[] = { 708 { .compatible = "jedec,spd5118", }, 709 { } 710 }; 711 MODULE_DEVICE_TABLE(of, spd5118_of_ids); 712 713 static struct i2c_driver spd5118_i2c_driver = { 714 .class = I2C_CLASS_HWMON, 715 .driver = { 716 .name = "spd5118", 717 .of_match_table = spd5118_of_ids, 718 .pm = pm_sleep_ptr(&spd5118_pm_ops), 719 }, 720 .probe = spd5118_i2c_probe, 721 .id_table = spd5118_i2c_id, 722 .detect = IS_ENABLED(CONFIG_SENSORS_SPD5118_DETECT) ? spd5118_detect : NULL, 723 .address_list = IS_ENABLED(CONFIG_SENSORS_SPD5118_DETECT) ? normal_i2c : NULL, 724 }; 725 726 /* I3C */ 727 728 static int spd5118_i3c_probe(struct i3c_device *i3cdev) 729 { 730 struct device *dev = i3cdev_to_dev(i3cdev); 731 struct regmap *regmap; 732 u8 regval[2]; 733 int err; 734 735 regmap = devm_regmap_init_i3c(i3cdev, &spd5118_regmap_i3c_config); 736 if (IS_ERR(regmap)) 737 return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n"); 738 739 err = regmap_bulk_read(regmap, SPD5118_REG_TYPE, regval, 2); 740 if (err) 741 return dev_err_probe(dev, err, "failed to read device type\n"); 742 743 if (regval[0] != 0x51 || regval[1] != 0x18) 744 return -ENODEV; 745 746 return spd5118_common_probe(dev, regmap); 747 } 748 749 static struct i3c_driver spd5118_i3c_driver = { 750 .driver = { 751 .name = "spd5118_i3c", 752 .of_match_table = spd5118_of_ids, 753 .pm = pm_sleep_ptr(&spd5118_pm_ops), 754 }, 755 .probe = spd5118_i3c_probe, 756 }; 757 758 module_i3c_i2c_driver(spd5118_i3c_driver, &spd5118_i2c_driver); 759 760 MODULE_AUTHOR("René Rebe <rene@exactcode.de>"); 761 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>"); 762 MODULE_DESCRIPTION("SPD 5118 driver"); 763 MODULE_LICENSE("GPL"); 764