1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Altera SoC FPGA hardware monitoring driver 4 * 5 * Copyright (c) 2026 Altera Corporation 6 * 7 * Authors: 8 * Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> 9 * Tze Yee Ng <tze.yee.ng@altera.com> 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/cleanup.h> 14 #include <linux/completion.h> 15 #include <linux/delay.h> 16 #include <linux/firmware/intel/stratix10-svc-client.h> 17 #include <linux/hwmon.h> 18 #include <linux/hwmon-sysfs.h> 19 #include <linux/jiffies.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 25 #define HWMON_TIMEOUT msecs_to_jiffies(SVC_HWMON_REQUEST_TIMEOUT_MS) 26 #define HWMON_RETRY_SLEEP_US 1000U 27 #define HWMON_ASYNC_MSG_RETRY 3U 28 #define SOCFPGA_HWMON_MAXSENSORS 16 29 #define SOCFPGA_HWMON_CHANNEL_MASK GENMASK(15, 0) 30 #define SOCFPGA_HWMON_PAGE_SHIFT 16 31 #define SOCFPGA_HWMON_CHAN(page, channel) \ 32 (((page) << SOCFPGA_HWMON_PAGE_SHIFT) | \ 33 ((channel) & SOCFPGA_HWMON_CHANNEL_MASK)) 34 #define SOCFPGA_HWMON_ATTR_VISIBLE 0444 35 /* Temperature from SDM is signed Q8.8 degrees Celsius (8 fractional bits). */ 36 #define SOCFPGA_HWMON_TEMP_FRAC_BITS 8 37 #define SOCFPGA_HWMON_TEMP_FRAC_DIV BIT(SOCFPGA_HWMON_TEMP_FRAC_BITS) 38 #define SOCFPGA_HWMON_TEMP_MDEG_SCALE 1000 39 /* Voltage from SDM is unsigned Q16 volts (16 fractional bits). */ 40 #define SOCFPGA_HWMON_VOLT_FRAC_BITS 16 41 #define SOCFPGA_HWMON_VOLT_FRAC_DIV BIT(SOCFPGA_HWMON_VOLT_FRAC_BITS) 42 #define SOCFPGA_HWMON_VOLT_MV_SCALE 1000 43 44 #define ETEMP_INACTIVE 0x80000000U 45 #define ETEMP_TOO_OLD 0x80000001U 46 #define ETEMP_NOT_PRESENT 0x80000002U 47 #define ETEMP_TIMEOUT 0x80000003U 48 #define ETEMP_CORRUPT 0x80000004U 49 #define ETEMP_BUSY 0x80000005U 50 #define ETEMP_NOT_INITIALIZED 0x800000FFU 51 52 struct socfpga_hwmon_channel { 53 u32 reg; 54 const char *label; 55 }; 56 57 struct socfpga_hwmon_board_data { 58 const struct socfpga_hwmon_channel *temp; 59 unsigned int num_temp; 60 const struct socfpga_hwmon_channel *volt; 61 unsigned int num_volt; 62 }; 63 64 struct socfpga_hwmon_priv { 65 struct stratix10_svc_chan *chan; 66 struct stratix10_svc_client client; 67 struct completion completion; 68 struct mutex lock; /* protect SVC calls */ 69 bool async; 70 int last_err; /* sync-mode SVC result; 0 on success */ 71 u32 temperature; 72 u32 voltage; 73 int temperature_channels; 74 int voltage_channels; 75 const char *temp_chan_names[SOCFPGA_HWMON_MAXSENSORS]; 76 const char *volt_chan_names[SOCFPGA_HWMON_MAXSENSORS]; 77 u32 temp_chan[SOCFPGA_HWMON_MAXSENSORS]; 78 u32 volt_chan[SOCFPGA_HWMON_MAXSENSORS]; 79 }; 80 81 static umode_t socfpga_hwmon_is_visible(const void *dev, 82 enum hwmon_sensor_types type, 83 u32 attr, int chan) 84 { 85 const struct socfpga_hwmon_priv *priv = dev; 86 87 switch (type) { 88 case hwmon_temp: 89 if (chan < priv->temperature_channels) 90 return SOCFPGA_HWMON_ATTR_VISIBLE; 91 return 0; 92 case hwmon_in: 93 if (chan < priv->voltage_channels) 94 return SOCFPGA_HWMON_ATTR_VISIBLE; 95 return 0; 96 default: 97 return 0; 98 } 99 } 100 101 static void socfpga_hwmon_readtemp_cb(struct stratix10_svc_client *client, 102 struct stratix10_svc_cb_data *data) 103 { 104 struct socfpga_hwmon_priv *priv = client->priv; 105 106 priv->last_err = -EIO; 107 if (data->status == BIT(SVC_STATUS_OK)) { 108 priv->last_err = 0; 109 priv->temperature = (u32)*(unsigned long *)data->kaddr1; 110 } else if (data->kaddr1) { 111 dev_err(client->dev, "%s failed with status 0x%x, value 0x%lx\n", 112 __func__, data->status, 113 *(unsigned long *)data->kaddr1); 114 } else { 115 dev_err(client->dev, "%s failed with status 0x%x\n", 116 __func__, data->status); 117 } 118 119 complete(&priv->completion); 120 } 121 122 static void socfpga_hwmon_readvolt_cb(struct stratix10_svc_client *client, 123 struct stratix10_svc_cb_data *data) 124 { 125 struct socfpga_hwmon_priv *priv = client->priv; 126 127 priv->last_err = -EIO; 128 if (data->status == BIT(SVC_STATUS_OK)) { 129 priv->last_err = 0; 130 priv->voltage = (u32)*(unsigned long *)data->kaddr1; 131 } else if (data->kaddr1) { 132 dev_err(client->dev, "%s failed with status 0x%x, value 0x%lx\n", 133 __func__, data->status, 134 *(unsigned long *)data->kaddr1); 135 } else { 136 dev_err(client->dev, "%s failed with status 0x%x\n", 137 __func__, data->status); 138 } 139 140 complete(&priv->completion); 141 } 142 143 static int socfpga_hwmon_parse_temp(long *val, u32 temperature) 144 { 145 switch (temperature) { 146 case ETEMP_INACTIVE: 147 case ETEMP_NOT_PRESENT: 148 case ETEMP_CORRUPT: 149 case ETEMP_NOT_INITIALIZED: 150 return -EOPNOTSUPP; 151 case ETEMP_TIMEOUT: 152 case ETEMP_BUSY: 153 case ETEMP_TOO_OLD: 154 return -EAGAIN; 155 default: 156 /* SDM returns a 16-bit signed Q8.8 value in the low 16 bits. */ 157 *val = (long)(s16)(temperature & SOCFPGA_HWMON_CHANNEL_MASK) * 158 SOCFPGA_HWMON_TEMP_MDEG_SCALE / SOCFPGA_HWMON_TEMP_FRAC_DIV; 159 return 0; 160 } 161 } 162 163 static int socfpga_hwmon_encode_temp_arg(u32 reg, u64 *arg) 164 { 165 u32 page = (reg >> SOCFPGA_HWMON_PAGE_SHIFT) & SOCFPGA_HWMON_CHANNEL_MASK; 166 u32 channel = reg & SOCFPGA_HWMON_CHANNEL_MASK; 167 168 if (channel >= SOCFPGA_HWMON_MAXSENSORS) 169 return -EINVAL; 170 171 *arg = (1ULL << channel) | ((u64)page << SOCFPGA_HWMON_PAGE_SHIFT); 172 return 0; 173 } 174 175 static int socfpga_hwmon_encode_volt_arg(u32 reg, u64 *arg) 176 { 177 u32 channel = reg & SOCFPGA_HWMON_CHANNEL_MASK; 178 179 if (channel >= SOCFPGA_HWMON_MAXSENSORS) 180 return -EINVAL; 181 182 *arg = 1ULL << channel; 183 return 0; 184 } 185 186 static int socfpga_hwmon_async_read(struct device *dev, 187 enum hwmon_sensor_types type, 188 struct stratix10_svc_client_msg *msg) 189 { 190 struct socfpga_hwmon_priv *priv = dev_get_drvdata(dev); 191 struct stratix10_svc_cb_data data = {}; 192 unsigned long deadline = jiffies + HWMON_TIMEOUT; 193 void *handle = NULL; 194 int status, index, ret; 195 196 for (index = 0; index < HWMON_ASYNC_MSG_RETRY; index++) { 197 status = stratix10_svc_async_send(priv->chan, msg, &handle, 198 NULL, NULL); 199 if (status == 0) 200 break; 201 dev_warn(dev, "Failed to send async message: %d\n", status); 202 usleep_range(HWMON_RETRY_SLEEP_US, HWMON_RETRY_SLEEP_US * 2); 203 } 204 205 if (status && !handle) { 206 dev_err(dev, "Failed to send async message after %u retries: %d\n", 207 HWMON_ASYNC_MSG_RETRY, status); 208 return status; 209 } 210 211 ret = -ETIMEDOUT; 212 while (!time_after(jiffies, deadline)) { 213 status = stratix10_svc_async_poll(priv->chan, handle, &data); 214 if (status == -EAGAIN) { 215 /* still in progress */ 216 } else if (status < 0) { 217 ret = status; 218 break; 219 } else if (status == 0) { 220 ret = 0; 221 break; 222 } 223 usleep_range(HWMON_RETRY_SLEEP_US, HWMON_RETRY_SLEEP_US * 2); 224 } 225 226 if (ret) { 227 dev_err(dev, "Failed to get async response\n"); 228 goto done; 229 } 230 231 if (data.status) { 232 dev_err(dev, "%s returned 0x%x from SDM\n", __func__, 233 data.status); 234 ret = -EFAULT; 235 goto done; 236 } 237 238 if (type == hwmon_temp) 239 priv->temperature = (u32)*(unsigned long *)data.kaddr1; 240 else 241 priv->voltage = (u32)*(unsigned long *)data.kaddr1; 242 243 ret = 0; 244 245 done: 246 stratix10_svc_async_done(priv->chan, handle); 247 return ret; 248 } 249 250 static int socfpga_hwmon_sync_read(struct device *dev, 251 enum hwmon_sensor_types type, 252 struct stratix10_svc_client_msg *msg) 253 { 254 struct socfpga_hwmon_priv *priv = dev_get_drvdata(dev); 255 int ret; 256 257 reinit_completion(&priv->completion); 258 259 if (type == hwmon_temp) 260 priv->client.receive_cb = socfpga_hwmon_readtemp_cb; 261 else 262 priv->client.receive_cb = socfpga_hwmon_readvolt_cb; 263 264 ret = stratix10_svc_send(priv->chan, msg); 265 if (ret < 0) 266 goto status_done; 267 268 ret = wait_for_completion_timeout(&priv->completion, HWMON_TIMEOUT); 269 if (!ret) { 270 dev_err(priv->client.dev, "timeout waiting for SMC call\n"); 271 ret = -ETIMEDOUT; 272 goto status_done; 273 } 274 275 ret = priv->last_err; 276 277 status_done: 278 stratix10_svc_done(priv->chan); 279 return ret; 280 } 281 282 static int socfpga_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 283 u32 attr, int chan, long *val) 284 { 285 struct socfpga_hwmon_priv *priv = dev_get_drvdata(dev); 286 struct stratix10_svc_client_msg msg = {0}; 287 int ret; 288 289 if (chan >= SOCFPGA_HWMON_MAXSENSORS) 290 return -EOPNOTSUPP; 291 292 switch (type) { 293 case hwmon_temp: 294 ret = socfpga_hwmon_encode_temp_arg(priv->temp_chan[chan], 295 &msg.arg[0]); 296 if (ret) 297 return ret; 298 msg.command = COMMAND_HWMON_READTEMP; 299 break; 300 case hwmon_in: 301 ret = socfpga_hwmon_encode_volt_arg(priv->volt_chan[chan], 302 &msg.arg[0]); 303 if (ret) 304 return ret; 305 msg.command = COMMAND_HWMON_READVOLT; 306 break; 307 default: 308 return -EOPNOTSUPP; 309 } 310 311 guard(mutex)(&priv->lock); 312 if (priv->async) 313 ret = socfpga_hwmon_async_read(dev, type, &msg); 314 else 315 ret = socfpga_hwmon_sync_read(dev, type, &msg); 316 if (ret) 317 return ret; 318 319 if (type == hwmon_temp) 320 ret = socfpga_hwmon_parse_temp(val, priv->temperature); 321 else 322 /* SDM returns Q16 volts; convert to hwmon millivolts. */ 323 *val = (long)priv->voltage * SOCFPGA_HWMON_VOLT_MV_SCALE / 324 SOCFPGA_HWMON_VOLT_FRAC_DIV; 325 return ret; 326 } 327 328 static int socfpga_hwmon_read_string(struct device *dev, 329 enum hwmon_sensor_types type, u32 attr, 330 int chan, const char **str) 331 { 332 struct socfpga_hwmon_priv *priv = dev_get_drvdata(dev); 333 334 switch (type) { 335 case hwmon_in: 336 *str = priv->volt_chan_names[chan]; 337 return 0; 338 case hwmon_temp: 339 *str = priv->temp_chan_names[chan]; 340 return 0; 341 default: 342 return -EOPNOTSUPP; 343 } 344 } 345 346 static const struct hwmon_ops socfpga_hwmon_ops = { 347 .is_visible = socfpga_hwmon_is_visible, 348 .read = socfpga_hwmon_read, 349 .read_string = socfpga_hwmon_read_string, 350 }; 351 352 static const struct hwmon_channel_info *socfpga_hwmon_info[] = { 353 HWMON_CHANNEL_INFO(temp, 354 HWMON_T_INPUT | HWMON_T_LABEL, 355 HWMON_T_INPUT | HWMON_T_LABEL, 356 HWMON_T_INPUT | HWMON_T_LABEL, 357 HWMON_T_INPUT | HWMON_T_LABEL, 358 HWMON_T_INPUT | HWMON_T_LABEL, 359 HWMON_T_INPUT | HWMON_T_LABEL, 360 HWMON_T_INPUT | HWMON_T_LABEL, 361 HWMON_T_INPUT | HWMON_T_LABEL, 362 HWMON_T_INPUT | HWMON_T_LABEL, 363 HWMON_T_INPUT | HWMON_T_LABEL, 364 HWMON_T_INPUT | HWMON_T_LABEL, 365 HWMON_T_INPUT | HWMON_T_LABEL, 366 HWMON_T_INPUT | HWMON_T_LABEL, 367 HWMON_T_INPUT | HWMON_T_LABEL, 368 HWMON_T_INPUT | HWMON_T_LABEL, 369 HWMON_T_INPUT | HWMON_T_LABEL), 370 HWMON_CHANNEL_INFO(in, 371 HWMON_I_INPUT | HWMON_I_LABEL, 372 HWMON_I_INPUT | HWMON_I_LABEL, 373 HWMON_I_INPUT | HWMON_I_LABEL, 374 HWMON_I_INPUT | HWMON_I_LABEL, 375 HWMON_I_INPUT | HWMON_I_LABEL, 376 HWMON_I_INPUT | HWMON_I_LABEL, 377 HWMON_I_INPUT | HWMON_I_LABEL, 378 HWMON_I_INPUT | HWMON_I_LABEL, 379 HWMON_I_INPUT | HWMON_I_LABEL, 380 HWMON_I_INPUT | HWMON_I_LABEL, 381 HWMON_I_INPUT | HWMON_I_LABEL, 382 HWMON_I_INPUT | HWMON_I_LABEL, 383 HWMON_I_INPUT | HWMON_I_LABEL, 384 HWMON_I_INPUT | HWMON_I_LABEL, 385 HWMON_I_INPUT | HWMON_I_LABEL, 386 HWMON_I_INPUT | HWMON_I_LABEL), 387 NULL 388 }; 389 390 static const struct hwmon_chip_info socfpga_hwmon_chip_info = { 391 .ops = &socfpga_hwmon_ops, 392 .info = socfpga_hwmon_info, 393 }; 394 395 static const struct socfpga_hwmon_channel s10_hwmon_volt_channels[] = { 396 { SOCFPGA_HWMON_CHAN(0, 2), "0.8V VCC" }, 397 { SOCFPGA_HWMON_CHAN(0, 3), "1.8V VCCIO_SDM" }, 398 { SOCFPGA_HWMON_CHAN(0, 6), "0.9V VCCERAM" }, 399 }; 400 401 static const struct socfpga_hwmon_channel s10_hwmon_temp_channels[] = { 402 { SOCFPGA_HWMON_CHAN(0, 0), "Main Die SDM" }, 403 }; 404 405 static const struct socfpga_hwmon_board_data s10_hwmon_board = { 406 .temp = s10_hwmon_temp_channels, 407 .num_temp = ARRAY_SIZE(s10_hwmon_temp_channels), 408 .volt = s10_hwmon_volt_channels, 409 .num_volt = ARRAY_SIZE(s10_hwmon_volt_channels), 410 }; 411 412 static const struct socfpga_hwmon_channel agilex_hwmon_volt_channels[] = { 413 { SOCFPGA_HWMON_CHAN(0, 2), "0.8V VCC" }, 414 { SOCFPGA_HWMON_CHAN(0, 3), "1.8V VCCIO_SDM" }, 415 { SOCFPGA_HWMON_CHAN(0, 4), "1.8V VCCPT" }, 416 { SOCFPGA_HWMON_CHAN(0, 5), "1.2V VCCCRCORE" }, 417 { SOCFPGA_HWMON_CHAN(0, 6), "0.9V VCCH" }, 418 { SOCFPGA_HWMON_CHAN(0, 7), "0.8V VCCL" }, 419 }; 420 421 static const struct socfpga_hwmon_channel agilex_hwmon_temp_channels[] = { 422 { SOCFPGA_HWMON_CHAN(0, 0), "Main Die SDM" }, 423 { SOCFPGA_HWMON_CHAN(1, 0), "Main Die corner bottom left max" }, 424 { SOCFPGA_HWMON_CHAN(2, 0), "Main Die corner top left max" }, 425 { SOCFPGA_HWMON_CHAN(3, 0), "Main Die corner bottom right max" }, 426 { SOCFPGA_HWMON_CHAN(4, 0), "Main Die corner top right max" }, 427 }; 428 429 static const struct socfpga_hwmon_board_data agilex_hwmon_board = { 430 .temp = agilex_hwmon_temp_channels, 431 .num_temp = ARRAY_SIZE(agilex_hwmon_temp_channels), 432 .volt = agilex_hwmon_volt_channels, 433 .num_volt = ARRAY_SIZE(agilex_hwmon_volt_channels), 434 }; 435 436 static const struct socfpga_hwmon_board_data * 437 socfpga_hwmon_get_board(struct device *dev) 438 { 439 struct device_node *np = dev->of_node; 440 441 if (!np) 442 return NULL; 443 444 if (of_device_is_compatible(np, "intel,stratix10-svc")) 445 return &s10_hwmon_board; 446 if (of_device_is_compatible(np, "intel,agilex-svc")) 447 return &agilex_hwmon_board; 448 449 return NULL; 450 } 451 452 static int socfpga_hwmon_init_channels(struct device *dev, 453 const struct socfpga_hwmon_board_data *board, 454 struct socfpga_hwmon_priv *priv) 455 { 456 unsigned int i; 457 458 if (board->num_temp > SOCFPGA_HWMON_MAXSENSORS || 459 board->num_volt > SOCFPGA_HWMON_MAXSENSORS) 460 return -EINVAL; 461 462 for (i = 0; i < board->num_temp; i++) { 463 priv->temp_chan_names[i] = board->temp[i].label; 464 priv->temp_chan[i] = board->temp[i].reg; 465 } 466 priv->temperature_channels = board->num_temp; 467 468 for (i = 0; i < board->num_volt; i++) { 469 priv->volt_chan_names[i] = board->volt[i].label; 470 priv->volt_chan[i] = board->volt[i].reg; 471 } 472 priv->voltage_channels = board->num_volt; 473 474 return 0; 475 } 476 477 static void socfpga_hwmon_release_svc(void *data) 478 { 479 struct socfpga_hwmon_priv *priv = data; 480 481 if (priv->async) 482 stratix10_svc_remove_async_client(priv->chan); 483 stratix10_svc_free_channel(priv->chan); 484 } 485 486 static int socfpga_hwmon_probe(struct platform_device *pdev) 487 { 488 struct device *dev = &pdev->dev; 489 struct device *parent = dev->parent; 490 const struct socfpga_hwmon_board_data *board; 491 struct socfpga_hwmon_priv *priv; 492 struct device *hwmon_dev; 493 int ret; 494 495 if (!parent || !parent->of_node) { 496 dev_err(dev, "missing parent device node\n"); 497 return -ENODEV; 498 } 499 500 board = socfpga_hwmon_get_board(parent); 501 if (!board) { 502 dev_err(dev, "unsupported service layer compatible\n"); 503 return -ENODEV; 504 } 505 506 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 507 if (!priv) 508 return -ENOMEM; 509 510 priv->client.dev = dev; 511 priv->client.priv = priv; 512 init_completion(&priv->completion); 513 mutex_init(&priv->lock); 514 515 ret = socfpga_hwmon_init_channels(dev, board, priv); 516 if (ret) 517 return ret; 518 519 priv->chan = stratix10_svc_request_channel_byname(&priv->client, 520 SVC_CLIENT_HWMON); 521 if (IS_ERR(priv->chan)) { 522 ret = PTR_ERR(priv->chan); 523 if (ret == -EPROBE_DEFER) 524 dev_dbg(dev, "service channel %s not ready, deferring probe\n", 525 SVC_CLIENT_HWMON); 526 else 527 dev_err(dev, "couldn't get service channel %s: %d\n", 528 SVC_CLIENT_HWMON, ret); 529 return ret; 530 } 531 532 ret = stratix10_svc_add_async_client(priv->chan, false); 533 switch (ret) { 534 case 0: 535 priv->async = true; 536 break; 537 case -EINVAL: 538 case -EOPNOTSUPP: 539 /* 540 * stratix10_svc_add_async_client() returns -EINVAL when the 541 * async controller is not initialized; fall back to sync mode. 542 */ 543 dev_dbg(dev, "async operations not supported, using sync mode\n"); 544 priv->async = false; 545 break; 546 default: 547 dev_err(dev, "failed to add async client: %d\n", ret); 548 stratix10_svc_free_channel(priv->chan); 549 return ret; 550 } 551 552 ret = devm_add_action_or_reset(dev, socfpga_hwmon_release_svc, priv); 553 if (ret) 554 return ret; 555 556 hwmon_dev = devm_hwmon_device_register_with_info(dev, "socfpga_hwmon", 557 priv, 558 &socfpga_hwmon_chip_info, 559 NULL); 560 if (IS_ERR(hwmon_dev)) 561 return PTR_ERR(hwmon_dev); 562 563 platform_set_drvdata(pdev, priv); 564 return 0; 565 } 566 567 static struct platform_driver socfpga_hwmon_driver = { 568 .probe = socfpga_hwmon_probe, 569 .driver = { 570 .name = "socfpga-hwmon", 571 }, 572 }; 573 module_platform_driver(socfpga_hwmon_driver); 574 575 MODULE_AUTHOR("Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>"); 576 MODULE_AUTHOR("Tze Yee Ng <tze.yee.ng@altera.com>"); 577 MODULE_DESCRIPTION("Altera SoC FPGA hardware monitoring driver"); 578 MODULE_LICENSE("GPL"); 579 MODULE_ALIAS("platform:socfpga-hwmon"); 580