1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * pmbus.h - Common defines and structures for PMBus devices 4 * 5 * Copyright (c) 2010, 2011 Ericsson AB. 6 * Copyright (c) 2012 Guenter Roeck 7 */ 8 9 #ifndef PMBUS_H 10 #define PMBUS_H 11 12 #include <linux/bitops.h> 13 #include <linux/regulator/driver.h> 14 15 /* 16 * Registers 17 */ 18 enum pmbus_regs { 19 PMBUS_PAGE = 0x00, 20 PMBUS_OPERATION = 0x01, 21 PMBUS_ON_OFF_CONFIG = 0x02, 22 PMBUS_CLEAR_FAULTS = 0x03, 23 PMBUS_PHASE = 0x04, 24 25 PMBUS_WRITE_PROTECT = 0x10, 26 27 PMBUS_CAPABILITY = 0x19, 28 PMBUS_QUERY = 0x1A, 29 PMBUS_SMBALERT_MASK = 0x1B, 30 PMBUS_VOUT_MODE = 0x20, 31 PMBUS_VOUT_COMMAND = 0x21, 32 PMBUS_VOUT_TRIM = 0x22, 33 PMBUS_VOUT_CAL_OFFSET = 0x23, 34 PMBUS_VOUT_MAX = 0x24, 35 PMBUS_VOUT_MARGIN_HIGH = 0x25, 36 PMBUS_VOUT_MARGIN_LOW = 0x26, 37 PMBUS_VOUT_TRANSITION_RATE = 0x27, 38 PMBUS_VOUT_DROOP = 0x28, 39 PMBUS_VOUT_SCALE_LOOP = 0x29, 40 PMBUS_VOUT_SCALE_MONITOR = 0x2A, 41 42 PMBUS_COEFFICIENTS = 0x30, 43 PMBUS_POUT_MAX = 0x31, 44 45 PMBUS_FAN_CONFIG_12 = 0x3A, 46 PMBUS_FAN_COMMAND_1 = 0x3B, 47 PMBUS_FAN_COMMAND_2 = 0x3C, 48 PMBUS_FAN_CONFIG_34 = 0x3D, 49 PMBUS_FAN_COMMAND_3 = 0x3E, 50 PMBUS_FAN_COMMAND_4 = 0x3F, 51 52 PMBUS_VOUT_OV_FAULT_LIMIT = 0x40, 53 PMBUS_VOUT_OV_FAULT_RESPONSE = 0x41, 54 PMBUS_VOUT_OV_WARN_LIMIT = 0x42, 55 PMBUS_VOUT_UV_WARN_LIMIT = 0x43, 56 PMBUS_VOUT_UV_FAULT_LIMIT = 0x44, 57 PMBUS_VOUT_UV_FAULT_RESPONSE = 0x45, 58 PMBUS_IOUT_OC_FAULT_LIMIT = 0x46, 59 PMBUS_IOUT_OC_FAULT_RESPONSE = 0x47, 60 PMBUS_IOUT_OC_LV_FAULT_LIMIT = 0x48, 61 PMBUS_IOUT_OC_LV_FAULT_RESPONSE = 0x49, 62 PMBUS_IOUT_OC_WARN_LIMIT = 0x4A, 63 PMBUS_IOUT_UC_FAULT_LIMIT = 0x4B, 64 PMBUS_IOUT_UC_FAULT_RESPONSE = 0x4C, 65 66 PMBUS_OT_FAULT_LIMIT = 0x4F, 67 PMBUS_OT_FAULT_RESPONSE = 0x50, 68 PMBUS_OT_WARN_LIMIT = 0x51, 69 PMBUS_UT_WARN_LIMIT = 0x52, 70 PMBUS_UT_FAULT_LIMIT = 0x53, 71 PMBUS_UT_FAULT_RESPONSE = 0x54, 72 PMBUS_VIN_OV_FAULT_LIMIT = 0x55, 73 PMBUS_VIN_OV_FAULT_RESPONSE = 0x56, 74 PMBUS_VIN_OV_WARN_LIMIT = 0x57, 75 PMBUS_VIN_UV_WARN_LIMIT = 0x58, 76 PMBUS_VIN_UV_FAULT_LIMIT = 0x59, 77 78 PMBUS_IIN_OC_FAULT_LIMIT = 0x5B, 79 PMBUS_IIN_OC_WARN_LIMIT = 0x5D, 80 81 PMBUS_POUT_OP_FAULT_LIMIT = 0x68, 82 PMBUS_POUT_OP_WARN_LIMIT = 0x6A, 83 PMBUS_PIN_OP_WARN_LIMIT = 0x6B, 84 85 PMBUS_STATUS_BYTE = 0x78, 86 PMBUS_STATUS_WORD = 0x79, 87 PMBUS_STATUS_VOUT = 0x7A, 88 PMBUS_STATUS_IOUT = 0x7B, 89 PMBUS_STATUS_INPUT = 0x7C, 90 PMBUS_STATUS_TEMPERATURE = 0x7D, 91 PMBUS_STATUS_CML = 0x7E, 92 PMBUS_STATUS_OTHER = 0x7F, 93 PMBUS_STATUS_MFR_SPECIFIC = 0x80, 94 PMBUS_STATUS_FAN_12 = 0x81, 95 PMBUS_STATUS_FAN_34 = 0x82, 96 97 PMBUS_READ_VIN = 0x88, 98 PMBUS_READ_IIN = 0x89, 99 PMBUS_READ_VCAP = 0x8A, 100 PMBUS_READ_VOUT = 0x8B, 101 PMBUS_READ_IOUT = 0x8C, 102 PMBUS_READ_TEMPERATURE_1 = 0x8D, 103 PMBUS_READ_TEMPERATURE_2 = 0x8E, 104 PMBUS_READ_TEMPERATURE_3 = 0x8F, 105 PMBUS_READ_FAN_SPEED_1 = 0x90, 106 PMBUS_READ_FAN_SPEED_2 = 0x91, 107 PMBUS_READ_FAN_SPEED_3 = 0x92, 108 PMBUS_READ_FAN_SPEED_4 = 0x93, 109 PMBUS_READ_DUTY_CYCLE = 0x94, 110 PMBUS_READ_FREQUENCY = 0x95, 111 PMBUS_READ_POUT = 0x96, 112 PMBUS_READ_PIN = 0x97, 113 114 PMBUS_REVISION = 0x98, 115 PMBUS_MFR_ID = 0x99, 116 PMBUS_MFR_MODEL = 0x9A, 117 PMBUS_MFR_REVISION = 0x9B, 118 PMBUS_MFR_LOCATION = 0x9C, 119 PMBUS_MFR_DATE = 0x9D, 120 PMBUS_MFR_SERIAL = 0x9E, 121 122 PMBUS_MFR_VIN_MIN = 0xA0, 123 PMBUS_MFR_VIN_MAX = 0xA1, 124 PMBUS_MFR_IIN_MAX = 0xA2, 125 PMBUS_MFR_PIN_MAX = 0xA3, 126 PMBUS_MFR_VOUT_MIN = 0xA4, 127 PMBUS_MFR_VOUT_MAX = 0xA5, 128 PMBUS_MFR_IOUT_MAX = 0xA6, 129 PMBUS_MFR_POUT_MAX = 0xA7, 130 131 PMBUS_IC_DEVICE_ID = 0xAD, 132 PMBUS_IC_DEVICE_REV = 0xAE, 133 134 PMBUS_MFR_MAX_TEMP_1 = 0xC0, 135 PMBUS_MFR_MAX_TEMP_2 = 0xC1, 136 PMBUS_MFR_MAX_TEMP_3 = 0xC2, 137 138 /* 139 * Virtual registers. 140 * Useful to support attributes which are not supported by standard PMBus 141 * registers but exist as manufacturer specific registers on individual chips. 142 * Must be mapped to real registers in device specific code. 143 * 144 * Semantics: 145 * Virtual registers are all word size. 146 * READ registers are read-only; writes are either ignored or return an error. 147 * RESET registers are read/write. Reading reset registers returns zero 148 * (used for detection), writing any value causes the associated history to be 149 * reset. 150 * Virtual registers have to be handled in device specific driver code. Chip 151 * driver code returns non-negative register values if a virtual register is 152 * supported, or a negative error code if not. The chip driver may return 153 * -ENODATA or any other error code in this case, though an error code other 154 * than -ENODATA is handled more efficiently and thus preferred. Either case, 155 * the calling PMBus core code will abort if the chip driver returns an error 156 * code when reading or writing virtual registers. 157 */ 158 PMBUS_VIRT_BASE = 0x100, 159 PMBUS_VIRT_READ_TEMP_AVG, 160 PMBUS_VIRT_READ_TEMP_MIN, 161 PMBUS_VIRT_READ_TEMP_MAX, 162 PMBUS_VIRT_RESET_TEMP_HISTORY, 163 PMBUS_VIRT_READ_VIN_AVG, 164 PMBUS_VIRT_READ_VIN_MIN, 165 PMBUS_VIRT_READ_VIN_MAX, 166 PMBUS_VIRT_RESET_VIN_HISTORY, 167 PMBUS_VIRT_READ_IIN_AVG, 168 PMBUS_VIRT_READ_IIN_MIN, 169 PMBUS_VIRT_READ_IIN_MAX, 170 PMBUS_VIRT_RESET_IIN_HISTORY, 171 PMBUS_VIRT_READ_PIN_AVG, 172 PMBUS_VIRT_READ_PIN_MIN, 173 PMBUS_VIRT_READ_PIN_MAX, 174 PMBUS_VIRT_RESET_PIN_HISTORY, 175 PMBUS_VIRT_READ_POUT_AVG, 176 PMBUS_VIRT_READ_POUT_MIN, 177 PMBUS_VIRT_READ_POUT_MAX, 178 PMBUS_VIRT_RESET_POUT_HISTORY, 179 PMBUS_VIRT_READ_VOUT_AVG, 180 PMBUS_VIRT_READ_VOUT_MIN, 181 PMBUS_VIRT_READ_VOUT_MAX, 182 PMBUS_VIRT_RESET_VOUT_HISTORY, 183 PMBUS_VIRT_READ_IOUT_AVG, 184 PMBUS_VIRT_READ_IOUT_MIN, 185 PMBUS_VIRT_READ_IOUT_MAX, 186 PMBUS_VIRT_RESET_IOUT_HISTORY, 187 PMBUS_VIRT_READ_TEMP2_AVG, 188 PMBUS_VIRT_READ_TEMP2_MIN, 189 PMBUS_VIRT_READ_TEMP2_MAX, 190 PMBUS_VIRT_RESET_TEMP2_HISTORY, 191 192 PMBUS_VIRT_READ_VMON, 193 PMBUS_VIRT_VMON_UV_WARN_LIMIT, 194 PMBUS_VIRT_VMON_OV_WARN_LIMIT, 195 PMBUS_VIRT_VMON_UV_FAULT_LIMIT, 196 PMBUS_VIRT_VMON_OV_FAULT_LIMIT, 197 PMBUS_VIRT_STATUS_VMON, 198 199 /* 200 * RPM and PWM Fan control 201 * 202 * Drivers wanting to expose PWM control must define the behaviour of 203 * PMBUS_VIRT_PWM_[1-4] and PMBUS_VIRT_PWM_ENABLE_[1-4] in the 204 * {read,write}_word_data callback. 205 * 206 * pmbus core provides a default implementation for 207 * PMBUS_VIRT_FAN_TARGET_[1-4]. 208 * 209 * TARGET, PWM and PWM_ENABLE members must be defined sequentially; 210 * pmbus core uses the difference between the provided register and 211 * it's _1 counterpart to calculate the FAN/PWM ID. 212 */ 213 PMBUS_VIRT_FAN_TARGET_1, 214 PMBUS_VIRT_FAN_TARGET_2, 215 PMBUS_VIRT_FAN_TARGET_3, 216 PMBUS_VIRT_FAN_TARGET_4, 217 PMBUS_VIRT_PWM_1, 218 PMBUS_VIRT_PWM_2, 219 PMBUS_VIRT_PWM_3, 220 PMBUS_VIRT_PWM_4, 221 PMBUS_VIRT_PWM_ENABLE_1, 222 PMBUS_VIRT_PWM_ENABLE_2, 223 PMBUS_VIRT_PWM_ENABLE_3, 224 PMBUS_VIRT_PWM_ENABLE_4, 225 226 /* Samples for average 227 * 228 * Drivers wanting to expose functionality for changing the number of 229 * samples used for average values should implement support in 230 * {read,write}_word_data callback for either PMBUS_VIRT_SAMPLES if it 231 * applies to all types of measurements, or any number of specific 232 * PMBUS_VIRT_*_SAMPLES registers to allow for individual control. 233 */ 234 PMBUS_VIRT_SAMPLES, 235 PMBUS_VIRT_IN_SAMPLES, 236 PMBUS_VIRT_CURR_SAMPLES, 237 PMBUS_VIRT_POWER_SAMPLES, 238 PMBUS_VIRT_TEMP_SAMPLES, 239 }; 240 241 /* 242 * OPERATION 243 */ 244 #define PB_OPERATION_CONTROL_ON BIT(7) 245 246 /* 247 * ON_OFF_CONFIG 248 */ 249 #define PB_ON_OFF_CONFIG_POWERUP_CONTROL BIT(4) 250 #define PB_ON_OFF_CONFIG_OPERATION_REQ BIT(3) 251 #define PB_ON_OFF_CONFIG_EN_PIN_REQ BIT(2) 252 #define PB_ON_OFF_CONFIG_POLARITY_HIGH BIT(1) 253 #define PB_ON_OFF_CONFIG_TURN_OFF_FAST BIT(0) 254 255 /* 256 * WRITE_PROTECT 257 */ 258 #define PB_WP_ALL BIT(7) /* all but WRITE_PROTECT */ 259 #define PB_WP_OP BIT(6) /* all but WP, OPERATION, PAGE */ 260 #define PB_WP_VOUT BIT(5) /* all but WP, OPERATION, PAGE, VOUT, ON_OFF */ 261 262 #define PB_WP_ANY (PB_WP_ALL | PB_WP_OP | PB_WP_VOUT) 263 264 /* 265 * CAPABILITY 266 */ 267 #define PB_CAPABILITY_SMBALERT BIT(4) 268 #define PB_CAPABILITY_ERROR_CHECK BIT(7) 269 270 /* 271 * VOUT_MODE 272 */ 273 #define PB_VOUT_MODE_MODE_MASK 0xe0 274 #define PB_VOUT_MODE_PARAM_MASK 0x1f 275 276 #define PB_VOUT_MODE_LINEAR 0x00 277 #define PB_VOUT_MODE_VID 0x20 278 #define PB_VOUT_MODE_DIRECT 0x40 279 280 /* 281 * Fan configuration 282 */ 283 #define PB_FAN_2_PULSE_MASK (BIT(0) | BIT(1)) 284 #define PB_FAN_2_RPM BIT(2) 285 #define PB_FAN_2_INSTALLED BIT(3) 286 #define PB_FAN_1_PULSE_MASK (BIT(4) | BIT(5)) 287 #define PB_FAN_1_RPM BIT(6) 288 #define PB_FAN_1_INSTALLED BIT(7) 289 290 enum pmbus_fan_mode { percent = 0, rpm }; 291 292 /* 293 * STATUS_BYTE, STATUS_WORD (lower) 294 */ 295 #define PB_STATUS_NONE_ABOVE BIT(0) 296 #define PB_STATUS_CML BIT(1) 297 #define PB_STATUS_TEMPERATURE BIT(2) 298 #define PB_STATUS_VIN_UV BIT(3) 299 #define PB_STATUS_IOUT_OC BIT(4) 300 #define PB_STATUS_VOUT_OV BIT(5) 301 #define PB_STATUS_OFF BIT(6) 302 #define PB_STATUS_BUSY BIT(7) 303 304 /* 305 * STATUS_WORD (upper) 306 */ 307 #define PB_STATUS_UNKNOWN BIT(8) 308 #define PB_STATUS_OTHER BIT(9) 309 #define PB_STATUS_FANS BIT(10) 310 #define PB_STATUS_POWER_GOOD_N BIT(11) 311 #define PB_STATUS_WORD_MFR BIT(12) 312 #define PB_STATUS_INPUT BIT(13) 313 #define PB_STATUS_IOUT_POUT BIT(14) 314 #define PB_STATUS_VOUT BIT(15) 315 316 /* 317 * STATUS_IOUT 318 */ 319 #define PB_POUT_OP_WARNING BIT(0) 320 #define PB_POUT_OP_FAULT BIT(1) 321 #define PB_POWER_LIMITING BIT(2) 322 #define PB_CURRENT_SHARE_FAULT BIT(3) 323 #define PB_IOUT_UC_FAULT BIT(4) 324 #define PB_IOUT_OC_WARNING BIT(5) 325 #define PB_IOUT_OC_LV_FAULT BIT(6) 326 #define PB_IOUT_OC_FAULT BIT(7) 327 328 /* 329 * STATUS_VOUT, STATUS_INPUT 330 */ 331 #define PB_VOLTAGE_VIN_OFF BIT(3) 332 #define PB_VOLTAGE_UV_FAULT BIT(4) 333 #define PB_VOLTAGE_UV_WARNING BIT(5) 334 #define PB_VOLTAGE_OV_WARNING BIT(6) 335 #define PB_VOLTAGE_OV_FAULT BIT(7) 336 337 /* 338 * STATUS_INPUT 339 */ 340 #define PB_PIN_OP_WARNING BIT(0) 341 #define PB_IIN_OC_WARNING BIT(1) 342 #define PB_IIN_OC_FAULT BIT(2) 343 344 /* 345 * STATUS_TEMPERATURE 346 */ 347 #define PB_TEMP_UT_FAULT BIT(4) 348 #define PB_TEMP_UT_WARNING BIT(5) 349 #define PB_TEMP_OT_WARNING BIT(6) 350 #define PB_TEMP_OT_FAULT BIT(7) 351 352 /* 353 * STATUS_FAN 354 */ 355 #define PB_FAN_AIRFLOW_WARNING BIT(0) 356 #define PB_FAN_AIRFLOW_FAULT BIT(1) 357 #define PB_FAN_FAN2_SPEED_OVERRIDE BIT(2) 358 #define PB_FAN_FAN1_SPEED_OVERRIDE BIT(3) 359 #define PB_FAN_FAN2_WARNING BIT(4) 360 #define PB_FAN_FAN1_WARNING BIT(5) 361 #define PB_FAN_FAN2_FAULT BIT(6) 362 #define PB_FAN_FAN1_FAULT BIT(7) 363 364 /* 365 * CML_FAULT_STATUS 366 */ 367 #define PB_CML_FAULT_OTHER_MEM_LOGIC BIT(0) 368 #define PB_CML_FAULT_OTHER_COMM BIT(1) 369 #define PB_CML_FAULT_PROCESSOR BIT(3) 370 #define PB_CML_FAULT_MEMORY BIT(4) 371 #define PB_CML_FAULT_PACKET_ERROR BIT(5) 372 #define PB_CML_FAULT_INVALID_DATA BIT(6) 373 #define PB_CML_FAULT_INVALID_COMMAND BIT(7) 374 375 enum pmbus_sensor_classes { 376 PSC_VOLTAGE_IN = 0, 377 PSC_VOLTAGE_OUT, 378 PSC_CURRENT_IN, 379 PSC_CURRENT_OUT, 380 PSC_POWER, 381 PSC_TEMPERATURE, 382 PSC_FAN, 383 PSC_PWM, 384 PSC_NUM_CLASSES /* Number of power sensor classes */ 385 }; 386 387 #define PMBUS_PAGES 32 /* Per PMBus specification */ 388 #define PMBUS_PHASES 10 /* Maximum number of phases per page */ 389 390 /* Functionality bit mask */ 391 #define PMBUS_HAVE_VIN BIT(0) 392 #define PMBUS_HAVE_VCAP BIT(1) 393 #define PMBUS_HAVE_VOUT BIT(2) 394 #define PMBUS_HAVE_IIN BIT(3) 395 #define PMBUS_HAVE_IOUT BIT(4) 396 #define PMBUS_HAVE_PIN BIT(5) 397 #define PMBUS_HAVE_POUT BIT(6) 398 #define PMBUS_HAVE_FAN12 BIT(7) 399 #define PMBUS_HAVE_FAN34 BIT(8) 400 #define PMBUS_HAVE_TEMP BIT(9) 401 #define PMBUS_HAVE_TEMP2 BIT(10) 402 #define PMBUS_HAVE_TEMP3 BIT(11) 403 #define PMBUS_HAVE_STATUS_VOUT BIT(12) 404 #define PMBUS_HAVE_STATUS_IOUT BIT(13) 405 #define PMBUS_HAVE_STATUS_INPUT BIT(14) 406 #define PMBUS_HAVE_STATUS_TEMP BIT(15) 407 #define PMBUS_HAVE_STATUS_FAN12 BIT(16) 408 #define PMBUS_HAVE_STATUS_FAN34 BIT(17) 409 #define PMBUS_HAVE_VMON BIT(18) 410 #define PMBUS_HAVE_STATUS_VMON BIT(19) 411 #define PMBUS_HAVE_PWM12 BIT(20) 412 #define PMBUS_HAVE_PWM34 BIT(21) 413 #define PMBUS_HAVE_SAMPLES BIT(22) 414 415 #define PMBUS_PHASE_VIRTUAL BIT(30) /* Phases on this page are virtual */ 416 #define PMBUS_PAGE_VIRTUAL BIT(31) /* Page is virtual */ 417 418 enum pmbus_data_format { linear = 0, ieee754, direct, vid }; 419 enum vrm_version { vr11 = 0, vr12, vr13, imvp9, amd625mv }; 420 421 /* PMBus revision identifiers */ 422 #define PMBUS_REV_10 0x00 /* PMBus revision 1.0 */ 423 #define PMBUS_REV_11 0x11 /* PMBus revision 1.1 */ 424 #define PMBUS_REV_12 0x22 /* PMBus revision 1.2 */ 425 #define PMBUS_REV_13 0x33 /* PMBus revision 1.3 */ 426 427 struct pmbus_driver_info { 428 int pages; /* Total number of pages */ 429 u8 phases[PMBUS_PAGES]; /* Number of phases per page */ 430 enum pmbus_data_format format[PSC_NUM_CLASSES]; 431 enum vrm_version vrm_version[PMBUS_PAGES]; /* vrm version per page */ 432 /* 433 * Support one set of coefficients for each sensor type 434 * Used for chips providing data in direct mode. 435 */ 436 int m[PSC_NUM_CLASSES]; /* mantissa for direct data format */ 437 int b[PSC_NUM_CLASSES]; /* offset */ 438 int R[PSC_NUM_CLASSES]; /* exponent */ 439 440 u32 func[PMBUS_PAGES]; /* Functionality, per page */ 441 u32 pfunc[PMBUS_PHASES];/* Functionality, per phase */ 442 /* 443 * The following functions map manufacturing specific register values 444 * to PMBus standard register values. Specify only if mapping is 445 * necessary. 446 * Functions return the register value (read) or zero (write) if 447 * successful. A return value of -ENODATA indicates that there is no 448 * manufacturer specific register, but that a standard PMBus register 449 * may exist. Any other negative return value indicates that the 450 * register does not exist, and that no attempt should be made to read 451 * the standard register. 452 */ 453 int (*read_byte_data)(struct i2c_client *client, int page, int reg); 454 int (*read_word_data)(struct i2c_client *client, int page, int phase, 455 int reg); 456 int (*write_byte_data)(struct i2c_client *client, int page, int reg, 457 u8 byte); 458 int (*write_word_data)(struct i2c_client *client, int page, int reg, 459 u16 word); 460 int (*write_byte)(struct i2c_client *client, int page, u8 value); 461 /* 462 * The identify function determines supported PMBus functionality. 463 * This function is only necessary if a chip driver supports multiple 464 * chips, and the chip functionality is not pre-determined. 465 */ 466 int (*identify)(struct i2c_client *client, 467 struct pmbus_driver_info *info); 468 469 /* Regulator functionality, if supported by this chip driver. */ 470 int num_regulators; 471 const struct regulator_desc *reg_desc; 472 473 /* custom attributes */ 474 const struct attribute_group **groups; 475 476 /* 477 * Some chips need a little delay between SMBus communication. When 478 * set, the generic PMBus helper functions will wait if necessary 479 * to meet this requirement. The access delay is honored after 480 * every SMBus operation. The write delay is only honored after 481 * SMBus write operations. 482 */ 483 int access_delay; /* in microseconds */ 484 int write_delay; /* in microseconds */ 485 }; 486 487 /* Regulator ops */ 488 489 extern const struct regulator_ops pmbus_regulator_ops; 490 491 /* Macros for filling in array of struct regulator_desc */ 492 #define PMBUS_REGULATOR_STEP(_name, _id, _voltages, _step, _min_uV) \ 493 [_id] = { \ 494 .name = (_name # _id), \ 495 .id = (_id), \ 496 .of_match = of_match_ptr(_name # _id), \ 497 .regulators_node = of_match_ptr("regulators"), \ 498 .ops = &pmbus_regulator_ops, \ 499 .type = REGULATOR_VOLTAGE, \ 500 .owner = THIS_MODULE, \ 501 .n_voltages = _voltages, \ 502 .uV_step = _step, \ 503 .min_uV = _min_uV, \ 504 } 505 506 #define PMBUS_REGULATOR(_name, _id) PMBUS_REGULATOR_STEP(_name, _id, 0, 0, 0) 507 508 #define PMBUS_REGULATOR_STEP_ONE(_name, _voltages, _step, _min_uV) \ 509 { \ 510 .name = (_name), \ 511 .of_match = of_match_ptr(_name), \ 512 .regulators_node = of_match_ptr("regulators"), \ 513 .ops = &pmbus_regulator_ops, \ 514 .type = REGULATOR_VOLTAGE, \ 515 .owner = THIS_MODULE, \ 516 .n_voltages = _voltages, \ 517 .uV_step = _step, \ 518 .min_uV = _min_uV, \ 519 } 520 521 #define PMBUS_REGULATOR_ONE(_name) PMBUS_REGULATOR_STEP_ONE(_name, 0, 0, 0) 522 523 /* Function declarations */ 524 525 void pmbus_clear_cache(struct i2c_client *client); 526 void pmbus_set_update(struct i2c_client *client, u8 reg, bool update); 527 int pmbus_set_page(struct i2c_client *client, int page, int phase); 528 int pmbus_read_word_data(struct i2c_client *client, int page, int phase, 529 u8 reg); 530 int pmbus_write_word_data(struct i2c_client *client, int page, u8 reg, 531 u16 word); 532 int pmbus_read_byte_data(struct i2c_client *client, int page, u8 reg); 533 int pmbus_write_byte(struct i2c_client *client, int page, u8 value); 534 int pmbus_write_byte_data(struct i2c_client *client, int page, u8 reg, 535 u8 value); 536 int pmbus_update_byte_data(struct i2c_client *client, int page, u8 reg, 537 u8 mask, u8 value); 538 void pmbus_clear_faults(struct i2c_client *client); 539 bool pmbus_check_byte_register(struct i2c_client *client, int page, int reg); 540 bool pmbus_check_word_register(struct i2c_client *client, int page, int reg); 541 int pmbus_do_probe(struct i2c_client *client, struct pmbus_driver_info *info); 542 const struct pmbus_driver_info *pmbus_get_driver_info(struct i2c_client 543 *client); 544 int pmbus_get_fan_rate_device(struct i2c_client *client, int page, int id, 545 enum pmbus_fan_mode mode); 546 int pmbus_get_fan_rate_cached(struct i2c_client *client, int page, int id, 547 enum pmbus_fan_mode mode); 548 int pmbus_lock_interruptible(struct i2c_client *client); 549 void pmbus_unlock(struct i2c_client *client); 550 int pmbus_update_fan(struct i2c_client *client, int page, int id, 551 u8 config, u8 mask, u16 command); 552 struct dentry *pmbus_get_debugfs_dir(struct i2c_client *client); 553 554 #endif /* PMBUS_H */ 555