1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 MaxLinear, Inc. 4 * 5 * This driver is a hardware monitoring driver for PVT controller 6 * (MR75203) which is used to configure & control Moortec embedded 7 * analog IP to enable multiple embedded temperature sensor(TS), 8 * voltage monitor(VM) & process detector(PD) modules. 9 */ 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/hwmon.h> 13 #include <linux/module.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/mutex.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 #include <linux/units.h> 21 22 /* PVT Common register */ 23 #define PVT_IP_CONFIG 0x04 24 #define TS_NUM_MSK GENMASK(4, 0) 25 #define TS_NUM_SFT 0 26 #define PD_NUM_MSK GENMASK(12, 8) 27 #define PD_NUM_SFT 8 28 #define VM_NUM_MSK GENMASK(20, 16) 29 #define VM_NUM_SFT 16 30 #define CH_NUM_MSK GENMASK(31, 24) 31 #define CH_NUM_SFT 24 32 33 /* Macro Common Register */ 34 #define CLK_SYNTH 0x00 35 #define CLK_SYNTH_LO_SFT 0 36 #define CLK_SYNTH_HI_SFT 8 37 #define CLK_SYNTH_HOLD_SFT 16 38 #define CLK_SYNTH_EN BIT(24) 39 #define CLK_SYS_CYCLES_MAX 514 40 #define CLK_SYS_CYCLES_MIN 2 41 42 #define SDIF_DISABLE 0x04 43 44 #define SDIF_STAT 0x08 45 #define SDIF_BUSY BIT(0) 46 #define SDIF_LOCK BIT(1) 47 48 #define SDIF_W 0x0c 49 #define SDIF_PROG BIT(31) 50 #define SDIF_WRN_W BIT(27) 51 #define SDIF_WRN_R 0x00 52 #define SDIF_ADDR_SFT 24 53 54 #define SDIF_HALT 0x10 55 #define SDIF_CTRL 0x14 56 #define SDIF_SMPL_CTRL 0x20 57 58 /* TS & PD Individual Macro Register */ 59 #define COM_REG_SIZE 0x40 60 61 #define SDIF_DONE(n) (COM_REG_SIZE + 0x14 + 0x40 * (n)) 62 #define SDIF_SMPL_DONE BIT(0) 63 64 #define SDIF_DATA(n) (COM_REG_SIZE + 0x18 + 0x40 * (n)) 65 #define SAMPLE_DATA_MSK GENMASK(15, 0) 66 67 #define HILO_RESET(n) (COM_REG_SIZE + 0x2c + 0x40 * (n)) 68 69 /* VM Individual Macro Register */ 70 #define VM_COM_REG_SIZE 0x200 71 #define VM_SDIF_DONE(n) (VM_COM_REG_SIZE + 0x34 + 0x200 * (n)) 72 #define VM_SDIF_DATA(n) (VM_COM_REG_SIZE + 0x40 + 0x200 * (n)) 73 74 /* SDA Slave Register */ 75 #define IP_CTRL 0x00 76 #define IP_RST_REL BIT(1) 77 #define IP_RUN_CONT BIT(3) 78 #define IP_AUTO BIT(8) 79 #define IP_VM_MODE BIT(10) 80 81 #define IP_CFG 0x01 82 #define CFG0_MODE_2 BIT(0) 83 #define CFG0_PARALLEL_OUT 0 84 #define CFG0_12_BIT 0 85 #define CFG1_VOL_MEAS_MODE 0 86 #define CFG1_PARALLEL_OUT 0 87 #define CFG1_14_BIT 0 88 89 #define IP_DATA 0x03 90 91 #define IP_POLL 0x04 92 #define VM_CH_INIT BIT(20) 93 #define VM_CH_REQ BIT(21) 94 95 #define IP_TMR 0x05 96 #define POWER_DELAY_CYCLE_256 0x100 97 #define POWER_DELAY_CYCLE_64 0x40 98 99 #define PVT_POLL_DELAY_US 20 100 #define PVT_POLL_TIMEOUT_US 20000 101 #define PVT_H_CONST 100000 102 #define PVT_CAL5_CONST 2047 103 #define PVT_G_CONST 40000 104 #define PVT_CONV_BITS 10 105 #define PVT_N_CONST 90 106 #define PVT_R_CONST 245805 107 108 struct pvt_device { 109 struct regmap *c_map; 110 struct regmap *t_map; 111 struct regmap *p_map; 112 struct regmap *v_map; 113 struct clk *clk; 114 struct reset_control *rst; 115 u32 t_num; 116 u32 p_num; 117 u32 v_num; 118 u32 ip_freq; 119 u8 *vm_idx; 120 }; 121 122 static umode_t pvt_is_visible(const void *data, enum hwmon_sensor_types type, 123 u32 attr, int channel) 124 { 125 switch (type) { 126 case hwmon_temp: 127 if (attr == hwmon_temp_input) 128 return 0444; 129 break; 130 case hwmon_in: 131 if (attr == hwmon_in_input) 132 return 0444; 133 break; 134 default: 135 break; 136 } 137 return 0; 138 } 139 140 static int pvt_read_temp(struct device *dev, u32 attr, int channel, long *val) 141 { 142 struct pvt_device *pvt = dev_get_drvdata(dev); 143 struct regmap *t_map = pvt->t_map; 144 u32 stat, nbs; 145 int ret; 146 u64 tmp; 147 148 switch (attr) { 149 case hwmon_temp_input: 150 ret = regmap_read_poll_timeout(t_map, SDIF_DONE(channel), 151 stat, stat & SDIF_SMPL_DONE, 152 PVT_POLL_DELAY_US, 153 PVT_POLL_TIMEOUT_US); 154 if (ret) 155 return ret; 156 157 ret = regmap_read(t_map, SDIF_DATA(channel), &nbs); 158 if(ret < 0) 159 return ret; 160 161 nbs &= SAMPLE_DATA_MSK; 162 163 /* 164 * Convert the register value to 165 * degrees centigrade temperature 166 */ 167 tmp = nbs * PVT_H_CONST; 168 do_div(tmp, PVT_CAL5_CONST); 169 *val = tmp - PVT_G_CONST - pvt->ip_freq; 170 171 return 0; 172 default: 173 return -EOPNOTSUPP; 174 } 175 } 176 177 static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val) 178 { 179 struct pvt_device *pvt = dev_get_drvdata(dev); 180 struct regmap *v_map = pvt->v_map; 181 u32 n, stat; 182 u8 vm_idx; 183 int ret; 184 185 if (channel >= pvt->v_num) 186 return -EINVAL; 187 188 vm_idx = pvt->vm_idx[channel]; 189 190 switch (attr) { 191 case hwmon_in_input: 192 ret = regmap_read_poll_timeout(v_map, VM_SDIF_DONE(vm_idx), 193 stat, stat & SDIF_SMPL_DONE, 194 PVT_POLL_DELAY_US, 195 PVT_POLL_TIMEOUT_US); 196 if (ret) 197 return ret; 198 199 ret = regmap_read(v_map, VM_SDIF_DATA(vm_idx), &n); 200 if(ret < 0) 201 return ret; 202 203 n &= SAMPLE_DATA_MSK; 204 /* Convert the N bitstream count into voltage */ 205 *val = (PVT_N_CONST * n - PVT_R_CONST) >> PVT_CONV_BITS; 206 207 return 0; 208 default: 209 return -EOPNOTSUPP; 210 } 211 } 212 213 static int pvt_read(struct device *dev, enum hwmon_sensor_types type, 214 u32 attr, int channel, long *val) 215 { 216 switch (type) { 217 case hwmon_temp: 218 return pvt_read_temp(dev, attr, channel, val); 219 case hwmon_in: 220 return pvt_read_in(dev, attr, channel, val); 221 default: 222 return -EOPNOTSUPP; 223 } 224 } 225 226 static struct hwmon_channel_info pvt_temp = { 227 .type = hwmon_temp, 228 }; 229 230 static struct hwmon_channel_info pvt_in = { 231 .type = hwmon_in, 232 }; 233 234 static const struct hwmon_ops pvt_hwmon_ops = { 235 .is_visible = pvt_is_visible, 236 .read = pvt_read, 237 }; 238 239 static struct hwmon_chip_info pvt_chip_info = { 240 .ops = &pvt_hwmon_ops, 241 }; 242 243 static int pvt_init(struct pvt_device *pvt) 244 { 245 u16 sys_freq, key, middle, low = 4, high = 8; 246 struct regmap *t_map = pvt->t_map; 247 struct regmap *p_map = pvt->p_map; 248 struct regmap *v_map = pvt->v_map; 249 u32 t_num = pvt->t_num; 250 u32 p_num = pvt->p_num; 251 u32 v_num = pvt->v_num; 252 u32 clk_synth, val; 253 int ret; 254 255 sys_freq = clk_get_rate(pvt->clk) / HZ_PER_MHZ; 256 while (high >= low) { 257 middle = (low + high + 1) / 2; 258 key = DIV_ROUND_CLOSEST(sys_freq, middle); 259 if (key > CLK_SYS_CYCLES_MAX) { 260 low = middle + 1; 261 continue; 262 } else if (key < CLK_SYS_CYCLES_MIN) { 263 high = middle - 1; 264 continue; 265 } else { 266 break; 267 } 268 } 269 270 /* 271 * The system supports 'clk_sys' to 'clk_ip' frequency ratios 272 * from 2:1 to 512:1 273 */ 274 key = clamp_val(key, CLK_SYS_CYCLES_MIN, CLK_SYS_CYCLES_MAX) - 2; 275 276 clk_synth = ((key + 1) >> 1) << CLK_SYNTH_LO_SFT | 277 (key >> 1) << CLK_SYNTH_HI_SFT | 278 (key >> 1) << CLK_SYNTH_HOLD_SFT | CLK_SYNTH_EN; 279 280 pvt->ip_freq = sys_freq * 100 / (key + 2); 281 282 if (t_num) { 283 ret = regmap_write(t_map, SDIF_SMPL_CTRL, 0x0); 284 if(ret < 0) 285 return ret; 286 287 ret = regmap_write(t_map, SDIF_HALT, 0x0); 288 if(ret < 0) 289 return ret; 290 291 ret = regmap_write(t_map, CLK_SYNTH, clk_synth); 292 if(ret < 0) 293 return ret; 294 295 ret = regmap_write(t_map, SDIF_DISABLE, 0x0); 296 if(ret < 0) 297 return ret; 298 299 ret = regmap_read_poll_timeout(t_map, SDIF_STAT, 300 val, !(val & SDIF_BUSY), 301 PVT_POLL_DELAY_US, 302 PVT_POLL_TIMEOUT_US); 303 if (ret) 304 return ret; 305 306 val = CFG0_MODE_2 | CFG0_PARALLEL_OUT | CFG0_12_BIT | 307 IP_CFG << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG; 308 ret = regmap_write(t_map, SDIF_W, val); 309 if(ret < 0) 310 return ret; 311 312 ret = regmap_read_poll_timeout(t_map, SDIF_STAT, 313 val, !(val & SDIF_BUSY), 314 PVT_POLL_DELAY_US, 315 PVT_POLL_TIMEOUT_US); 316 if (ret) 317 return ret; 318 319 val = POWER_DELAY_CYCLE_256 | IP_TMR << SDIF_ADDR_SFT | 320 SDIF_WRN_W | SDIF_PROG; 321 ret = regmap_write(t_map, SDIF_W, val); 322 if(ret < 0) 323 return ret; 324 325 ret = regmap_read_poll_timeout(t_map, SDIF_STAT, 326 val, !(val & SDIF_BUSY), 327 PVT_POLL_DELAY_US, 328 PVT_POLL_TIMEOUT_US); 329 if (ret) 330 return ret; 331 332 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | 333 IP_CTRL << SDIF_ADDR_SFT | 334 SDIF_WRN_W | SDIF_PROG; 335 ret = regmap_write(t_map, SDIF_W, val); 336 if(ret < 0) 337 return ret; 338 } 339 340 if (p_num) { 341 ret = regmap_write(p_map, SDIF_HALT, 0x0); 342 if(ret < 0) 343 return ret; 344 345 ret = regmap_write(p_map, SDIF_DISABLE, BIT(p_num) - 1); 346 if(ret < 0) 347 return ret; 348 349 ret = regmap_write(p_map, CLK_SYNTH, clk_synth); 350 if(ret < 0) 351 return ret; 352 } 353 354 if (v_num) { 355 ret = regmap_write(v_map, SDIF_SMPL_CTRL, 0x0); 356 if(ret < 0) 357 return ret; 358 359 ret = regmap_write(v_map, SDIF_HALT, 0x0); 360 if(ret < 0) 361 return ret; 362 363 ret = regmap_write(v_map, CLK_SYNTH, clk_synth); 364 if(ret < 0) 365 return ret; 366 367 ret = regmap_write(v_map, SDIF_DISABLE, 0x0); 368 if(ret < 0) 369 return ret; 370 371 ret = regmap_read_poll_timeout(v_map, SDIF_STAT, 372 val, !(val & SDIF_BUSY), 373 PVT_POLL_DELAY_US, 374 PVT_POLL_TIMEOUT_US); 375 if (ret) 376 return ret; 377 378 val = CFG1_VOL_MEAS_MODE | CFG1_PARALLEL_OUT | 379 CFG1_14_BIT | IP_CFG << SDIF_ADDR_SFT | 380 SDIF_WRN_W | SDIF_PROG; 381 ret = regmap_write(v_map, SDIF_W, val); 382 if(ret < 0) 383 return ret; 384 385 ret = regmap_read_poll_timeout(v_map, SDIF_STAT, 386 val, !(val & SDIF_BUSY), 387 PVT_POLL_DELAY_US, 388 PVT_POLL_TIMEOUT_US); 389 if (ret) 390 return ret; 391 392 val = POWER_DELAY_CYCLE_64 | IP_TMR << SDIF_ADDR_SFT | 393 SDIF_WRN_W | SDIF_PROG; 394 ret = regmap_write(v_map, SDIF_W, val); 395 if(ret < 0) 396 return ret; 397 398 ret = regmap_read_poll_timeout(v_map, SDIF_STAT, 399 val, !(val & SDIF_BUSY), 400 PVT_POLL_DELAY_US, 401 PVT_POLL_TIMEOUT_US); 402 if (ret) 403 return ret; 404 405 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | IP_VM_MODE | 406 IP_CTRL << SDIF_ADDR_SFT | 407 SDIF_WRN_W | SDIF_PROG; 408 ret = regmap_write(v_map, SDIF_W, val); 409 if(ret < 0) 410 return ret; 411 } 412 413 return 0; 414 } 415 416 static struct regmap_config pvt_regmap_config = { 417 .reg_bits = 32, 418 .reg_stride = 4, 419 .val_bits = 32, 420 }; 421 422 static int pvt_get_regmap(struct platform_device *pdev, char *reg_name, 423 struct pvt_device *pvt) 424 { 425 struct device *dev = &pdev->dev; 426 struct regmap **reg_map; 427 void __iomem *io_base; 428 429 if (!strcmp(reg_name, "common")) 430 reg_map = &pvt->c_map; 431 else if (!strcmp(reg_name, "ts")) 432 reg_map = &pvt->t_map; 433 else if (!strcmp(reg_name, "pd")) 434 reg_map = &pvt->p_map; 435 else if (!strcmp(reg_name, "vm")) 436 reg_map = &pvt->v_map; 437 else 438 return -EINVAL; 439 440 io_base = devm_platform_ioremap_resource_byname(pdev, reg_name); 441 if (IS_ERR(io_base)) 442 return PTR_ERR(io_base); 443 444 pvt_regmap_config.name = reg_name; 445 *reg_map = devm_regmap_init_mmio(dev, io_base, &pvt_regmap_config); 446 if (IS_ERR(*reg_map)) { 447 dev_err(dev, "failed to init register map\n"); 448 return PTR_ERR(*reg_map); 449 } 450 451 return 0; 452 } 453 454 static void pvt_clk_disable(void *data) 455 { 456 struct pvt_device *pvt = data; 457 458 clk_disable_unprepare(pvt->clk); 459 } 460 461 static int pvt_clk_enable(struct device *dev, struct pvt_device *pvt) 462 { 463 int ret; 464 465 ret = clk_prepare_enable(pvt->clk); 466 if (ret) 467 return ret; 468 469 return devm_add_action_or_reset(dev, pvt_clk_disable, pvt); 470 } 471 472 static void pvt_reset_control_assert(void *data) 473 { 474 struct pvt_device *pvt = data; 475 476 reset_control_assert(pvt->rst); 477 } 478 479 static int pvt_reset_control_deassert(struct device *dev, struct pvt_device *pvt) 480 { 481 int ret; 482 483 ret = reset_control_deassert(pvt->rst); 484 if (ret) 485 return ret; 486 487 return devm_add_action_or_reset(dev, pvt_reset_control_assert, pvt); 488 } 489 490 static int mr75203_probe(struct platform_device *pdev) 491 { 492 const struct hwmon_channel_info **pvt_info; 493 u32 ts_num, vm_num, pd_num, val, index, i; 494 struct device *dev = &pdev->dev; 495 u32 *temp_config, *in_config; 496 struct device *hwmon_dev; 497 struct pvt_device *pvt; 498 int ret; 499 500 pvt = devm_kzalloc(dev, sizeof(*pvt), GFP_KERNEL); 501 if (!pvt) 502 return -ENOMEM; 503 504 ret = pvt_get_regmap(pdev, "common", pvt); 505 if (ret) 506 return ret; 507 508 pvt->clk = devm_clk_get(dev, NULL); 509 if (IS_ERR(pvt->clk)) 510 return dev_err_probe(dev, PTR_ERR(pvt->clk), "failed to get clock\n"); 511 512 ret = pvt_clk_enable(dev, pvt); 513 if (ret) { 514 dev_err(dev, "failed to enable clock\n"); 515 return ret; 516 } 517 518 pvt->rst = devm_reset_control_get_exclusive(dev, NULL); 519 if (IS_ERR(pvt->rst)) 520 return dev_err_probe(dev, PTR_ERR(pvt->rst), 521 "failed to get reset control\n"); 522 523 ret = pvt_reset_control_deassert(dev, pvt); 524 if (ret) 525 return dev_err_probe(dev, ret, "cannot deassert reset control\n"); 526 527 ret = regmap_read(pvt->c_map, PVT_IP_CONFIG, &val); 528 if(ret < 0) 529 return ret; 530 531 ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT; 532 pd_num = (val & PD_NUM_MSK) >> PD_NUM_SFT; 533 vm_num = (val & VM_NUM_MSK) >> VM_NUM_SFT; 534 pvt->t_num = ts_num; 535 pvt->p_num = pd_num; 536 pvt->v_num = vm_num; 537 val = 0; 538 if (ts_num) 539 val++; 540 if (vm_num) 541 val++; 542 if (!val) 543 return -ENODEV; 544 545 pvt_info = devm_kcalloc(dev, val + 2, sizeof(*pvt_info), GFP_KERNEL); 546 if (!pvt_info) 547 return -ENOMEM; 548 pvt_info[0] = HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ); 549 index = 1; 550 551 if (ts_num) { 552 ret = pvt_get_regmap(pdev, "ts", pvt); 553 if (ret) 554 return ret; 555 556 temp_config = devm_kcalloc(dev, ts_num + 1, 557 sizeof(*temp_config), GFP_KERNEL); 558 if (!temp_config) 559 return -ENOMEM; 560 561 memset32(temp_config, HWMON_T_INPUT, ts_num); 562 pvt_temp.config = temp_config; 563 pvt_info[index++] = &pvt_temp; 564 } 565 566 if (pd_num) { 567 ret = pvt_get_regmap(pdev, "pd", pvt); 568 if (ret) 569 return ret; 570 } 571 572 if (vm_num) { 573 u32 num = vm_num; 574 575 ret = pvt_get_regmap(pdev, "vm", pvt); 576 if (ret) 577 return ret; 578 579 pvt->vm_idx = devm_kcalloc(dev, vm_num, sizeof(*pvt->vm_idx), 580 GFP_KERNEL); 581 if (!pvt->vm_idx) 582 return -ENOMEM; 583 584 ret = device_property_read_u8_array(dev, "intel,vm-map", 585 pvt->vm_idx, vm_num); 586 if (ret) { 587 num = 0; 588 } else { 589 for (i = 0; i < vm_num; i++) 590 if (pvt->vm_idx[i] >= vm_num || 591 pvt->vm_idx[i] == 0xff) { 592 num = i; 593 break; 594 } 595 } 596 597 /* 598 * Incase intel,vm-map property is not defined, we assume 599 * incremental channel numbers. 600 */ 601 for (i = num; i < vm_num; i++) 602 pvt->vm_idx[i] = i; 603 604 in_config = devm_kcalloc(dev, num + 1, 605 sizeof(*in_config), GFP_KERNEL); 606 if (!in_config) 607 return -ENOMEM; 608 609 memset32(in_config, HWMON_I_INPUT, num); 610 in_config[num] = 0; 611 pvt_in.config = in_config; 612 613 pvt_info[index++] = &pvt_in; 614 } 615 616 ret = pvt_init(pvt); 617 if (ret) { 618 dev_err(dev, "failed to init pvt: %d\n", ret); 619 return ret; 620 } 621 622 pvt_chip_info.info = pvt_info; 623 hwmon_dev = devm_hwmon_device_register_with_info(dev, "pvt", 624 pvt, 625 &pvt_chip_info, 626 NULL); 627 628 return PTR_ERR_OR_ZERO(hwmon_dev); 629 } 630 631 static const struct of_device_id moortec_pvt_of_match[] = { 632 { .compatible = "moortec,mr75203" }, 633 { } 634 }; 635 MODULE_DEVICE_TABLE(of, moortec_pvt_of_match); 636 637 static struct platform_driver moortec_pvt_driver = { 638 .driver = { 639 .name = "moortec-pvt", 640 .of_match_table = moortec_pvt_of_match, 641 }, 642 .probe = mr75203_probe, 643 }; 644 module_platform_driver(moortec_pvt_driver); 645 646 MODULE_LICENSE("GPL v2"); 647