1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C 4 * 5 * Copyright 2023 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/cleanup.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/hwmon.h> 15 #include <linux/hwmon-sysfs.h> 16 #include <linux/i2c.h> 17 #include <linux/math.h> 18 #include <linux/minmax.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/mutex.h> 22 #include <linux/regmap.h> 23 #include <linux/property.h> 24 #include <linux/string.h> 25 #include <linux/units.h> 26 #include <linux/util_macros.h> 27 28 #define LTC4282_CTRL_LSB 0x00 29 #define LTC4282_CTRL_OV_RETRY_MASK BIT(0) 30 #define LTC4282_CTRL_UV_RETRY_MASK BIT(1) 31 #define LTC4282_CTRL_OC_RETRY_MASK BIT(2) 32 #define LTC4282_CTRL_ON_ACTIVE_LOW_MASK BIT(5) 33 #define LTC4282_CTRL_ON_DELAY_MASK BIT(6) 34 #define LTC4282_CTRL_MSB 0x01 35 #define LTC4282_CTRL_VIN_MODE_MASK GENMASK(1, 0) 36 #define LTC4282_CTRL_OV_MODE_MASK GENMASK(3, 2) 37 #define LTC4282_CTRL_UV_MODE_MASK GENMASK(5, 4) 38 #define LTC4282_FAULT_LOG 0x04 39 #define LTC4282_OV_FAULT_MASK BIT(0) 40 #define LTC4282_UV_FAULT_MASK BIT(1) 41 #define LTC4282_VDD_FAULT_MASK \ 42 (LTC4282_OV_FAULT_MASK | LTC4282_UV_FAULT_MASK) 43 #define LTC4282_OC_FAULT_MASK BIT(2) 44 #define LTC4282_POWER_BAD_FAULT_MASK BIT(3) 45 #define LTC4282_FET_SHORT_FAULT_MASK BIT(5) 46 #define LTC4282_FET_BAD_FAULT_MASK BIT(6) 47 #define LTC4282_FET_FAILURE_FAULT_MASK \ 48 (LTC4282_FET_SHORT_FAULT_MASK | LTC4282_FET_BAD_FAULT_MASK) 49 #define LTC4282_ADC_ALERT_LOG 0x05 50 #define LTC4282_GPIO_ALARM_L_MASK BIT(0) 51 #define LTC4282_GPIO_ALARM_H_MASK BIT(1) 52 #define LTC4282_VSOURCE_ALARM_L_MASK BIT(2) 53 #define LTC4282_VSOURCE_ALARM_H_MASK BIT(3) 54 #define LTC4282_VSENSE_ALARM_L_MASK BIT(4) 55 #define LTC4282_VSENSE_ALARM_H_MASK BIT(5) 56 #define LTC4282_POWER_ALARM_L_MASK BIT(6) 57 #define LTC4282_POWER_ALARM_H_MASK BIT(7) 58 #define LTC4282_FET_BAD_FAULT_TIMEOUT 0x06 59 #define LTC4282_FET_BAD_MAX_TIMEOUT 255 60 #define LTC4282_GPIO_CONFIG 0x07 61 #define LTC4282_GPIO_2_FET_STRESS_MASK BIT(1) 62 #define LTC4282_GPIO_1_CONFIG_MASK GENMASK(5, 4) 63 #define LTC4282_VGPIO_MIN 0x08 64 #define LTC4282_VGPIO_MAX 0x09 65 #define LTC4282_VSOURCE_MIN 0x0a 66 #define LTC4282_VSOURCE_MAX 0x0b 67 #define LTC4282_VSENSE_MIN 0x0c 68 #define LTC4282_VSENSE_MAX 0x0d 69 #define LTC4282_POWER_MIN 0x0e 70 #define LTC4282_POWER_MAX 0x0f 71 #define LTC4282_CLK_DIV 0x10 72 #define LTC4282_CLK_DIV_MASK GENMASK(4, 0) 73 #define LTC4282_CLKOUT_MASK GENMASK(6, 5) 74 #define LTC4282_ILIM_ADJUST 0x11 75 #define LTC4282_GPIO_MODE_MASK BIT(1) 76 #define LTC4282_VDD_MONITOR_MASK BIT(2) 77 #define LTC4282_FOLDBACK_MODE_MASK GENMASK(4, 3) 78 #define LTC4282_ILIM_ADJUST_MASK GENMASK(7, 5) 79 #define LTC4282_ENERGY 0x12 80 #define LTC4282_TIME_COUNTER 0x18 81 #define LTC4282_ALERT_CTRL 0x1c 82 #define LTC4282_ALERT_OUT_MASK BIT(6) 83 #define LTC4282_ADC_CTRL 0x1d 84 #define LTC4282_FAULT_LOG_EN_MASK BIT(2) 85 #define LTC4282_METER_HALT_MASK BIT(5) 86 #define LTC4282_METER_RESET_MASK BIT(6) 87 #define LTC4282_RESET_MASK BIT(7) 88 #define LTC4282_STATUS_LSB 0x1e 89 #define LTC4282_OV_STATUS_MASK BIT(0) 90 #define LTC4282_UV_STATUS_MASK BIT(1) 91 #define LTC4282_VDD_STATUS_MASK \ 92 (LTC4282_OV_STATUS_MASK | LTC4282_UV_STATUS_MASK) 93 #define LTC4282_OC_STATUS_MASK BIT(2) 94 #define LTC4282_POWER_GOOD_MASK BIT(3) 95 #define LTC4282_FET_FAILURE_MASK GENMASK(6, 5) 96 #define LTC4282_STATUS_MSB 0x1f 97 #define LTC4282_RESERVED_1 0x32 98 #define LTC4282_RESERVED_2 0x33 99 #define LTC4282_VGPIO 0x34 100 #define LTC4282_VGPIO_LOWEST 0x36 101 #define LTC4282_VGPIO_HIGHEST 0x38 102 #define LTC4282_VSOURCE 0x3a 103 #define LTC4282_VSOURCE_LOWEST 0x3c 104 #define LTC4282_VSOURCE_HIGHEST 0x3e 105 #define LTC4282_VSENSE 0x40 106 #define LTC4282_VSENSE_LOWEST 0x42 107 #define LTC4282_VSENSE_HIGHEST 0x44 108 #define LTC4282_POWER 0x46 109 #define LTC4282_POWER_LOWEST 0x48 110 #define LTC4282_POWER_HIGHEST 0x4a 111 #define LTC4282_RESERVED_3 0x50 112 113 #define LTC4282_CLKIN_MIN (250 * KILO) 114 #define LTC4282_CLKIN_MAX (15500 * KILO) 115 #define LTC4282_CLKIN_RANGE (LTC4282_CLKIN_MAX - LTC4282_CLKIN_MIN + 1) 116 #define LTC4282_CLKOUT_SYSTEM (250 * KILO) 117 #define LTC4282_CLKOUT_CNV 15 118 119 enum { 120 LTC4282_CHAN_VSOURCE, 121 LTC4282_CHAN_VDD, 122 LTC4282_CHAN_VGPIO, 123 }; 124 125 struct ltc4282_cache { 126 u32 in_max_raw; 127 u32 in_min_raw; 128 long in_highest; 129 long in_lowest; 130 bool en; 131 }; 132 133 struct ltc4282_state { 134 struct regmap *map; 135 /* Protect against multiple accesses to the device registers */ 136 struct mutex lock; 137 struct clk_hw clk_hw; 138 /* 139 * Used to cache values for VDD/VSOURCE depending which will be used 140 * when hwmon is not enabled for that channel. Needed because they share 141 * the same registers. 142 */ 143 struct ltc4282_cache in0_1_cache[LTC4282_CHAN_VGPIO]; 144 u32 vsense_max; 145 long power_max; 146 u32 rsense; 147 u16 vdd; 148 u16 vfs_out; 149 bool energy_en; 150 }; 151 152 enum { 153 LTC4282_CLKOUT_NONE, 154 LTC4282_CLKOUT_INT, 155 LTC4282_CLKOUT_TICK, 156 }; 157 158 static int ltc4282_set_rate(struct clk_hw *hw, 159 unsigned long rate, unsigned long parent_rate) 160 { 161 struct ltc4282_state *st = container_of(hw, struct ltc4282_state, 162 clk_hw); 163 u32 val = LTC4282_CLKOUT_INT; 164 165 if (rate == LTC4282_CLKOUT_CNV) 166 val = LTC4282_CLKOUT_TICK; 167 168 return regmap_update_bits(st->map, LTC4282_CLK_DIV, LTC4282_CLKOUT_MASK, 169 FIELD_PREP(LTC4282_CLKOUT_MASK, val)); 170 } 171 172 /* 173 * Note the 15HZ conversion rate assumes 12bit ADC which is what we are 174 * supporting for now. 175 */ 176 static const unsigned int ltc4282_out_rates[] = { 177 LTC4282_CLKOUT_CNV, LTC4282_CLKOUT_SYSTEM 178 }; 179 180 static long ltc4282_round_rate(struct clk_hw *hw, unsigned long rate, 181 unsigned long *parent_rate) 182 { 183 int idx = find_closest(rate, ltc4282_out_rates, 184 ARRAY_SIZE(ltc4282_out_rates)); 185 186 return ltc4282_out_rates[idx]; 187 } 188 189 static unsigned long ltc4282_recalc_rate(struct clk_hw *hw, 190 unsigned long parent) 191 { 192 struct ltc4282_state *st = container_of(hw, struct ltc4282_state, 193 clk_hw); 194 u32 clkdiv; 195 int ret; 196 197 ret = regmap_read(st->map, LTC4282_CLK_DIV, &clkdiv); 198 if (ret) 199 return 0; 200 201 clkdiv = FIELD_GET(LTC4282_CLKOUT_MASK, clkdiv); 202 if (!clkdiv) 203 return 0; 204 if (clkdiv == LTC4282_CLKOUT_INT) 205 return LTC4282_CLKOUT_SYSTEM; 206 207 return LTC4282_CLKOUT_CNV; 208 } 209 210 static void ltc4282_disable(struct clk_hw *clk_hw) 211 { 212 struct ltc4282_state *st = container_of(clk_hw, struct ltc4282_state, 213 clk_hw); 214 215 regmap_clear_bits(st->map, LTC4282_CLK_DIV, LTC4282_CLKOUT_MASK); 216 } 217 218 static int ltc4282_read_voltage_word(const struct ltc4282_state *st, u32 reg, 219 u32 fs, long *val) 220 { 221 __be16 in; 222 int ret; 223 224 ret = regmap_bulk_read(st->map, reg, &in, sizeof(in)); 225 if (ret) 226 return ret; 227 228 /* 229 * This is also used to calculate current in which case fs comes in 230 * 10 * uV. Hence the ULL usage. 231 */ 232 *val = DIV_ROUND_CLOSEST_ULL(be16_to_cpu(in) * (u64)fs, U16_MAX); 233 return 0; 234 } 235 236 static int ltc4282_read_voltage_byte_cached(const struct ltc4282_state *st, 237 u32 reg, u32 fs, long *val, 238 u32 *cached_raw) 239 { 240 int ret; 241 u32 in; 242 243 if (cached_raw) { 244 in = *cached_raw; 245 } else { 246 ret = regmap_read(st->map, reg, &in); 247 if (ret) 248 return ret; 249 } 250 251 *val = DIV_ROUND_CLOSEST(in * fs, U8_MAX); 252 return 0; 253 } 254 255 static int ltc4282_read_voltage_byte(const struct ltc4282_state *st, u32 reg, 256 u32 fs, long *val) 257 { 258 return ltc4282_read_voltage_byte_cached(st, reg, fs, val, NULL); 259 } 260 261 static int __ltc4282_read_alarm(struct ltc4282_state *st, u32 reg, u32 mask, 262 long *val) 263 { 264 u32 alarm; 265 int ret; 266 267 ret = regmap_read(st->map, reg, &alarm); 268 if (ret) 269 return ret; 270 271 *val = !!(alarm & mask); 272 273 /* if not status/fault logs, clear the alarm after reading it */ 274 if (reg != LTC4282_STATUS_LSB && reg != LTC4282_FAULT_LOG) 275 return regmap_clear_bits(st->map, reg, mask); 276 277 return 0; 278 } 279 280 static int ltc4282_read_alarm(struct ltc4282_state *st, u32 reg, u32 mask, 281 long *val) 282 { 283 guard(mutex)(&st->lock); 284 return __ltc4282_read_alarm(st, reg, mask, val); 285 } 286 287 static int ltc4282_vdd_source_read_in(struct ltc4282_state *st, u32 channel, 288 long *val) 289 { 290 guard(mutex)(&st->lock); 291 if (!st->in0_1_cache[channel].en) 292 return -ENODATA; 293 294 return ltc4282_read_voltage_word(st, LTC4282_VSOURCE, st->vfs_out, val); 295 } 296 297 static int ltc4282_vdd_source_read_hist(struct ltc4282_state *st, u32 reg, 298 u32 channel, long *cached, long *val) 299 { 300 int ret; 301 302 guard(mutex)(&st->lock); 303 if (!st->in0_1_cache[channel].en) { 304 *val = *cached; 305 return 0; 306 } 307 308 ret = ltc4282_read_voltage_word(st, reg, st->vfs_out, val); 309 if (ret) 310 return ret; 311 312 *cached = *val; 313 return 0; 314 } 315 316 static int ltc4282_vdd_source_read_lim(struct ltc4282_state *st, u32 reg, 317 u32 channel, u32 *cached, long *val) 318 { 319 guard(mutex)(&st->lock); 320 if (!st->in0_1_cache[channel].en) 321 return ltc4282_read_voltage_byte_cached(st, reg, st->vfs_out, 322 val, cached); 323 324 return ltc4282_read_voltage_byte(st, reg, st->vfs_out, val); 325 } 326 327 static int ltc4282_vdd_source_read_alm(struct ltc4282_state *st, u32 mask, 328 u32 channel, long *val) 329 { 330 guard(mutex)(&st->lock); 331 if (!st->in0_1_cache[channel].en) { 332 /* 333 * Do this otherwise alarms can get confused because we clear 334 * them after reading them. So, if someone mistakenly reads 335 * VSOURCE right before VDD (or the other way around), we might 336 * get no alarm just because it was cleared when reading VSOURCE 337 * and had no time for a new conversion and thus having the 338 * alarm again. 339 */ 340 *val = 0; 341 return 0; 342 } 343 344 return __ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, mask, val); 345 } 346 347 static int ltc4282_read_in(struct ltc4282_state *st, u32 attr, long *val, 348 u32 channel) 349 { 350 switch (attr) { 351 case hwmon_in_input: 352 if (channel == LTC4282_CHAN_VGPIO) 353 return ltc4282_read_voltage_word(st, LTC4282_VGPIO, 354 1280, val); 355 356 return ltc4282_vdd_source_read_in(st, channel, val); 357 case hwmon_in_highest: 358 if (channel == LTC4282_CHAN_VGPIO) 359 return ltc4282_read_voltage_word(st, 360 LTC4282_VGPIO_HIGHEST, 361 1280, val); 362 363 return ltc4282_vdd_source_read_hist(st, LTC4282_VSOURCE_HIGHEST, 364 channel, 365 &st->in0_1_cache[channel].in_highest, val); 366 case hwmon_in_lowest: 367 if (channel == LTC4282_CHAN_VGPIO) 368 return ltc4282_read_voltage_word(st, LTC4282_VGPIO_LOWEST, 369 1280, val); 370 371 return ltc4282_vdd_source_read_hist(st, LTC4282_VSOURCE_LOWEST, 372 channel, 373 &st->in0_1_cache[channel].in_lowest, val); 374 case hwmon_in_max_alarm: 375 if (channel == LTC4282_CHAN_VGPIO) 376 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 377 LTC4282_GPIO_ALARM_H_MASK, 378 val); 379 380 return ltc4282_vdd_source_read_alm(st, 381 LTC4282_VSOURCE_ALARM_H_MASK, 382 channel, val); 383 case hwmon_in_min_alarm: 384 if (channel == LTC4282_CHAN_VGPIO) 385 ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 386 LTC4282_GPIO_ALARM_L_MASK, val); 387 388 return ltc4282_vdd_source_read_alm(st, 389 LTC4282_VSOURCE_ALARM_L_MASK, 390 channel, val); 391 case hwmon_in_crit_alarm: 392 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 393 LTC4282_OV_STATUS_MASK, val); 394 case hwmon_in_lcrit_alarm: 395 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 396 LTC4282_UV_STATUS_MASK, val); 397 case hwmon_in_max: 398 if (channel == LTC4282_CHAN_VGPIO) 399 return ltc4282_read_voltage_byte(st, LTC4282_VGPIO_MAX, 400 1280, val); 401 402 return ltc4282_vdd_source_read_lim(st, LTC4282_VSOURCE_MAX, 403 channel, 404 &st->in0_1_cache[channel].in_max_raw, val); 405 case hwmon_in_min: 406 if (channel == LTC4282_CHAN_VGPIO) 407 return ltc4282_read_voltage_byte(st, LTC4282_VGPIO_MIN, 408 1280, val); 409 410 return ltc4282_vdd_source_read_lim(st, LTC4282_VSOURCE_MIN, 411 channel, 412 &st->in0_1_cache[channel].in_min_raw, val); 413 case hwmon_in_enable: 414 scoped_guard(mutex, &st->lock) { 415 *val = st->in0_1_cache[channel].en; 416 } 417 return 0; 418 case hwmon_in_fault: 419 /* 420 * We report failure if we detect either a fer_bad or a 421 * fet_short in the status register. 422 */ 423 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 424 LTC4282_FET_FAILURE_MASK, val); 425 default: 426 return -EOPNOTSUPP; 427 } 428 } 429 430 static int ltc4282_read_current_word(const struct ltc4282_state *st, u32 reg, 431 long *val) 432 { 433 long in; 434 int ret; 435 436 /* 437 * We pass in full scale in 10 * micro (note that 40 is already 438 * millivolt) so we have better approximations to calculate current. 439 */ 440 ret = ltc4282_read_voltage_word(st, reg, DECA * 40 * MILLI, &in); 441 if (ret) 442 return ret; 443 444 *val = DIV_ROUND_CLOSEST(in * MILLI, st->rsense); 445 446 return 0; 447 } 448 449 static int ltc4282_read_current_byte(const struct ltc4282_state *st, u32 reg, 450 long *val) 451 { 452 long in; 453 int ret; 454 455 ret = ltc4282_read_voltage_byte(st, reg, DECA * 40 * MILLI, &in); 456 if (ret) 457 return ret; 458 459 *val = DIV_ROUND_CLOSEST(in * MILLI, st->rsense); 460 461 return 0; 462 } 463 464 static int ltc4282_read_curr(struct ltc4282_state *st, const u32 attr, 465 long *val) 466 { 467 switch (attr) { 468 case hwmon_curr_input: 469 return ltc4282_read_current_word(st, LTC4282_VSENSE, val); 470 case hwmon_curr_highest: 471 return ltc4282_read_current_word(st, LTC4282_VSENSE_HIGHEST, 472 val); 473 case hwmon_curr_lowest: 474 return ltc4282_read_current_word(st, LTC4282_VSENSE_LOWEST, 475 val); 476 case hwmon_curr_max: 477 return ltc4282_read_current_byte(st, LTC4282_VSENSE_MAX, val); 478 case hwmon_curr_min: 479 return ltc4282_read_current_byte(st, LTC4282_VSENSE_MIN, val); 480 case hwmon_curr_max_alarm: 481 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 482 LTC4282_VSENSE_ALARM_H_MASK, val); 483 case hwmon_curr_min_alarm: 484 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 485 LTC4282_VSENSE_ALARM_L_MASK, val); 486 case hwmon_curr_crit_alarm: 487 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 488 LTC4282_OC_STATUS_MASK, val); 489 default: 490 return -EOPNOTSUPP; 491 } 492 } 493 494 static int ltc4282_read_power_word(const struct ltc4282_state *st, u32 reg, 495 long *val) 496 { 497 u64 temp = DECA * 40ULL * st->vfs_out * BIT(16), temp_2; 498 __be16 raw; 499 u16 power; 500 int ret; 501 502 ret = regmap_bulk_read(st->map, reg, &raw, sizeof(raw)); 503 if (ret) 504 return ret; 505 506 power = be16_to_cpu(raw); 507 /* 508 * Power is given by: 509 * P = CODE(16b) * 0.040 * Vfs(out) * 2^16 / ((2^16 - 1)^2 * Rsense) 510 */ 511 if (check_mul_overflow(power * temp, MICRO, &temp_2)) { 512 temp = DIV_ROUND_CLOSEST_ULL(power * temp, U16_MAX); 513 *val = DIV64_U64_ROUND_CLOSEST(temp * MICRO, 514 U16_MAX * (u64)st->rsense); 515 return 0; 516 } 517 518 *val = DIV64_U64_ROUND_CLOSEST(temp_2, 519 st->rsense * int_pow(U16_MAX, 2)); 520 521 return 0; 522 } 523 524 static int ltc4282_read_power_byte(const struct ltc4282_state *st, u32 reg, 525 long *val) 526 { 527 u32 power; 528 u64 temp; 529 int ret; 530 531 ret = regmap_read(st->map, reg, &power); 532 if (ret) 533 return ret; 534 535 temp = power * 40 * DECA * st->vfs_out * BIT_ULL(8); 536 *val = DIV64_U64_ROUND_CLOSEST(temp * MICRO, 537 int_pow(U8_MAX, 2) * st->rsense); 538 539 return 0; 540 } 541 542 static int ltc4282_read_energy(const struct ltc4282_state *st, u64 *val) 543 { 544 u64 temp, energy; 545 __be64 raw; 546 int ret; 547 548 ret = regmap_bulk_read(st->map, LTC4282_ENERGY, &raw, 6); 549 if (ret) 550 return ret; 551 552 energy = be64_to_cpu(raw) >> 16; 553 /* 554 * The formula for energy is given by: 555 * E = CODE(48b) * 0.040 * Vfs(out) * Tconv * 256 / 556 * ((2^16 - 1)^2 * Rsense) 557 * 558 * Since we only support 12bit ADC, Tconv = 0.065535s. Passing Vfs(out) 559 * and 0.040 to mV and Tconv to us, we can simplify the formula to: 560 * E = CODE(48b) * 40 * Vfs(out) * 256 / (U16_MAX * Rsense) 561 * 562 * As Rsense can have tenths of micro-ohm resolution, we need to 563 * multiply by DECA to get microujoule. 564 */ 565 if (check_mul_overflow(DECA * st->vfs_out * 40 * BIT(8), energy, &temp)) { 566 temp = DIV_ROUND_CLOSEST(DECA * st->vfs_out * 40 * BIT(8), U16_MAX); 567 *val = DIV_ROUND_CLOSEST_ULL(temp * energy, st->rsense); 568 return 0; 569 } 570 571 *val = DIV64_U64_ROUND_CLOSEST(temp, U16_MAX * (u64)st->rsense); 572 573 return 0; 574 } 575 576 static int ltc4282_read_power(struct ltc4282_state *st, const u32 attr, 577 long *val) 578 { 579 switch (attr) { 580 case hwmon_power_input: 581 return ltc4282_read_power_word(st, LTC4282_POWER, val); 582 case hwmon_power_input_highest: 583 return ltc4282_read_power_word(st, LTC4282_POWER_HIGHEST, val); 584 case hwmon_power_input_lowest: 585 return ltc4282_read_power_word(st, LTC4282_POWER_LOWEST, val); 586 case hwmon_power_max_alarm: 587 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 588 LTC4282_POWER_ALARM_H_MASK, val); 589 case hwmon_power_min_alarm: 590 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 591 LTC4282_POWER_ALARM_L_MASK, val); 592 case hwmon_power_max: 593 return ltc4282_read_power_byte(st, LTC4282_POWER_MAX, val); 594 case hwmon_power_min: 595 return ltc4282_read_power_byte(st, LTC4282_POWER_MIN, val); 596 default: 597 return -EOPNOTSUPP; 598 } 599 } 600 601 static int ltc4282_read(struct device *dev, enum hwmon_sensor_types type, 602 u32 attr, int channel, long *val) 603 { 604 struct ltc4282_state *st = dev_get_drvdata(dev); 605 606 switch (type) { 607 case hwmon_in: 608 return ltc4282_read_in(st, attr, val, channel); 609 case hwmon_curr: 610 return ltc4282_read_curr(st, attr, val); 611 case hwmon_power: 612 return ltc4282_read_power(st, attr, val); 613 case hwmon_energy: 614 scoped_guard(mutex, &st->lock) { 615 *val = st->energy_en; 616 } 617 return 0; 618 default: 619 return -EOPNOTSUPP; 620 } 621 } 622 623 static int ltc4282_write_power_byte(const struct ltc4282_state *st, u32 reg, 624 long val) 625 { 626 u32 power; 627 u64 temp; 628 629 if (val > st->power_max) 630 val = st->power_max; 631 632 temp = val * int_pow(U8_MAX, 2) * st->rsense; 633 power = DIV64_U64_ROUND_CLOSEST(temp, 634 MICRO * DECA * 256ULL * st->vfs_out * 40); 635 636 return regmap_write(st->map, reg, power); 637 } 638 639 static int ltc4282_write_power_word(const struct ltc4282_state *st, u32 reg, 640 long val) 641 { 642 u64 temp = int_pow(U16_MAX, 2) * st->rsense, temp_2; 643 __be16 __raw; 644 u16 code; 645 646 if (check_mul_overflow(temp, val, &temp_2)) { 647 temp = DIV_ROUND_CLOSEST_ULL(temp, DECA * MICRO); 648 code = DIV64_U64_ROUND_CLOSEST(temp * val, 649 40ULL * BIT(16) * st->vfs_out); 650 } else { 651 temp = DECA * MICRO * 40ULL * BIT(16) * st->vfs_out; 652 code = DIV64_U64_ROUND_CLOSEST(temp_2, temp); 653 } 654 655 __raw = cpu_to_be16(code); 656 return regmap_bulk_write(st->map, reg, &__raw, sizeof(__raw)); 657 } 658 659 static int __ltc4282_in_write_history(const struct ltc4282_state *st, u32 reg, 660 long lowest, long highest, u32 fs) 661 { 662 __be16 __raw; 663 u16 tmp; 664 int ret; 665 666 tmp = DIV_ROUND_CLOSEST(U16_MAX * lowest, fs); 667 668 __raw = cpu_to_be16(tmp); 669 670 ret = regmap_bulk_write(st->map, reg, &__raw, 2); 671 if (ret) 672 return ret; 673 674 tmp = DIV_ROUND_CLOSEST(U16_MAX * highest, fs); 675 676 __raw = cpu_to_be16(tmp); 677 678 return regmap_bulk_write(st->map, reg + 2, &__raw, 2); 679 } 680 681 static int ltc4282_in_write_history(struct ltc4282_state *st, u32 reg, 682 long lowest, long highest, u32 fs) 683 { 684 guard(mutex)(&st->lock); 685 return __ltc4282_in_write_history(st, reg, lowest, highest, fs); 686 } 687 688 static int ltc4282_power_reset_hist(struct ltc4282_state *st) 689 { 690 int ret; 691 692 guard(mutex)(&st->lock); 693 694 ret = ltc4282_write_power_word(st, LTC4282_POWER_LOWEST, 695 st->power_max); 696 if (ret) 697 return ret; 698 699 ret = ltc4282_write_power_word(st, LTC4282_POWER_HIGHEST, 0); 700 if (ret) 701 return ret; 702 703 /* now, let's also clear possible power_bad fault logs */ 704 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 705 LTC4282_POWER_BAD_FAULT_MASK); 706 } 707 708 static int ltc4282_write_power(struct ltc4282_state *st, u32 attr, 709 long val) 710 { 711 switch (attr) { 712 case hwmon_power_max: 713 return ltc4282_write_power_byte(st, LTC4282_POWER_MAX, val); 714 case hwmon_power_min: 715 return ltc4282_write_power_byte(st, LTC4282_POWER_MIN, val); 716 case hwmon_power_reset_history: 717 return ltc4282_power_reset_hist(st); 718 default: 719 return -EOPNOTSUPP; 720 } 721 } 722 723 static int ltc4282_write_voltage_byte_cached(const struct ltc4282_state *st, 724 u32 reg, u32 fs, long val, 725 u32 *cache_raw) 726 { 727 u32 in; 728 729 val = clamp_val(val, 0, fs); 730 in = DIV_ROUND_CLOSEST(val * U8_MAX, fs); 731 732 if (cache_raw) { 733 *cache_raw = in; 734 return 0; 735 } 736 737 return regmap_write(st->map, reg, in); 738 } 739 740 static int ltc4282_write_voltage_byte(const struct ltc4282_state *st, u32 reg, 741 u32 fs, long val) 742 { 743 return ltc4282_write_voltage_byte_cached(st, reg, fs, val, NULL); 744 } 745 746 static int ltc4282_cache_history(struct ltc4282_state *st, u32 channel) 747 { 748 long val; 749 int ret; 750 751 ret = ltc4282_read_voltage_word(st, LTC4282_VSOURCE_LOWEST, st->vfs_out, 752 &val); 753 if (ret) 754 return ret; 755 756 st->in0_1_cache[channel].in_lowest = val; 757 758 ret = ltc4282_read_voltage_word(st, LTC4282_VSOURCE_HIGHEST, 759 st->vfs_out, &val); 760 if (ret) 761 return ret; 762 763 st->in0_1_cache[channel].in_highest = val; 764 765 ret = regmap_read(st->map, LTC4282_VSOURCE_MIN, 766 &st->in0_1_cache[channel].in_min_raw); 767 if (ret) 768 return ret; 769 770 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 771 &st->in0_1_cache[channel].in_max_raw); 772 } 773 774 static int ltc4282_cache_sync(struct ltc4282_state *st, u32 channel) 775 { 776 int ret; 777 778 ret = __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 779 st->in0_1_cache[channel].in_lowest, 780 st->in0_1_cache[channel].in_highest, 781 st->vfs_out); 782 if (ret) 783 return ret; 784 785 ret = regmap_write(st->map, LTC4282_VSOURCE_MIN, 786 st->in0_1_cache[channel].in_min_raw); 787 if (ret) 788 return ret; 789 790 return regmap_write(st->map, LTC4282_VSOURCE_MAX, 791 st->in0_1_cache[channel].in_max_raw); 792 } 793 794 static int ltc4282_vdd_source_write_lim(struct ltc4282_state *st, u32 reg, 795 int channel, u32 *cache, long val) 796 { 797 int ret; 798 799 guard(mutex)(&st->lock); 800 if (st->in0_1_cache[channel].en) 801 ret = ltc4282_write_voltage_byte(st, reg, st->vfs_out, val); 802 else 803 ret = ltc4282_write_voltage_byte_cached(st, reg, st->vfs_out, 804 val, cache); 805 806 return ret; 807 } 808 809 static int ltc4282_vdd_source_reset_hist(struct ltc4282_state *st, int channel) 810 { 811 long lowest = st->vfs_out; 812 int ret; 813 814 if (channel == LTC4282_CHAN_VDD) 815 lowest = st->vdd; 816 817 guard(mutex)(&st->lock); 818 if (st->in0_1_cache[channel].en) { 819 ret = __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 820 lowest, 0, st->vfs_out); 821 if (ret) 822 return ret; 823 } 824 825 st->in0_1_cache[channel].in_lowest = lowest; 826 st->in0_1_cache[channel].in_highest = 0; 827 828 /* 829 * We are also clearing possible fault logs in reset_history. Clearing 830 * the logs might be important when the auto retry bits are not enabled 831 * as the chip only enables the output again after having these logs 832 * cleared. As some of these logs are related to limits, it makes sense 833 * to clear them in here. For VDD, we need to clear under/over voltage 834 * events. For VSOURCE, fet_short and fet_bad... 835 */ 836 if (channel == LTC4282_CHAN_VSOURCE) 837 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 838 LTC4282_FET_FAILURE_FAULT_MASK); 839 840 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 841 LTC4282_VDD_FAULT_MASK); 842 } 843 844 /* 845 * We need to mux between VSOURCE and VDD which means they are mutually 846 * exclusive. Moreover, we can't really disable both VDD and VSOURCE as the ADC 847 * is continuously running (we cannot independently halt it without also 848 * stopping VGPIO). Hence, the logic is that disabling or enabling VDD will 849 * automatically have the reverse effect on VSOURCE and vice-versa. 850 */ 851 static int ltc4282_vdd_source_enable(struct ltc4282_state *st, int channel, 852 long val) 853 { 854 int ret, other_chan = ~channel & 0x1; 855 u8 __val = val; 856 857 guard(mutex)(&st->lock); 858 if (st->in0_1_cache[channel].en == !!val) 859 return 0; 860 861 /* clearing the bit makes the ADC to monitor VDD */ 862 if (channel == LTC4282_CHAN_VDD) 863 __val = !__val; 864 865 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 866 LTC4282_VDD_MONITOR_MASK, 867 FIELD_PREP(LTC4282_VDD_MONITOR_MASK, !!__val)); 868 if (ret) 869 return ret; 870 871 st->in0_1_cache[channel].en = !!val; 872 st->in0_1_cache[other_chan].en = !val; 873 874 if (st->in0_1_cache[channel].en) { 875 /* 876 * Then, we are disabling @other_chan. Let's save it's current 877 * history. 878 */ 879 ret = ltc4282_cache_history(st, other_chan); 880 if (ret) 881 return ret; 882 883 return ltc4282_cache_sync(st, channel); 884 } 885 /* 886 * Then, we are enabling @other_chan. We need to do the opposite from 887 * above. 888 */ 889 ret = ltc4282_cache_history(st, channel); 890 if (ret) 891 return ret; 892 893 return ltc4282_cache_sync(st, other_chan); 894 } 895 896 static int ltc4282_write_in(struct ltc4282_state *st, u32 attr, long val, 897 int channel) 898 { 899 switch (attr) { 900 case hwmon_in_max: 901 if (channel == LTC4282_CHAN_VGPIO) 902 return ltc4282_write_voltage_byte(st, LTC4282_VGPIO_MAX, 903 1280, val); 904 905 return ltc4282_vdd_source_write_lim(st, LTC4282_VSOURCE_MAX, 906 channel, 907 &st->in0_1_cache[channel].in_max_raw, val); 908 case hwmon_in_min: 909 if (channel == LTC4282_CHAN_VGPIO) 910 return ltc4282_write_voltage_byte(st, LTC4282_VGPIO_MIN, 911 1280, val); 912 913 return ltc4282_vdd_source_write_lim(st, LTC4282_VSOURCE_MIN, 914 channel, 915 &st->in0_1_cache[channel].in_min_raw, val); 916 case hwmon_in_reset_history: 917 if (channel == LTC4282_CHAN_VGPIO) 918 return ltc4282_in_write_history(st, 919 LTC4282_VGPIO_LOWEST, 920 1280, 0, 1280); 921 922 return ltc4282_vdd_source_reset_hist(st, channel); 923 case hwmon_in_enable: 924 return ltc4282_vdd_source_enable(st, channel, val); 925 default: 926 return -EOPNOTSUPP; 927 } 928 } 929 930 static int ltc4282_curr_reset_hist(struct ltc4282_state *st) 931 { 932 int ret; 933 934 guard(mutex)(&st->lock); 935 936 ret = __ltc4282_in_write_history(st, LTC4282_VSENSE_LOWEST, 937 st->vsense_max, 0, 40 * MILLI); 938 if (ret) 939 return ret; 940 941 /* now, let's also clear possible overcurrent fault logs */ 942 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 943 LTC4282_OC_FAULT_MASK); 944 } 945 946 static int ltc4282_write_curr(struct ltc4282_state *st, u32 attr, 947 long val) 948 { 949 /* need to pass it in millivolt */ 950 u32 in = DIV_ROUND_CLOSEST_ULL((u64)val * st->rsense, DECA * MICRO); 951 952 switch (attr) { 953 case hwmon_curr_max: 954 return ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MAX, 40, 955 in); 956 case hwmon_curr_min: 957 return ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MIN, 40, 958 in); 959 case hwmon_curr_reset_history: 960 return ltc4282_curr_reset_hist(st); 961 default: 962 return -EOPNOTSUPP; 963 } 964 } 965 966 static int ltc4282_energy_enable_set(struct ltc4282_state *st, long val) 967 { 968 int ret; 969 970 guard(mutex)(&st->lock); 971 /* setting the bit halts the meter */ 972 ret = regmap_update_bits(st->map, LTC4282_ADC_CTRL, 973 LTC4282_METER_HALT_MASK, 974 FIELD_PREP(LTC4282_METER_HALT_MASK, !val)); 975 if (ret) 976 return ret; 977 978 st->energy_en = !!val; 979 980 return 0; 981 } 982 983 static int ltc4282_write(struct device *dev, 984 enum hwmon_sensor_types type, 985 u32 attr, int channel, long val) 986 { 987 struct ltc4282_state *st = dev_get_drvdata(dev); 988 989 switch (type) { 990 case hwmon_power: 991 return ltc4282_write_power(st, attr, val); 992 case hwmon_in: 993 return ltc4282_write_in(st, attr, val, channel); 994 case hwmon_curr: 995 return ltc4282_write_curr(st, attr, val); 996 case hwmon_energy: 997 return ltc4282_energy_enable_set(st, val); 998 default: 999 return -EOPNOTSUPP; 1000 } 1001 } 1002 1003 static umode_t ltc4282_in_is_visible(const struct ltc4282_state *st, u32 attr) 1004 { 1005 switch (attr) { 1006 case hwmon_in_input: 1007 case hwmon_in_highest: 1008 case hwmon_in_lowest: 1009 case hwmon_in_max_alarm: 1010 case hwmon_in_min_alarm: 1011 case hwmon_in_label: 1012 case hwmon_in_lcrit_alarm: 1013 case hwmon_in_crit_alarm: 1014 case hwmon_in_fault: 1015 return 0444; 1016 case hwmon_in_max: 1017 case hwmon_in_min: 1018 case hwmon_in_enable: 1019 case hwmon_in_reset_history: 1020 return 0644; 1021 default: 1022 return 0; 1023 } 1024 } 1025 1026 static umode_t ltc4282_curr_is_visible(u32 attr) 1027 { 1028 switch (attr) { 1029 case hwmon_curr_input: 1030 case hwmon_curr_highest: 1031 case hwmon_curr_lowest: 1032 case hwmon_curr_max_alarm: 1033 case hwmon_curr_min_alarm: 1034 case hwmon_curr_crit_alarm: 1035 case hwmon_curr_label: 1036 return 0444; 1037 case hwmon_curr_max: 1038 case hwmon_curr_min: 1039 case hwmon_curr_reset_history: 1040 return 0644; 1041 default: 1042 return 0; 1043 } 1044 } 1045 1046 static umode_t ltc4282_power_is_visible(u32 attr) 1047 { 1048 switch (attr) { 1049 case hwmon_power_input: 1050 case hwmon_power_input_highest: 1051 case hwmon_power_input_lowest: 1052 case hwmon_power_label: 1053 case hwmon_power_max_alarm: 1054 case hwmon_power_min_alarm: 1055 return 0444; 1056 case hwmon_power_max: 1057 case hwmon_power_min: 1058 case hwmon_power_reset_history: 1059 return 0644; 1060 default: 1061 return 0; 1062 } 1063 } 1064 1065 static umode_t ltc4282_is_visible(const void *data, 1066 enum hwmon_sensor_types type, 1067 u32 attr, int channel) 1068 { 1069 switch (type) { 1070 case hwmon_in: 1071 return ltc4282_in_is_visible(data, attr); 1072 case hwmon_curr: 1073 return ltc4282_curr_is_visible(attr); 1074 case hwmon_power: 1075 return ltc4282_power_is_visible(attr); 1076 case hwmon_energy: 1077 /* hwmon_energy_enable */ 1078 return 0644; 1079 default: 1080 return 0; 1081 } 1082 } 1083 1084 static const char * const ltc4282_in_strs[] = { 1085 "VSOURCE", "VDD", "VGPIO" 1086 }; 1087 1088 static int ltc4282_read_labels(struct device *dev, 1089 enum hwmon_sensor_types type, 1090 u32 attr, int channel, const char **str) 1091 { 1092 switch (type) { 1093 case hwmon_in: 1094 *str = ltc4282_in_strs[channel]; 1095 return 0; 1096 case hwmon_curr: 1097 *str = "ISENSE"; 1098 return 0; 1099 case hwmon_power: 1100 *str = "Power"; 1101 return 0; 1102 default: 1103 return -EOPNOTSUPP; 1104 } 1105 } 1106 1107 static ssize_t ltc4282_energy_show(struct device *dev, 1108 struct device_attribute *da, char *buf) 1109 { 1110 struct ltc4282_state *st = dev_get_drvdata(dev); 1111 u64 energy; 1112 int ret; 1113 1114 guard(mutex)(&st->lock); 1115 if (!st->energy_en) 1116 return -ENODATA; 1117 1118 ret = ltc4282_read_energy(st, &energy); 1119 if (ret < 0) 1120 return ret; 1121 1122 return sysfs_emit(buf, "%llu\n", energy); 1123 } 1124 1125 static const struct clk_ops ltc4282_ops = { 1126 .recalc_rate = ltc4282_recalc_rate, 1127 .round_rate = ltc4282_round_rate, 1128 .set_rate = ltc4282_set_rate, 1129 .disable = ltc4282_disable, 1130 }; 1131 1132 static int ltc428_clk_provider_setup(struct ltc4282_state *st, 1133 struct device *dev) 1134 { 1135 struct clk_init_data init; 1136 int ret; 1137 1138 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1139 return 0; 1140 1141 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", 1142 fwnode_get_name(dev_fwnode(dev))); 1143 if (!init.name) 1144 return -ENOMEM; 1145 1146 init.ops = <c4282_ops; 1147 init.flags = CLK_GET_RATE_NOCACHE; 1148 st->clk_hw.init = &init; 1149 1150 ret = devm_clk_hw_register(dev, &st->clk_hw); 1151 if (ret) 1152 return ret; 1153 1154 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1155 &st->clk_hw); 1156 } 1157 1158 static int ltc428_clks_setup(struct ltc4282_state *st, struct device *dev) 1159 { 1160 unsigned long rate; 1161 struct clk *clkin; 1162 u32 val; 1163 int ret; 1164 1165 ret = ltc428_clk_provider_setup(st, dev); 1166 if (ret) 1167 return ret; 1168 1169 clkin = devm_clk_get_optional_enabled(dev, NULL); 1170 if (IS_ERR(clkin)) 1171 return dev_err_probe(dev, PTR_ERR(clkin), 1172 "Failed to get clkin"); 1173 if (!clkin) 1174 return 0; 1175 1176 rate = clk_get_rate(clkin); 1177 if (!in_range(rate, LTC4282_CLKIN_MIN, LTC4282_CLKIN_RANGE)) 1178 return dev_err_probe(dev, -EINVAL, 1179 "Invalid clkin range(%lu) [%lu %lu]\n", 1180 rate, LTC4282_CLKIN_MIN, 1181 LTC4282_CLKIN_MAX); 1182 1183 /* 1184 * Clocks faster than 250KHZ should be reduced to 250KHZ. The clock 1185 * frequency is divided by twice the value in the register. 1186 */ 1187 val = rate / (2 * LTC4282_CLKIN_MIN); 1188 1189 return regmap_update_bits(st->map, LTC4282_CLK_DIV, 1190 LTC4282_CLK_DIV_MASK, 1191 FIELD_PREP(LTC4282_CLK_DIV_MASK, val)); 1192 } 1193 1194 static const int ltc4282_curr_lim_uv[] = { 1195 12500, 15625, 18750, 21875, 25000, 28125, 31250, 34375 1196 }; 1197 1198 static int ltc4282_get_defaults(struct ltc4282_state *st, u32 *vin_mode) 1199 { 1200 u32 reg_val, ilm_adjust; 1201 int ret; 1202 1203 ret = regmap_read(st->map, LTC4282_ADC_CTRL, ®_val); 1204 if (ret) 1205 return ret; 1206 1207 st->energy_en = !FIELD_GET(LTC4282_METER_HALT_MASK, reg_val); 1208 1209 ret = regmap_read(st->map, LTC4282_CTRL_MSB, ®_val); 1210 if (ret) 1211 return ret; 1212 1213 *vin_mode = FIELD_GET(LTC4282_CTRL_VIN_MODE_MASK, reg_val); 1214 1215 ret = regmap_read(st->map, LTC4282_ILIM_ADJUST, ®_val); 1216 if (ret) 1217 return ret; 1218 1219 ilm_adjust = FIELD_GET(LTC4282_ILIM_ADJUST_MASK, reg_val); 1220 st->vsense_max = ltc4282_curr_lim_uv[ilm_adjust]; 1221 1222 st->in0_1_cache[LTC4282_CHAN_VSOURCE].en = FIELD_GET(LTC4282_VDD_MONITOR_MASK, 1223 ilm_adjust); 1224 if (!st->in0_1_cache[LTC4282_CHAN_VSOURCE].en) { 1225 st->in0_1_cache[LTC4282_CHAN_VDD].en = true; 1226 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 1227 &st->in0_1_cache[LTC4282_CHAN_VSOURCE].in_max_raw); 1228 } 1229 1230 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 1231 &st->in0_1_cache[LTC4282_CHAN_VDD].in_max_raw); 1232 } 1233 1234 /* 1235 * Set max limits for ISENSE and Power as that depends on the max voltage on 1236 * rsense that is defined in ILIM_ADJUST. This is specially important for power 1237 * because for some rsense and vfsout values, if we allow the default raw 255 1238 * value, that would overflow long in 32bit archs when reading back the max 1239 * power limit. 1240 * 1241 * Also set meaningful historic values for VDD and VSOURCE 1242 * (0 would not mean much). 1243 */ 1244 static int ltc4282_set_max_limits(struct ltc4282_state *st) 1245 { 1246 int ret; 1247 1248 ret = ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MAX, 40 * MILLI, 1249 st->vsense_max); 1250 if (ret) 1251 return ret; 1252 1253 /* Power is given by ISENSE * Vout. */ 1254 st->power_max = DIV_ROUND_CLOSEST(st->vsense_max * DECA * MILLI, st->rsense) * st->vfs_out; 1255 ret = ltc4282_write_power_byte(st, LTC4282_POWER_MAX, st->power_max); 1256 if (ret) 1257 return ret; 1258 1259 if (st->in0_1_cache[LTC4282_CHAN_VDD].en) { 1260 st->in0_1_cache[LTC4282_CHAN_VSOURCE].in_lowest = st->vfs_out; 1261 return __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 1262 st->vdd, 0, st->vfs_out); 1263 } 1264 1265 st->in0_1_cache[LTC4282_CHAN_VDD].in_lowest = st->vdd; 1266 return __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 1267 st->vfs_out, 0, st->vfs_out); 1268 } 1269 1270 static const char * const ltc4282_gpio1_modes[] = { 1271 "power_bad", "power_good" 1272 }; 1273 1274 static const char * const ltc4282_gpio2_modes[] = { 1275 "adc_input", "stress_fet" 1276 }; 1277 1278 static int ltc4282_gpio_setup(struct ltc4282_state *st, struct device *dev) 1279 { 1280 const char *func = NULL; 1281 int ret; 1282 1283 ret = device_property_read_string(dev, "adi,gpio1-mode", &func); 1284 if (!ret) { 1285 ret = match_string(ltc4282_gpio1_modes, 1286 ARRAY_SIZE(ltc4282_gpio1_modes), func); 1287 if (ret < 0) 1288 return dev_err_probe(dev, ret, 1289 "Invalid func(%s) for gpio1\n", 1290 func); 1291 1292 ret = regmap_update_bits(st->map, LTC4282_GPIO_CONFIG, 1293 LTC4282_GPIO_1_CONFIG_MASK, 1294 FIELD_PREP(LTC4282_GPIO_1_CONFIG_MASK, ret)); 1295 if (ret) 1296 return ret; 1297 } 1298 1299 ret = device_property_read_string(dev, "adi,gpio2-mode", &func); 1300 if (!ret) { 1301 ret = match_string(ltc4282_gpio2_modes, 1302 ARRAY_SIZE(ltc4282_gpio2_modes), func); 1303 if (ret < 0) 1304 return dev_err_probe(dev, ret, 1305 "Invalid func(%s) for gpio2\n", 1306 func); 1307 if (!ret) { 1308 /* setting the bit to 1 so the ADC to monitors GPIO2 */ 1309 ret = regmap_set_bits(st->map, LTC4282_ILIM_ADJUST, 1310 LTC4282_GPIO_MODE_MASK); 1311 } else { 1312 ret = regmap_update_bits(st->map, LTC4282_GPIO_CONFIG, 1313 LTC4282_GPIO_2_FET_STRESS_MASK, 1314 FIELD_PREP(LTC4282_GPIO_2_FET_STRESS_MASK, 1)); 1315 } 1316 1317 if (ret) 1318 return ret; 1319 } 1320 1321 if (!device_property_read_bool(dev, "adi,gpio3-monitor-enable")) 1322 return 0; 1323 1324 if (func && !strcmp(func, "adc_input")) 1325 return dev_err_probe(dev, -EINVAL, 1326 "Cannot have both gpio2 and gpio3 muxed into the ADC"); 1327 1328 return regmap_clear_bits(st->map, LTC4282_ILIM_ADJUST, 1329 LTC4282_GPIO_MODE_MASK); 1330 } 1331 1332 static const char * const ltc4282_dividers[] = { 1333 "external", "vdd_5_percent", "vdd_10_percent", "vdd_15_percent" 1334 }; 1335 1336 /* This maps the Vout full scale for the given Vin mode */ 1337 static const u16 ltc4282_vfs_milli[] = { 5540, 8320, 16640, 33280 }; 1338 1339 static const u16 ltc4282_vdd_milli[] = { 3300, 5000, 12000, 24000 }; 1340 1341 enum { 1342 LTC4282_VIN_3_3V, 1343 LTC4282_VIN_5V, 1344 LTC4282_VIN_12V, 1345 LTC4282_VIN_24V, 1346 }; 1347 1348 static int ltc4282_setup(struct ltc4282_state *st, struct device *dev) 1349 { 1350 const char *divider; 1351 u32 val, vin_mode; 1352 int ret; 1353 1354 /* The part has an eeprom so let's get the needed defaults from it */ 1355 ret = ltc4282_get_defaults(st, &vin_mode); 1356 if (ret) 1357 return ret; 1358 1359 ret = device_property_read_u32(dev, "adi,rsense-nano-ohms", 1360 &st->rsense); 1361 if (ret) 1362 return dev_err_probe(dev, ret, 1363 "Failed to read adi,rsense-nano-ohms\n"); 1364 if (st->rsense < CENTI) 1365 return dev_err_probe(dev, -EINVAL, 1366 "adi,rsense-nano-ohms too small (< %lu)\n", 1367 CENTI); 1368 1369 /* 1370 * The resolution for rsense is tenths of micro (eg: 62.5 uOhm) which 1371 * means we need nano in the bindings. However, to make things easier to 1372 * handle (with respect to overflows) we divide it by 100 as we don't 1373 * really need the last two digits. 1374 */ 1375 st->rsense /= CENTI; 1376 1377 val = vin_mode; 1378 ret = device_property_read_u32(dev, "adi,vin-mode-microvolt", &val); 1379 if (!ret) { 1380 switch (val) { 1381 case 3300000: 1382 val = LTC4282_VIN_3_3V; 1383 break; 1384 case 5000000: 1385 val = LTC4282_VIN_5V; 1386 break; 1387 case 12000000: 1388 val = LTC4282_VIN_12V; 1389 break; 1390 case 24000000: 1391 val = LTC4282_VIN_24V; 1392 break; 1393 default: 1394 return dev_err_probe(dev, -EINVAL, 1395 "Invalid val(%u) for vin-mode-microvolt\n", 1396 val); 1397 } 1398 1399 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1400 LTC4282_CTRL_VIN_MODE_MASK, 1401 FIELD_PREP(LTC4282_CTRL_VIN_MODE_MASK, val)); 1402 if (ret) 1403 return ret; 1404 1405 /* Foldback mode should also be set to the input voltage */ 1406 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 1407 LTC4282_FOLDBACK_MODE_MASK, 1408 FIELD_PREP(LTC4282_FOLDBACK_MODE_MASK, val)); 1409 if (ret) 1410 return ret; 1411 } 1412 1413 st->vfs_out = ltc4282_vfs_milli[val]; 1414 st->vdd = ltc4282_vdd_milli[val]; 1415 1416 ret = device_property_read_u32(dev, "adi,current-limit-sense-microvolt", 1417 &st->vsense_max); 1418 if (!ret) { 1419 int reg_val; 1420 1421 switch (val) { 1422 case 12500: 1423 reg_val = 0; 1424 break; 1425 case 15625: 1426 reg_val = 1; 1427 break; 1428 case 18750: 1429 reg_val = 2; 1430 break; 1431 case 21875: 1432 reg_val = 3; 1433 break; 1434 case 25000: 1435 reg_val = 4; 1436 break; 1437 case 28125: 1438 reg_val = 5; 1439 break; 1440 case 31250: 1441 reg_val = 6; 1442 break; 1443 case 34375: 1444 reg_val = 7; 1445 break; 1446 default: 1447 return dev_err_probe(dev, -EINVAL, 1448 "Invalid val(%u) for adi,current-limit-microvolt\n", 1449 st->vsense_max); 1450 } 1451 1452 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 1453 LTC4282_ILIM_ADJUST_MASK, 1454 FIELD_PREP(LTC4282_ILIM_ADJUST_MASK, reg_val)); 1455 if (ret) 1456 return ret; 1457 } 1458 1459 ret = ltc4282_set_max_limits(st); 1460 if (ret) 1461 return ret; 1462 1463 ret = device_property_read_string(dev, "adi,overvoltage-dividers", 1464 ÷r); 1465 if (!ret) { 1466 int div = match_string(ltc4282_dividers, 1467 ARRAY_SIZE(ltc4282_dividers), divider); 1468 if (div < 0) 1469 return dev_err_probe(dev, -EINVAL, 1470 "Invalid val(%s) for adi,overvoltage-divider\n", 1471 divider); 1472 1473 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1474 LTC4282_CTRL_OV_MODE_MASK, 1475 FIELD_PREP(LTC4282_CTRL_OV_MODE_MASK, div)); 1476 } 1477 1478 ret = device_property_read_string(dev, "adi,undervoltage-dividers", 1479 ÷r); 1480 if (!ret) { 1481 int div = match_string(ltc4282_dividers, 1482 ARRAY_SIZE(ltc4282_dividers), divider); 1483 if (div < 0) 1484 return dev_err_probe(dev, -EINVAL, 1485 "Invalid val(%s) for adi,undervoltage-divider\n", 1486 divider); 1487 1488 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1489 LTC4282_CTRL_UV_MODE_MASK, 1490 FIELD_PREP(LTC4282_CTRL_UV_MODE_MASK, div)); 1491 } 1492 1493 if (device_property_read_bool(dev, "adi,overcurrent-retry")) { 1494 ret = regmap_set_bits(st->map, LTC4282_CTRL_LSB, 1495 LTC4282_CTRL_OC_RETRY_MASK); 1496 if (ret) 1497 return ret; 1498 } 1499 1500 if (device_property_read_bool(dev, "adi,overvoltage-retry-disable")) { 1501 ret = regmap_clear_bits(st->map, LTC4282_CTRL_LSB, 1502 LTC4282_CTRL_OV_RETRY_MASK); 1503 if (ret) 1504 return ret; 1505 } 1506 1507 if (device_property_read_bool(dev, "adi,undervoltage-retry-disable")) { 1508 ret = regmap_clear_bits(st->map, LTC4282_CTRL_LSB, 1509 LTC4282_CTRL_UV_RETRY_MASK); 1510 if (ret) 1511 return ret; 1512 } 1513 1514 if (device_property_read_bool(dev, "adi,fault-log-enable")) { 1515 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, 1516 LTC4282_FAULT_LOG_EN_MASK); 1517 if (ret) 1518 return ret; 1519 } 1520 1521 if (device_property_read_bool(dev, "adi,fault-log-enable")) { 1522 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_FAULT_LOG_EN_MASK); 1523 if (ret) 1524 return ret; 1525 } 1526 1527 ret = device_property_read_u32(dev, "adi,fet-bad-timeout-ms", &val); 1528 if (!ret) { 1529 if (val > LTC4282_FET_BAD_MAX_TIMEOUT) 1530 return dev_err_probe(dev, -EINVAL, 1531 "Invalid value(%u) for adi,fet-bad-timeout-ms", 1532 val); 1533 1534 ret = regmap_write(st->map, LTC4282_FET_BAD_FAULT_TIMEOUT, val); 1535 if (ret) 1536 return ret; 1537 } 1538 1539 return ltc4282_gpio_setup(st, dev); 1540 } 1541 1542 static bool ltc4282_readable_reg(struct device *dev, unsigned int reg) 1543 { 1544 if (reg == LTC4282_RESERVED_1 || reg == LTC4282_RESERVED_2) 1545 return false; 1546 1547 return true; 1548 } 1549 1550 static bool ltc4282_writable_reg(struct device *dev, unsigned int reg) 1551 { 1552 if (reg == LTC4282_STATUS_LSB || reg == LTC4282_STATUS_MSB) 1553 return false; 1554 if (reg == LTC4282_RESERVED_1 || reg == LTC4282_RESERVED_2) 1555 return false; 1556 1557 return true; 1558 } 1559 1560 static const struct regmap_config ltc4282_regmap_config = { 1561 .reg_bits = 8, 1562 .val_bits = 8, 1563 .max_register = LTC4282_RESERVED_3, 1564 .readable_reg = ltc4282_readable_reg, 1565 .writeable_reg = ltc4282_writable_reg, 1566 }; 1567 1568 static const struct hwmon_channel_info * const ltc4282_info[] = { 1569 HWMON_CHANNEL_INFO(in, 1570 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1571 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1572 HWMON_I_MAX_ALARM | HWMON_I_ENABLE | 1573 HWMON_I_RESET_HISTORY | HWMON_I_FAULT | 1574 HWMON_I_LABEL, 1575 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1576 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1577 HWMON_I_MAX_ALARM | HWMON_I_LCRIT_ALARM | 1578 HWMON_I_CRIT_ALARM | HWMON_I_ENABLE | 1579 HWMON_I_RESET_HISTORY | HWMON_I_LABEL, 1580 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1581 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1582 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1583 HWMON_I_LABEL), 1584 HWMON_CHANNEL_INFO(curr, 1585 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | 1586 HWMON_C_MAX | HWMON_C_MIN | HWMON_C_MIN_ALARM | 1587 HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM | 1588 HWMON_C_RESET_HISTORY | HWMON_C_LABEL), 1589 HWMON_CHANNEL_INFO(power, 1590 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | 1591 HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN | 1592 HWMON_P_MAX_ALARM | HWMON_P_MIN_ALARM | 1593 HWMON_P_RESET_HISTORY | HWMON_P_LABEL), 1594 HWMON_CHANNEL_INFO(energy, 1595 HWMON_E_ENABLE), 1596 NULL 1597 }; 1598 1599 static const struct hwmon_ops ltc4282_hwmon_ops = { 1600 .read = ltc4282_read, 1601 .write = ltc4282_write, 1602 .is_visible = ltc4282_is_visible, 1603 .read_string = ltc4282_read_labels, 1604 }; 1605 1606 static const struct hwmon_chip_info ltc2947_chip_info = { 1607 .ops = <c4282_hwmon_ops, 1608 .info = ltc4282_info, 1609 }; 1610 1611 /* energy attributes are 6bytes wide so we need u64 */ 1612 static SENSOR_DEVICE_ATTR_RO(energy1_input, ltc4282_energy, 0); 1613 1614 static struct attribute *ltc4282_attrs[] = { 1615 &sensor_dev_attr_energy1_input.dev_attr.attr, 1616 NULL 1617 }; 1618 ATTRIBUTE_GROUPS(ltc4282); 1619 1620 static int ltc4282_show_fault_log(void *arg, u64 *val, u32 mask) 1621 { 1622 struct ltc4282_state *st = arg; 1623 long alarm; 1624 int ret; 1625 1626 ret = ltc4282_read_alarm(st, LTC4282_FAULT_LOG, mask, &alarm); 1627 if (ret) 1628 return ret; 1629 1630 *val = alarm; 1631 1632 return 0; 1633 } 1634 1635 static int ltc4282_show_curr1_crit_fault_log(void *arg, u64 *val) 1636 { 1637 return ltc4282_show_fault_log(arg, val, LTC4282_OC_FAULT_MASK); 1638 } 1639 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_curr1_crit_fault_log, 1640 ltc4282_show_curr1_crit_fault_log, NULL, "%llu\n"); 1641 1642 static int ltc4282_show_in1_lcrit_fault_log(void *arg, u64 *val) 1643 { 1644 return ltc4282_show_fault_log(arg, val, LTC4282_UV_FAULT_MASK); 1645 } 1646 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_in1_lcrit_fault_log, 1647 ltc4282_show_in1_lcrit_fault_log, NULL, "%llu\n"); 1648 1649 static int ltc4282_show_in1_crit_fault_log(void *arg, u64 *val) 1650 { 1651 return ltc4282_show_fault_log(arg, val, LTC4282_OV_FAULT_MASK); 1652 } 1653 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_in1_crit_fault_log, 1654 ltc4282_show_in1_crit_fault_log, NULL, "%llu\n"); 1655 1656 static int ltc4282_show_fet_bad_fault_log(void *arg, u64 *val) 1657 { 1658 return ltc4282_show_fault_log(arg, val, LTC4282_FET_BAD_FAULT_MASK); 1659 } 1660 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_fet_bad_fault_log, 1661 ltc4282_show_fet_bad_fault_log, NULL, "%llu\n"); 1662 1663 static int ltc4282_show_fet_short_fault_log(void *arg, u64 *val) 1664 { 1665 return ltc4282_show_fault_log(arg, val, LTC4282_FET_SHORT_FAULT_MASK); 1666 } 1667 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_fet_short_fault_log, 1668 ltc4282_show_fet_short_fault_log, NULL, "%llu\n"); 1669 1670 static int ltc4282_show_power1_bad_fault_log(void *arg, u64 *val) 1671 { 1672 return ltc4282_show_fault_log(arg, val, LTC4282_POWER_BAD_FAULT_MASK); 1673 } 1674 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_power1_bad_fault_log, 1675 ltc4282_show_power1_bad_fault_log, NULL, "%llu\n"); 1676 1677 static void ltc4282_debugfs_remove(void *dir) 1678 { 1679 debugfs_remove_recursive(dir); 1680 } 1681 1682 static void ltc4282_debugfs_init(struct ltc4282_state *st, 1683 struct i2c_client *i2c, 1684 const struct device *hwmon) 1685 { 1686 const char *debugfs_name; 1687 struct dentry *dentry; 1688 int ret; 1689 1690 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 1691 return; 1692 1693 debugfs_name = devm_kasprintf(&i2c->dev, GFP_KERNEL, "ltc4282-%s", 1694 dev_name(hwmon)); 1695 if (!debugfs_name) 1696 return; 1697 1698 dentry = debugfs_create_dir(debugfs_name, NULL); 1699 if (IS_ERR(dentry)) 1700 return; 1701 1702 ret = devm_add_action_or_reset(&i2c->dev, ltc4282_debugfs_remove, 1703 dentry); 1704 if (ret) 1705 return; 1706 1707 debugfs_create_file_unsafe("power1_bad_fault_log", 0400, dentry, st, 1708 <c4282_power1_bad_fault_log); 1709 debugfs_create_file_unsafe("in0_fet_short_fault_log", 0400, dentry, st, 1710 <c4282_fet_short_fault_log); 1711 debugfs_create_file_unsafe("in0_fet_bad_fault_log", 0400, dentry, st, 1712 <c4282_fet_bad_fault_log); 1713 debugfs_create_file_unsafe("in1_crit_fault_log", 0400, dentry, st, 1714 <c4282_in1_crit_fault_log); 1715 debugfs_create_file_unsafe("in1_lcrit_fault_log", 0400, dentry, st, 1716 <c4282_in1_lcrit_fault_log); 1717 debugfs_create_file_unsafe("curr1_crit_fault_log", 0400, dentry, st, 1718 <c4282_curr1_crit_fault_log); 1719 } 1720 1721 static int ltc4282_probe(struct i2c_client *i2c) 1722 { 1723 struct device *dev = &i2c->dev, *hwmon; 1724 struct ltc4282_state *st; 1725 int ret; 1726 1727 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 1728 if (!st) 1729 return dev_err_probe(dev, -ENOMEM, 1730 "Failed to allocate memory\n"); 1731 1732 st->map = devm_regmap_init_i2c(i2c, <c4282_regmap_config); 1733 if (IS_ERR(st->map)) 1734 return dev_err_probe(dev, PTR_ERR(st->map), 1735 "failed regmap init\n"); 1736 1737 /* Soft reset */ 1738 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_RESET_MASK); 1739 if (ret) 1740 return ret; 1741 1742 /* Yes, it's big but it is as specified in the datasheet */ 1743 msleep(3200); 1744 1745 ret = ltc428_clks_setup(st, dev); 1746 if (ret) 1747 return ret; 1748 1749 ret = ltc4282_setup(st, dev); 1750 if (ret) 1751 return ret; 1752 1753 mutex_init(&st->lock); 1754 hwmon = devm_hwmon_device_register_with_info(dev, "ltc4282", st, 1755 <c2947_chip_info, 1756 ltc4282_groups); 1757 if (IS_ERR(hwmon)) 1758 return PTR_ERR(hwmon); 1759 1760 ltc4282_debugfs_init(st, i2c, hwmon); 1761 1762 return 0; 1763 } 1764 1765 static const struct of_device_id ltc4282_of_match[] = { 1766 { .compatible = "adi,ltc4282" }, 1767 {} 1768 }; 1769 MODULE_DEVICE_TABLE(of, ltc4282_of_match); 1770 1771 static struct i2c_driver ltc4282_driver = { 1772 .driver = { 1773 .name = "ltc4282", 1774 .of_match_table = ltc4282_of_match, 1775 }, 1776 .probe = ltc4282_probe, 1777 }; 1778 module_i2c_driver(ltc4282_driver); 1779 1780 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1781 MODULE_DESCRIPTION("LTC4282 I2C High Current Hot Swap Controller"); 1782 MODULE_LICENSE("GPL"); 1783