1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C 4 * 5 * Copyright 2023 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/cleanup.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/hwmon.h> 15 #include <linux/i2c.h> 16 #include <linux/math.h> 17 #include <linux/math64.h> 18 #include <linux/minmax.h> 19 #include <linux/module.h> 20 #include <linux/regmap.h> 21 #include <linux/property.h> 22 #include <linux/string.h> 23 #include <linux/units.h> 24 #include <linux/util_macros.h> 25 26 #define LTC4282_CTRL_LSB 0x00 27 #define LTC4282_CTRL_OV_RETRY_MASK BIT(0) 28 #define LTC4282_CTRL_UV_RETRY_MASK BIT(1) 29 #define LTC4282_CTRL_OC_RETRY_MASK BIT(2) 30 #define LTC4282_CTRL_ON_ACTIVE_LOW_MASK BIT(5) 31 #define LTC4282_CTRL_ON_DELAY_MASK BIT(6) 32 #define LTC4282_CTRL_MSB 0x01 33 #define LTC4282_CTRL_VIN_MODE_MASK GENMASK(1, 0) 34 #define LTC4282_CTRL_OV_MODE_MASK GENMASK(3, 2) 35 #define LTC4282_CTRL_UV_MODE_MASK GENMASK(5, 4) 36 #define LTC4282_FAULT_LOG 0x04 37 #define LTC4282_OV_FAULT_MASK BIT(0) 38 #define LTC4282_UV_FAULT_MASK BIT(1) 39 #define LTC4282_VDD_FAULT_MASK \ 40 (LTC4282_OV_FAULT_MASK | LTC4282_UV_FAULT_MASK) 41 #define LTC4282_OC_FAULT_MASK BIT(2) 42 #define LTC4282_POWER_BAD_FAULT_MASK BIT(3) 43 #define LTC4282_FET_SHORT_FAULT_MASK BIT(5) 44 #define LTC4282_FET_BAD_FAULT_MASK BIT(6) 45 #define LTC4282_FET_FAILURE_FAULT_MASK \ 46 (LTC4282_FET_SHORT_FAULT_MASK | LTC4282_FET_BAD_FAULT_MASK) 47 #define LTC4282_ADC_ALERT_LOG 0x05 48 #define LTC4282_GPIO_ALARM_L_MASK BIT(0) 49 #define LTC4282_GPIO_ALARM_H_MASK BIT(1) 50 #define LTC4282_VSOURCE_ALARM_L_MASK BIT(2) 51 #define LTC4282_VSOURCE_ALARM_H_MASK BIT(3) 52 #define LTC4282_VSENSE_ALARM_L_MASK BIT(4) 53 #define LTC4282_VSENSE_ALARM_H_MASK BIT(5) 54 #define LTC4282_POWER_ALARM_L_MASK BIT(6) 55 #define LTC4282_POWER_ALARM_H_MASK BIT(7) 56 #define LTC4282_FET_BAD_FAULT_TIMEOUT 0x06 57 #define LTC4282_FET_BAD_MAX_TIMEOUT 255 58 #define LTC4282_GPIO_CONFIG 0x07 59 #define LTC4282_GPIO_2_FET_STRESS_MASK BIT(1) 60 #define LTC4282_GPIO_1_CONFIG_MASK GENMASK(5, 4) 61 #define LTC4282_VGPIO_MIN 0x08 62 #define LTC4282_VGPIO_MAX 0x09 63 #define LTC4282_VSOURCE_MIN 0x0a 64 #define LTC4282_VSOURCE_MAX 0x0b 65 #define LTC4282_VSENSE_MIN 0x0c 66 #define LTC4282_VSENSE_MAX 0x0d 67 #define LTC4282_POWER_MIN 0x0e 68 #define LTC4282_POWER_MAX 0x0f 69 #define LTC4282_CLK_DIV 0x10 70 #define LTC4282_CLK_DIV_MASK GENMASK(4, 0) 71 #define LTC4282_CLKOUT_MASK GENMASK(6, 5) 72 #define LTC4282_ILIM_ADJUST 0x11 73 #define LTC4282_GPIO_MODE_MASK BIT(1) 74 #define LTC4282_VDD_MONITOR_MASK BIT(2) 75 #define LTC4282_FOLDBACK_MODE_MASK GENMASK(4, 3) 76 #define LTC4282_ILIM_ADJUST_MASK GENMASK(7, 5) 77 #define LTC4282_ENERGY 0x12 78 #define LTC4282_TIME_COUNTER 0x18 79 #define LTC4282_ALERT_CTRL 0x1c 80 #define LTC4282_ALERT_OUT_MASK BIT(6) 81 #define LTC4282_ADC_CTRL 0x1d 82 #define LTC4282_FAULT_LOG_EN_MASK BIT(2) 83 #define LTC4282_METER_HALT_MASK BIT(5) 84 #define LTC4282_METER_RESET_MASK BIT(6) 85 #define LTC4282_RESET_MASK BIT(7) 86 #define LTC4282_STATUS_LSB 0x1e 87 #define LTC4282_OV_STATUS_MASK BIT(0) 88 #define LTC4282_UV_STATUS_MASK BIT(1) 89 #define LTC4282_VDD_STATUS_MASK \ 90 (LTC4282_OV_STATUS_MASK | LTC4282_UV_STATUS_MASK) 91 #define LTC4282_OC_STATUS_MASK BIT(2) 92 #define LTC4282_POWER_GOOD_MASK BIT(3) 93 #define LTC4282_FET_FAILURE_MASK GENMASK(6, 5) 94 #define LTC4282_STATUS_MSB 0x1f 95 #define LTC4282_RESERVED_1 0x32 96 #define LTC4282_RESERVED_2 0x33 97 #define LTC4282_VGPIO 0x34 98 #define LTC4282_VGPIO_LOWEST 0x36 99 #define LTC4282_VGPIO_HIGHEST 0x38 100 #define LTC4282_VSOURCE 0x3a 101 #define LTC4282_VSOURCE_LOWEST 0x3c 102 #define LTC4282_VSOURCE_HIGHEST 0x3e 103 #define LTC4282_VSENSE 0x40 104 #define LTC4282_VSENSE_LOWEST 0x42 105 #define LTC4282_VSENSE_HIGHEST 0x44 106 #define LTC4282_POWER 0x46 107 #define LTC4282_POWER_LOWEST 0x48 108 #define LTC4282_POWER_HIGHEST 0x4a 109 #define LTC4282_RESERVED_3 0x50 110 111 #define LTC4282_CLKIN_MIN (250 * KILO) 112 #define LTC4282_CLKIN_MAX (15500 * KILO) 113 #define LTC4282_CLKIN_RANGE (LTC4282_CLKIN_MAX - LTC4282_CLKIN_MIN + 1) 114 #define LTC4282_CLKOUT_SYSTEM (250 * KILO) 115 #define LTC4282_CLKOUT_CNV 15 116 117 enum { 118 LTC4282_CHAN_VSOURCE, 119 LTC4282_CHAN_VDD, 120 LTC4282_CHAN_VGPIO, 121 }; 122 123 struct ltc4282_cache { 124 u32 in_max_raw; 125 u32 in_min_raw; 126 long in_highest; 127 long in_lowest; 128 bool en; 129 }; 130 131 struct ltc4282_state { 132 struct regmap *map; 133 struct clk_hw clk_hw; 134 /* 135 * Used to cache values for VDD/VSOURCE depending which will be used 136 * when hwmon is not enabled for that channel. Needed because they share 137 * the same registers. 138 */ 139 struct ltc4282_cache in0_1_cache[LTC4282_CHAN_VGPIO]; 140 u32 vsense_max; 141 s64 power_max; 142 u32 rsense; 143 u16 vdd; 144 u16 vfs_out; 145 bool energy_en; 146 }; 147 148 enum { 149 LTC4282_CLKOUT_NONE, 150 LTC4282_CLKOUT_INT, 151 LTC4282_CLKOUT_TICK, 152 }; 153 154 static int ltc4282_set_rate(struct clk_hw *hw, 155 unsigned long rate, unsigned long parent_rate) 156 { 157 struct ltc4282_state *st = container_of(hw, struct ltc4282_state, 158 clk_hw); 159 u32 val = LTC4282_CLKOUT_INT; 160 161 if (rate == LTC4282_CLKOUT_CNV) 162 val = LTC4282_CLKOUT_TICK; 163 164 return regmap_update_bits(st->map, LTC4282_CLK_DIV, LTC4282_CLKOUT_MASK, 165 FIELD_PREP(LTC4282_CLKOUT_MASK, val)); 166 } 167 168 /* 169 * Note the 15HZ conversion rate assumes 12bit ADC which is what we are 170 * supporting for now. 171 */ 172 static const unsigned int ltc4282_out_rates[] = { 173 LTC4282_CLKOUT_CNV, LTC4282_CLKOUT_SYSTEM 174 }; 175 176 static int ltc4282_determine_rate(struct clk_hw *hw, 177 struct clk_rate_request *req) 178 { 179 int idx = find_closest(req->rate, ltc4282_out_rates, 180 ARRAY_SIZE(ltc4282_out_rates)); 181 182 req->rate = ltc4282_out_rates[idx]; 183 184 return 0; 185 } 186 187 static unsigned long ltc4282_recalc_rate(struct clk_hw *hw, 188 unsigned long parent) 189 { 190 struct ltc4282_state *st = container_of(hw, struct ltc4282_state, 191 clk_hw); 192 u32 clkdiv; 193 int ret; 194 195 ret = regmap_read(st->map, LTC4282_CLK_DIV, &clkdiv); 196 if (ret) 197 return 0; 198 199 clkdiv = FIELD_GET(LTC4282_CLKOUT_MASK, clkdiv); 200 if (!clkdiv) 201 return 0; 202 if (clkdiv == LTC4282_CLKOUT_INT) 203 return LTC4282_CLKOUT_SYSTEM; 204 205 return LTC4282_CLKOUT_CNV; 206 } 207 208 static void ltc4282_disable(struct clk_hw *clk_hw) 209 { 210 struct ltc4282_state *st = container_of(clk_hw, struct ltc4282_state, 211 clk_hw); 212 213 regmap_clear_bits(st->map, LTC4282_CLK_DIV, LTC4282_CLKOUT_MASK); 214 } 215 216 static int ltc4282_read_voltage_word(const struct ltc4282_state *st, u32 reg, 217 u32 fs, long *val) 218 { 219 __be16 in; 220 int ret; 221 222 ret = regmap_bulk_read(st->map, reg, &in, sizeof(in)); 223 if (ret) 224 return ret; 225 226 /* 227 * This is also used to calculate current in which case fs comes in 228 * 10 * uV. Hence the ULL usage. 229 */ 230 *val = DIV_ROUND_CLOSEST_ULL(be16_to_cpu(in) * (u64)fs, U16_MAX); 231 return 0; 232 } 233 234 static int ltc4282_read_voltage_byte_cached(const struct ltc4282_state *st, 235 u32 reg, u32 fs, long *val, 236 u32 *cached_raw) 237 { 238 int ret; 239 u32 in; 240 241 if (cached_raw) { 242 in = *cached_raw; 243 } else { 244 ret = regmap_read(st->map, reg, &in); 245 if (ret) 246 return ret; 247 } 248 249 *val = DIV_ROUND_CLOSEST(in * fs, U8_MAX); 250 return 0; 251 } 252 253 static int ltc4282_read_voltage_byte(const struct ltc4282_state *st, u32 reg, 254 u32 fs, long *val) 255 { 256 return ltc4282_read_voltage_byte_cached(st, reg, fs, val, NULL); 257 } 258 259 static int __ltc4282_read_alarm(struct ltc4282_state *st, u32 reg, u32 mask, 260 long *val) 261 { 262 u32 alarm; 263 int ret; 264 265 ret = regmap_read(st->map, reg, &alarm); 266 if (ret) 267 return ret; 268 269 *val = !!(alarm & mask); 270 271 /* if not status/fault logs, clear the alarm after reading it */ 272 if (reg != LTC4282_STATUS_LSB && reg != LTC4282_FAULT_LOG) 273 return regmap_clear_bits(st->map, reg, mask); 274 275 return 0; 276 } 277 278 static int ltc4282_read_alarm(struct ltc4282_state *st, u32 reg, u32 mask, 279 long *val) 280 { 281 return __ltc4282_read_alarm(st, reg, mask, val); 282 } 283 284 static int ltc4282_vdd_source_read_in(struct ltc4282_state *st, u32 channel, 285 long *val) 286 { 287 if (!st->in0_1_cache[channel].en) 288 return -ENODATA; 289 290 return ltc4282_read_voltage_word(st, LTC4282_VSOURCE, st->vfs_out, val); 291 } 292 293 static int ltc4282_vdd_source_read_hist(struct ltc4282_state *st, u32 reg, 294 u32 channel, long *cached, long *val) 295 { 296 int ret; 297 298 if (!st->in0_1_cache[channel].en) { 299 *val = *cached; 300 return 0; 301 } 302 303 ret = ltc4282_read_voltage_word(st, reg, st->vfs_out, val); 304 if (ret) 305 return ret; 306 307 *cached = *val; 308 return 0; 309 } 310 311 static int ltc4282_vdd_source_read_lim(struct ltc4282_state *st, u32 reg, 312 u32 channel, u32 *cached, long *val) 313 { 314 if (!st->in0_1_cache[channel].en) 315 return ltc4282_read_voltage_byte_cached(st, reg, st->vfs_out, 316 val, cached); 317 318 return ltc4282_read_voltage_byte(st, reg, st->vfs_out, val); 319 } 320 321 static int ltc4282_vdd_source_read_alm(struct ltc4282_state *st, u32 mask, 322 u32 channel, long *val) 323 { 324 if (!st->in0_1_cache[channel].en) { 325 /* 326 * Do this otherwise alarms can get confused because we clear 327 * them after reading them. So, if someone mistakenly reads 328 * VSOURCE right before VDD (or the other way around), we might 329 * get no alarm just because it was cleared when reading VSOURCE 330 * and had no time for a new conversion and thus having the 331 * alarm again. 332 */ 333 *val = 0; 334 return 0; 335 } 336 337 return __ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, mask, val); 338 } 339 340 static int ltc4282_read_in(struct ltc4282_state *st, u32 attr, long *val, 341 u32 channel) 342 { 343 switch (attr) { 344 case hwmon_in_input: 345 if (channel == LTC4282_CHAN_VGPIO) 346 return ltc4282_read_voltage_word(st, LTC4282_VGPIO, 347 1280, val); 348 349 return ltc4282_vdd_source_read_in(st, channel, val); 350 case hwmon_in_highest: 351 if (channel == LTC4282_CHAN_VGPIO) 352 return ltc4282_read_voltage_word(st, 353 LTC4282_VGPIO_HIGHEST, 354 1280, val); 355 356 return ltc4282_vdd_source_read_hist(st, LTC4282_VSOURCE_HIGHEST, 357 channel, 358 &st->in0_1_cache[channel].in_highest, val); 359 case hwmon_in_lowest: 360 if (channel == LTC4282_CHAN_VGPIO) 361 return ltc4282_read_voltage_word(st, LTC4282_VGPIO_LOWEST, 362 1280, val); 363 364 return ltc4282_vdd_source_read_hist(st, LTC4282_VSOURCE_LOWEST, 365 channel, 366 &st->in0_1_cache[channel].in_lowest, val); 367 case hwmon_in_max_alarm: 368 if (channel == LTC4282_CHAN_VGPIO) 369 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 370 LTC4282_GPIO_ALARM_H_MASK, 371 val); 372 373 return ltc4282_vdd_source_read_alm(st, 374 LTC4282_VSOURCE_ALARM_H_MASK, 375 channel, val); 376 case hwmon_in_min_alarm: 377 if (channel == LTC4282_CHAN_VGPIO) 378 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 379 LTC4282_GPIO_ALARM_L_MASK, val); 380 381 return ltc4282_vdd_source_read_alm(st, 382 LTC4282_VSOURCE_ALARM_L_MASK, 383 channel, val); 384 case hwmon_in_crit_alarm: 385 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 386 LTC4282_OV_STATUS_MASK, val); 387 case hwmon_in_lcrit_alarm: 388 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 389 LTC4282_UV_STATUS_MASK, val); 390 case hwmon_in_max: 391 if (channel == LTC4282_CHAN_VGPIO) 392 return ltc4282_read_voltage_byte(st, LTC4282_VGPIO_MAX, 393 1280, val); 394 395 return ltc4282_vdd_source_read_lim(st, LTC4282_VSOURCE_MAX, 396 channel, 397 &st->in0_1_cache[channel].in_max_raw, val); 398 case hwmon_in_min: 399 if (channel == LTC4282_CHAN_VGPIO) 400 return ltc4282_read_voltage_byte(st, LTC4282_VGPIO_MIN, 401 1280, val); 402 403 return ltc4282_vdd_source_read_lim(st, LTC4282_VSOURCE_MIN, 404 channel, 405 &st->in0_1_cache[channel].in_min_raw, val); 406 case hwmon_in_enable: 407 *val = st->in0_1_cache[channel].en; 408 return 0; 409 case hwmon_in_fault: 410 /* 411 * We report failure if we detect either a fer_bad or a 412 * fet_short in the status register. 413 */ 414 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 415 LTC4282_FET_FAILURE_MASK, val); 416 default: 417 return -EOPNOTSUPP; 418 } 419 } 420 421 static int ltc4282_read_current_word(const struct ltc4282_state *st, u32 reg, 422 long *val) 423 { 424 long in; 425 int ret; 426 427 /* 428 * We pass in full scale in 10 * micro (note that 40 is already 429 * millivolt) so we have better approximations to calculate current. 430 */ 431 ret = ltc4282_read_voltage_word(st, reg, DECA * 40 * MILLI, &in); 432 if (ret) 433 return ret; 434 435 *val = DIV_ROUND_CLOSEST(in * MILLI, st->rsense); 436 437 return 0; 438 } 439 440 static int ltc4282_read_current_byte(const struct ltc4282_state *st, u32 reg, 441 long *val) 442 { 443 long in; 444 int ret; 445 446 ret = ltc4282_read_voltage_byte(st, reg, DECA * 40 * MILLI, &in); 447 if (ret) 448 return ret; 449 450 *val = DIV_ROUND_CLOSEST(in * MILLI, st->rsense); 451 452 return 0; 453 } 454 455 static int ltc4282_read_curr(struct ltc4282_state *st, const u32 attr, 456 long *val) 457 { 458 switch (attr) { 459 case hwmon_curr_input: 460 return ltc4282_read_current_word(st, LTC4282_VSENSE, val); 461 case hwmon_curr_highest: 462 return ltc4282_read_current_word(st, LTC4282_VSENSE_HIGHEST, 463 val); 464 case hwmon_curr_lowest: 465 return ltc4282_read_current_word(st, LTC4282_VSENSE_LOWEST, 466 val); 467 case hwmon_curr_max: 468 return ltc4282_read_current_byte(st, LTC4282_VSENSE_MAX, val); 469 case hwmon_curr_min: 470 return ltc4282_read_current_byte(st, LTC4282_VSENSE_MIN, val); 471 case hwmon_curr_max_alarm: 472 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 473 LTC4282_VSENSE_ALARM_H_MASK, val); 474 case hwmon_curr_min_alarm: 475 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 476 LTC4282_VSENSE_ALARM_L_MASK, val); 477 case hwmon_curr_crit_alarm: 478 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 479 LTC4282_OC_STATUS_MASK, val); 480 default: 481 return -EOPNOTSUPP; 482 } 483 } 484 485 static int ltc4282_read_power_word(const struct ltc4282_state *st, u32 reg, 486 long *val) 487 { 488 u64 temp = DECA * 40ULL * st->vfs_out * BIT(16), temp_2; 489 __be16 raw; 490 u16 power; 491 int ret; 492 493 ret = regmap_bulk_read(st->map, reg, &raw, sizeof(raw)); 494 if (ret) 495 return ret; 496 497 power = be16_to_cpu(raw); 498 /* 499 * Power is given by: 500 * P = CODE(16b) * 0.040 * Vfs(out) * 2^16 / ((2^16 - 1)^2 * Rsense) 501 */ 502 if (check_mul_overflow(power * temp, MICRO, &temp_2)) { 503 temp = DIV_ROUND_CLOSEST_ULL(power * temp, U16_MAX); 504 *val = DIV64_U64_ROUND_CLOSEST(temp * MICRO, 505 U16_MAX * (u64)st->rsense); 506 return 0; 507 } 508 509 *val = DIV64_U64_ROUND_CLOSEST(temp_2, 510 st->rsense * int_pow(U16_MAX, 2)); 511 512 return 0; 513 } 514 515 static int ltc4282_read_power_byte(const struct ltc4282_state *st, u32 reg, 516 long *val) 517 { 518 u32 power; 519 u64 temp; 520 int ret; 521 522 ret = regmap_read(st->map, reg, &power); 523 if (ret) 524 return ret; 525 526 temp = power * 40 * DECA * st->vfs_out * BIT_ULL(8); 527 *val = DIV64_U64_ROUND_CLOSEST(temp * MICRO, 528 int_pow(U8_MAX, 2) * st->rsense); 529 530 return 0; 531 } 532 533 static int ltc4282_read_energy(const struct ltc4282_state *st, s64 *val) 534 { 535 u64 temp, energy; 536 __be64 raw; 537 int ret; 538 539 ret = regmap_bulk_read(st->map, LTC4282_ENERGY, &raw, 6); 540 if (ret) 541 return ret; 542 543 energy = be64_to_cpu(raw) >> 16; 544 /* 545 * The formula for energy is given by: 546 * E = CODE(48b) * 0.040 * Vfs(out) * Tconv * 256 / 547 * ((2^16 - 1)^2 * Rsense) 548 * 549 * Since we only support 12bit ADC, Tconv = 0.065535s. Passing Vfs(out) 550 * and 0.040 to mV and Tconv to us, we can simplify the formula to: 551 * E = CODE(48b) * 40 * Vfs(out) * 256 / (U16_MAX * Rsense) 552 * 553 * As Rsense can have tenths of micro-ohm resolution, we need to 554 * multiply by DECA to get microujoule. 555 */ 556 if (check_mul_overflow(DECA * st->vfs_out * 40 * BIT(8), energy, &temp)) { 557 temp = DIV_ROUND_CLOSEST(DECA * st->vfs_out * 40 * BIT(8), U16_MAX); 558 *val = DIV_ROUND_CLOSEST_ULL(temp * energy, st->rsense); 559 return 0; 560 } 561 562 *val = DIV64_U64_ROUND_CLOSEST(temp, U16_MAX * (u64)st->rsense); 563 564 return 0; 565 } 566 567 static int ltc4282_read_power(struct ltc4282_state *st, const u32 attr, 568 long *val) 569 { 570 switch (attr) { 571 case hwmon_power_input: 572 return ltc4282_read_power_word(st, LTC4282_POWER, val); 573 case hwmon_power_input_highest: 574 return ltc4282_read_power_word(st, LTC4282_POWER_HIGHEST, val); 575 case hwmon_power_input_lowest: 576 return ltc4282_read_power_word(st, LTC4282_POWER_LOWEST, val); 577 case hwmon_power_max_alarm: 578 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 579 LTC4282_POWER_ALARM_H_MASK, val); 580 case hwmon_power_min_alarm: 581 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 582 LTC4282_POWER_ALARM_L_MASK, val); 583 case hwmon_power_max: 584 return ltc4282_read_power_byte(st, LTC4282_POWER_MAX, val); 585 case hwmon_power_min: 586 return ltc4282_read_power_byte(st, LTC4282_POWER_MIN, val); 587 default: 588 return -EOPNOTSUPP; 589 } 590 } 591 592 static int ltc4282_read(struct device *dev, enum hwmon_sensor_types type, 593 u32 attr, int channel, long *val) 594 { 595 struct ltc4282_state *st = dev_get_drvdata(dev); 596 597 switch (type) { 598 case hwmon_in: 599 return ltc4282_read_in(st, attr, val, channel); 600 case hwmon_curr: 601 return ltc4282_read_curr(st, attr, val); 602 case hwmon_power: 603 return ltc4282_read_power(st, attr, val); 604 case hwmon_energy: 605 *val = st->energy_en; 606 return 0; 607 case hwmon_energy64: 608 if (st->energy_en) 609 return ltc4282_read_energy(st, (s64 *)val); 610 return -ENODATA; 611 default: 612 return -EOPNOTSUPP; 613 } 614 } 615 616 static int ltc4282_write_power_byte(const struct ltc4282_state *st, u32 reg, 617 s64 val) 618 { 619 u32 power; 620 u64 temp; 621 622 val = clamp(val, 0, st->power_max); 623 624 temp = val * int_pow(U8_MAX, 2) * st->rsense; 625 power = DIV64_U64_ROUND_CLOSEST(temp, 626 MICRO * DECA * 256ULL * st->vfs_out * 40); 627 628 return regmap_write(st->map, reg, power); 629 } 630 631 static int ltc4282_write_power_word(const struct ltc4282_state *st, u32 reg, 632 u64 val) 633 { 634 u64 temp = int_pow(U16_MAX, 2) * st->rsense, temp_2; 635 __be16 __raw; 636 u16 code; 637 638 if (check_mul_overflow(temp, val, &temp_2)) { 639 temp = DIV_ROUND_CLOSEST_ULL(temp, DECA * MICRO); 640 code = DIV64_U64_ROUND_CLOSEST(temp * val, 641 40ULL * BIT(16) * st->vfs_out); 642 } else { 643 temp = DECA * MICRO * 40ULL * BIT(16) * st->vfs_out; 644 code = DIV64_U64_ROUND_CLOSEST(temp_2, temp); 645 } 646 647 __raw = cpu_to_be16(code); 648 return regmap_bulk_write(st->map, reg, &__raw, sizeof(__raw)); 649 } 650 651 static int __ltc4282_in_write_history(const struct ltc4282_state *st, u32 reg, 652 long lowest, long highest, u32 fs) 653 { 654 __be16 __raw; 655 u16 tmp; 656 int ret; 657 658 tmp = DIV_ROUND_CLOSEST(U16_MAX * lowest, fs); 659 660 __raw = cpu_to_be16(tmp); 661 662 ret = regmap_bulk_write(st->map, reg, &__raw, 2); 663 if (ret) 664 return ret; 665 666 tmp = DIV_ROUND_CLOSEST(U16_MAX * highest, fs); 667 668 __raw = cpu_to_be16(tmp); 669 670 return regmap_bulk_write(st->map, reg + 2, &__raw, 2); 671 } 672 673 static int ltc4282_in_write_history(struct ltc4282_state *st, u32 reg, 674 long lowest, long highest, u32 fs) 675 { 676 return __ltc4282_in_write_history(st, reg, lowest, highest, fs); 677 } 678 679 static int ltc4282_power_reset_hist(struct ltc4282_state *st) 680 { 681 int ret; 682 683 ret = ltc4282_write_power_word(st, LTC4282_POWER_LOWEST, 684 st->power_max); 685 if (ret) 686 return ret; 687 688 ret = ltc4282_write_power_word(st, LTC4282_POWER_HIGHEST, 0); 689 if (ret) 690 return ret; 691 692 /* now, let's also clear possible power_bad fault logs */ 693 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 694 LTC4282_POWER_BAD_FAULT_MASK); 695 } 696 697 static int ltc4282_write_power(struct ltc4282_state *st, u32 attr, 698 long val) 699 { 700 switch (attr) { 701 case hwmon_power_max: 702 return ltc4282_write_power_byte(st, LTC4282_POWER_MAX, val); 703 case hwmon_power_min: 704 return ltc4282_write_power_byte(st, LTC4282_POWER_MIN, val); 705 case hwmon_power_reset_history: 706 return ltc4282_power_reset_hist(st); 707 default: 708 return -EOPNOTSUPP; 709 } 710 } 711 712 static int ltc4282_write_voltage_byte_cached(const struct ltc4282_state *st, 713 u32 reg, u32 fs, long val, 714 u32 *cache_raw) 715 { 716 u32 in; 717 718 val = clamp_val(val, 0, fs); 719 in = DIV_ROUND_CLOSEST(val * U8_MAX, fs); 720 721 if (cache_raw) { 722 *cache_raw = in; 723 return 0; 724 } 725 726 return regmap_write(st->map, reg, in); 727 } 728 729 static int ltc4282_write_voltage_byte(const struct ltc4282_state *st, u32 reg, 730 u32 fs, long val) 731 { 732 return ltc4282_write_voltage_byte_cached(st, reg, fs, val, NULL); 733 } 734 735 static int ltc4282_cache_history(struct ltc4282_state *st, u32 channel) 736 { 737 long val; 738 int ret; 739 740 ret = ltc4282_read_voltage_word(st, LTC4282_VSOURCE_LOWEST, st->vfs_out, 741 &val); 742 if (ret) 743 return ret; 744 745 st->in0_1_cache[channel].in_lowest = val; 746 747 ret = ltc4282_read_voltage_word(st, LTC4282_VSOURCE_HIGHEST, 748 st->vfs_out, &val); 749 if (ret) 750 return ret; 751 752 st->in0_1_cache[channel].in_highest = val; 753 754 ret = regmap_read(st->map, LTC4282_VSOURCE_MIN, 755 &st->in0_1_cache[channel].in_min_raw); 756 if (ret) 757 return ret; 758 759 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 760 &st->in0_1_cache[channel].in_max_raw); 761 } 762 763 static int ltc4282_cache_sync(struct ltc4282_state *st, u32 channel) 764 { 765 int ret; 766 767 ret = __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 768 st->in0_1_cache[channel].in_lowest, 769 st->in0_1_cache[channel].in_highest, 770 st->vfs_out); 771 if (ret) 772 return ret; 773 774 ret = regmap_write(st->map, LTC4282_VSOURCE_MIN, 775 st->in0_1_cache[channel].in_min_raw); 776 if (ret) 777 return ret; 778 779 return regmap_write(st->map, LTC4282_VSOURCE_MAX, 780 st->in0_1_cache[channel].in_max_raw); 781 } 782 783 static int ltc4282_vdd_source_write_lim(struct ltc4282_state *st, u32 reg, 784 int channel, u32 *cache, long val) 785 { 786 int ret; 787 788 if (st->in0_1_cache[channel].en) 789 ret = ltc4282_write_voltage_byte(st, reg, st->vfs_out, val); 790 else 791 ret = ltc4282_write_voltage_byte_cached(st, reg, st->vfs_out, 792 val, cache); 793 794 return ret; 795 } 796 797 static int ltc4282_vdd_source_reset_hist(struct ltc4282_state *st, int channel) 798 { 799 long lowest = st->vfs_out; 800 int ret; 801 802 if (channel == LTC4282_CHAN_VDD) 803 lowest = st->vdd; 804 805 if (st->in0_1_cache[channel].en) { 806 ret = __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 807 lowest, 0, st->vfs_out); 808 if (ret) 809 return ret; 810 } 811 812 st->in0_1_cache[channel].in_lowest = lowest; 813 st->in0_1_cache[channel].in_highest = 0; 814 815 /* 816 * We are also clearing possible fault logs in reset_history. Clearing 817 * the logs might be important when the auto retry bits are not enabled 818 * as the chip only enables the output again after having these logs 819 * cleared. As some of these logs are related to limits, it makes sense 820 * to clear them in here. For VDD, we need to clear under/over voltage 821 * events. For VSOURCE, fet_short and fet_bad... 822 */ 823 if (channel == LTC4282_CHAN_VSOURCE) 824 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 825 LTC4282_FET_FAILURE_FAULT_MASK); 826 827 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 828 LTC4282_VDD_FAULT_MASK); 829 } 830 831 /* 832 * We need to mux between VSOURCE and VDD which means they are mutually 833 * exclusive. Moreover, we can't really disable both VDD and VSOURCE as the ADC 834 * is continuously running (we cannot independently halt it without also 835 * stopping VGPIO). Hence, the logic is that disabling or enabling VDD will 836 * automatically have the reverse effect on VSOURCE and vice-versa. 837 */ 838 static int ltc4282_vdd_source_enable(struct ltc4282_state *st, int channel, 839 long val) 840 { 841 int ret, other_chan = ~channel & 0x1; 842 u8 __val = val; 843 844 if (st->in0_1_cache[channel].en == !!val) 845 return 0; 846 847 /* clearing the bit makes the ADC to monitor VDD */ 848 if (channel == LTC4282_CHAN_VDD) 849 __val = !__val; 850 851 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 852 LTC4282_VDD_MONITOR_MASK, 853 FIELD_PREP(LTC4282_VDD_MONITOR_MASK, !!__val)); 854 if (ret) 855 return ret; 856 857 st->in0_1_cache[channel].en = !!val; 858 st->in0_1_cache[other_chan].en = !val; 859 860 if (st->in0_1_cache[channel].en) { 861 /* 862 * Then, we are disabling @other_chan. Let's save it's current 863 * history. 864 */ 865 ret = ltc4282_cache_history(st, other_chan); 866 if (ret) 867 return ret; 868 869 return ltc4282_cache_sync(st, channel); 870 } 871 /* 872 * Then, we are enabling @other_chan. We need to do the opposite from 873 * above. 874 */ 875 ret = ltc4282_cache_history(st, channel); 876 if (ret) 877 return ret; 878 879 return ltc4282_cache_sync(st, other_chan); 880 } 881 882 static int ltc4282_write_in(struct ltc4282_state *st, u32 attr, long val, 883 int channel) 884 { 885 switch (attr) { 886 case hwmon_in_max: 887 if (channel == LTC4282_CHAN_VGPIO) 888 return ltc4282_write_voltage_byte(st, LTC4282_VGPIO_MAX, 889 1280, val); 890 891 return ltc4282_vdd_source_write_lim(st, LTC4282_VSOURCE_MAX, 892 channel, 893 &st->in0_1_cache[channel].in_max_raw, val); 894 case hwmon_in_min: 895 if (channel == LTC4282_CHAN_VGPIO) 896 return ltc4282_write_voltage_byte(st, LTC4282_VGPIO_MIN, 897 1280, val); 898 899 return ltc4282_vdd_source_write_lim(st, LTC4282_VSOURCE_MIN, 900 channel, 901 &st->in0_1_cache[channel].in_min_raw, val); 902 case hwmon_in_reset_history: 903 if (channel == LTC4282_CHAN_VGPIO) 904 return ltc4282_in_write_history(st, 905 LTC4282_VGPIO_LOWEST, 906 1280, 0, 1280); 907 908 return ltc4282_vdd_source_reset_hist(st, channel); 909 case hwmon_in_enable: 910 return ltc4282_vdd_source_enable(st, channel, val); 911 default: 912 return -EOPNOTSUPP; 913 } 914 } 915 916 static int ltc4282_curr_reset_hist(struct ltc4282_state *st) 917 { 918 int ret; 919 920 ret = __ltc4282_in_write_history(st, LTC4282_VSENSE_LOWEST, 921 st->vsense_max, 0, 40 * MILLI); 922 if (ret) 923 return ret; 924 925 /* now, let's also clear possible overcurrent fault logs */ 926 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 927 LTC4282_OC_FAULT_MASK); 928 } 929 930 static int ltc4282_write_curr(struct ltc4282_state *st, u32 attr, 931 long val) 932 { 933 s32 ulimit = min_t(u64, INT_MAX, 934 div_u64((u64)INT_MAX * DECA * MICRO, st->rsense)); 935 u64 val64 = clamp(val, 0, ulimit); 936 /* need to pass it in millivolt */ 937 u32 in = DIV_ROUND_CLOSEST_ULL(val64 * st->rsense, DECA * MICRO); 938 939 switch (attr) { 940 case hwmon_curr_max: 941 return ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MAX, 40, 942 in); 943 case hwmon_curr_min: 944 return ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MIN, 40, 945 in); 946 case hwmon_curr_reset_history: 947 return ltc4282_curr_reset_hist(st); 948 default: 949 return -EOPNOTSUPP; 950 } 951 } 952 953 static int ltc4282_energy_enable_set(struct ltc4282_state *st, long val) 954 { 955 int ret; 956 957 /* setting the bit halts the meter */ 958 ret = regmap_update_bits(st->map, LTC4282_ADC_CTRL, 959 LTC4282_METER_HALT_MASK, 960 FIELD_PREP(LTC4282_METER_HALT_MASK, !val)); 961 if (ret) 962 return ret; 963 964 st->energy_en = !!val; 965 966 return 0; 967 } 968 969 static int ltc4282_write(struct device *dev, 970 enum hwmon_sensor_types type, 971 u32 attr, int channel, long val) 972 { 973 struct ltc4282_state *st = dev_get_drvdata(dev); 974 975 switch (type) { 976 case hwmon_power: 977 return ltc4282_write_power(st, attr, val); 978 case hwmon_in: 979 return ltc4282_write_in(st, attr, val, channel); 980 case hwmon_curr: 981 return ltc4282_write_curr(st, attr, val); 982 case hwmon_energy: 983 return ltc4282_energy_enable_set(st, val); 984 default: 985 return -EOPNOTSUPP; 986 } 987 } 988 989 static umode_t ltc4282_in_is_visible(const struct ltc4282_state *st, u32 attr) 990 { 991 switch (attr) { 992 case hwmon_in_input: 993 case hwmon_in_highest: 994 case hwmon_in_lowest: 995 case hwmon_in_max_alarm: 996 case hwmon_in_min_alarm: 997 case hwmon_in_label: 998 case hwmon_in_lcrit_alarm: 999 case hwmon_in_crit_alarm: 1000 case hwmon_in_fault: 1001 return 0444; 1002 case hwmon_in_max: 1003 case hwmon_in_min: 1004 case hwmon_in_enable: 1005 return 0644; 1006 case hwmon_in_reset_history: 1007 return 0200; 1008 default: 1009 return 0; 1010 } 1011 } 1012 1013 static umode_t ltc4282_curr_is_visible(u32 attr) 1014 { 1015 switch (attr) { 1016 case hwmon_curr_input: 1017 case hwmon_curr_highest: 1018 case hwmon_curr_lowest: 1019 case hwmon_curr_max_alarm: 1020 case hwmon_curr_min_alarm: 1021 case hwmon_curr_crit_alarm: 1022 case hwmon_curr_label: 1023 return 0444; 1024 case hwmon_curr_max: 1025 case hwmon_curr_min: 1026 return 0644; 1027 case hwmon_curr_reset_history: 1028 return 0200; 1029 default: 1030 return 0; 1031 } 1032 } 1033 1034 static umode_t ltc4282_power_is_visible(u32 attr) 1035 { 1036 switch (attr) { 1037 case hwmon_power_input: 1038 case hwmon_power_input_highest: 1039 case hwmon_power_input_lowest: 1040 case hwmon_power_label: 1041 case hwmon_power_max_alarm: 1042 case hwmon_power_min_alarm: 1043 return 0444; 1044 case hwmon_power_max: 1045 case hwmon_power_min: 1046 return 0644; 1047 case hwmon_power_reset_history: 1048 return 0200; 1049 default: 1050 return 0; 1051 } 1052 } 1053 1054 static umode_t ltc4282_is_visible(const void *data, 1055 enum hwmon_sensor_types type, 1056 u32 attr, int channel) 1057 { 1058 switch (type) { 1059 case hwmon_in: 1060 return ltc4282_in_is_visible(data, attr); 1061 case hwmon_curr: 1062 return ltc4282_curr_is_visible(attr); 1063 case hwmon_power: 1064 return ltc4282_power_is_visible(attr); 1065 case hwmon_energy: 1066 /* hwmon_energy_enable */ 1067 return 0644; 1068 case hwmon_energy64: 1069 /* hwmon_energy_input */ 1070 return 0444; 1071 default: 1072 return 0; 1073 } 1074 } 1075 1076 static const char * const ltc4282_in_strs[] = { 1077 "VSOURCE", "VDD", "VGPIO" 1078 }; 1079 1080 static int ltc4282_read_labels(struct device *dev, 1081 enum hwmon_sensor_types type, 1082 u32 attr, int channel, const char **str) 1083 { 1084 switch (type) { 1085 case hwmon_in: 1086 *str = ltc4282_in_strs[channel]; 1087 return 0; 1088 case hwmon_curr: 1089 *str = "ISENSE"; 1090 return 0; 1091 case hwmon_power: 1092 *str = "Power"; 1093 return 0; 1094 default: 1095 return -EOPNOTSUPP; 1096 } 1097 } 1098 1099 static const struct clk_ops ltc4282_ops = { 1100 .recalc_rate = ltc4282_recalc_rate, 1101 .determine_rate = ltc4282_determine_rate, 1102 .set_rate = ltc4282_set_rate, 1103 .disable = ltc4282_disable, 1104 }; 1105 1106 static int ltc428_clk_provider_setup(struct ltc4282_state *st, 1107 struct device *dev) 1108 { 1109 struct clk_init_data init; 1110 int ret; 1111 1112 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1113 return 0; 1114 1115 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", 1116 fwnode_get_name(dev_fwnode(dev))); 1117 if (!init.name) 1118 return -ENOMEM; 1119 1120 init.ops = <c4282_ops; 1121 init.flags = CLK_GET_RATE_NOCACHE; 1122 st->clk_hw.init = &init; 1123 1124 ret = devm_clk_hw_register(dev, &st->clk_hw); 1125 if (ret) 1126 return ret; 1127 1128 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1129 &st->clk_hw); 1130 } 1131 1132 static int ltc428_clks_setup(struct ltc4282_state *st, struct device *dev) 1133 { 1134 unsigned long rate; 1135 struct clk *clkin; 1136 u32 val; 1137 int ret; 1138 1139 ret = ltc428_clk_provider_setup(st, dev); 1140 if (ret) 1141 return ret; 1142 1143 clkin = devm_clk_get_optional_enabled(dev, NULL); 1144 if (IS_ERR(clkin)) 1145 return dev_err_probe(dev, PTR_ERR(clkin), 1146 "Failed to get clkin"); 1147 if (!clkin) 1148 return 0; 1149 1150 rate = clk_get_rate(clkin); 1151 if (!in_range(rate, LTC4282_CLKIN_MIN, LTC4282_CLKIN_RANGE)) 1152 return dev_err_probe(dev, -EINVAL, 1153 "Invalid clkin range(%lu) [%lu %lu]\n", 1154 rate, LTC4282_CLKIN_MIN, 1155 LTC4282_CLKIN_MAX); 1156 1157 /* 1158 * Clocks faster than 250KHZ should be reduced to 250KHZ. The clock 1159 * frequency is divided by twice the value in the register. 1160 */ 1161 val = rate / (2 * LTC4282_CLKIN_MIN); 1162 1163 return regmap_update_bits(st->map, LTC4282_CLK_DIV, 1164 LTC4282_CLK_DIV_MASK, 1165 FIELD_PREP(LTC4282_CLK_DIV_MASK, val)); 1166 } 1167 1168 static const int ltc4282_curr_lim_uv[] = { 1169 12500, 15625, 18750, 21875, 25000, 28125, 31250, 34375 1170 }; 1171 1172 static int ltc4282_get_defaults(struct ltc4282_state *st, u32 *vin_mode) 1173 { 1174 u32 reg_val, ilm_adjust; 1175 int ret; 1176 1177 ret = regmap_read(st->map, LTC4282_ADC_CTRL, ®_val); 1178 if (ret) 1179 return ret; 1180 1181 st->energy_en = !FIELD_GET(LTC4282_METER_HALT_MASK, reg_val); 1182 1183 ret = regmap_read(st->map, LTC4282_CTRL_MSB, ®_val); 1184 if (ret) 1185 return ret; 1186 1187 *vin_mode = FIELD_GET(LTC4282_CTRL_VIN_MODE_MASK, reg_val); 1188 1189 ret = regmap_read(st->map, LTC4282_ILIM_ADJUST, ®_val); 1190 if (ret) 1191 return ret; 1192 1193 ilm_adjust = FIELD_GET(LTC4282_ILIM_ADJUST_MASK, reg_val); 1194 st->vsense_max = ltc4282_curr_lim_uv[ilm_adjust]; 1195 1196 st->in0_1_cache[LTC4282_CHAN_VSOURCE].en = FIELD_GET(LTC4282_VDD_MONITOR_MASK, 1197 ilm_adjust); 1198 if (!st->in0_1_cache[LTC4282_CHAN_VSOURCE].en) { 1199 st->in0_1_cache[LTC4282_CHAN_VDD].en = true; 1200 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 1201 &st->in0_1_cache[LTC4282_CHAN_VSOURCE].in_max_raw); 1202 } 1203 1204 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 1205 &st->in0_1_cache[LTC4282_CHAN_VDD].in_max_raw); 1206 } 1207 1208 /* 1209 * Set max limits for ISENSE and Power as that depends on the max voltage on 1210 * rsense that is defined in ILIM_ADJUST. This is specially important for power 1211 * because for some rsense and vfsout values, if we allow the default raw 255 1212 * value, that would overflow long in 32bit archs when reading back the max 1213 * power limit. 1214 * 1215 * Also set meaningful historic values for VDD and VSOURCE 1216 * (0 would not mean much). 1217 */ 1218 static int ltc4282_set_max_limits(struct ltc4282_state *st) 1219 { 1220 int ret; 1221 1222 ret = ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MAX, 40 * MILLI, 1223 st->vsense_max); 1224 if (ret) 1225 return ret; 1226 1227 /* Power is given by ISENSE * Vout. */ 1228 st->power_max = DIV_ROUND_CLOSEST_ULL((u64)st->vsense_max * DECA * MILLI, 1229 st->rsense) * st->vfs_out; 1230 ret = ltc4282_write_power_byte(st, LTC4282_POWER_MAX, st->power_max); 1231 if (ret) 1232 return ret; 1233 1234 if (st->in0_1_cache[LTC4282_CHAN_VDD].en) { 1235 st->in0_1_cache[LTC4282_CHAN_VSOURCE].in_lowest = st->vfs_out; 1236 return __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 1237 st->vdd, 0, st->vfs_out); 1238 } 1239 1240 st->in0_1_cache[LTC4282_CHAN_VDD].in_lowest = st->vdd; 1241 return __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 1242 st->vfs_out, 0, st->vfs_out); 1243 } 1244 1245 static const char * const ltc4282_gpio1_modes[] = { 1246 "power_bad", "power_good" 1247 }; 1248 1249 static const char * const ltc4282_gpio2_modes[] = { 1250 "adc_input", "stress_fet" 1251 }; 1252 1253 static int ltc4282_gpio_setup(struct ltc4282_state *st, struct device *dev) 1254 { 1255 const char *func = NULL; 1256 int ret; 1257 1258 ret = device_property_read_string(dev, "adi,gpio1-mode", &func); 1259 if (!ret) { 1260 ret = match_string(ltc4282_gpio1_modes, 1261 ARRAY_SIZE(ltc4282_gpio1_modes), func); 1262 if (ret < 0) 1263 return dev_err_probe(dev, ret, 1264 "Invalid func(%s) for gpio1\n", 1265 func); 1266 1267 ret = regmap_update_bits(st->map, LTC4282_GPIO_CONFIG, 1268 LTC4282_GPIO_1_CONFIG_MASK, 1269 FIELD_PREP(LTC4282_GPIO_1_CONFIG_MASK, ret)); 1270 if (ret) 1271 return ret; 1272 } 1273 1274 ret = device_property_read_string(dev, "adi,gpio2-mode", &func); 1275 if (!ret) { 1276 ret = match_string(ltc4282_gpio2_modes, 1277 ARRAY_SIZE(ltc4282_gpio2_modes), func); 1278 if (ret < 0) 1279 return dev_err_probe(dev, ret, 1280 "Invalid func(%s) for gpio2\n", 1281 func); 1282 if (!ret) { 1283 /* setting the bit to 1 so the ADC to monitors GPIO2 */ 1284 ret = regmap_set_bits(st->map, LTC4282_ILIM_ADJUST, 1285 LTC4282_GPIO_MODE_MASK); 1286 } else { 1287 ret = regmap_update_bits(st->map, LTC4282_GPIO_CONFIG, 1288 LTC4282_GPIO_2_FET_STRESS_MASK, 1289 FIELD_PREP(LTC4282_GPIO_2_FET_STRESS_MASK, 1)); 1290 } 1291 1292 if (ret) 1293 return ret; 1294 } 1295 1296 if (!device_property_read_bool(dev, "adi,gpio3-monitor-enable")) 1297 return 0; 1298 1299 if (func && !strcmp(func, "adc_input")) 1300 return dev_err_probe(dev, -EINVAL, 1301 "Cannot have both gpio2 and gpio3 muxed into the ADC"); 1302 1303 return regmap_clear_bits(st->map, LTC4282_ILIM_ADJUST, 1304 LTC4282_GPIO_MODE_MASK); 1305 } 1306 1307 static const char * const ltc4282_dividers[] = { 1308 "external", "vdd_5_percent", "vdd_10_percent", "vdd_15_percent" 1309 }; 1310 1311 /* This maps the Vout full scale for the given Vin mode */ 1312 static const u16 ltc4282_vfs_milli[] = { 5540, 8320, 16640, 33280 }; 1313 1314 static const u16 ltc4282_vdd_milli[] = { 3300, 5000, 12000, 24000 }; 1315 1316 enum { 1317 LTC4282_VIN_3_3V, 1318 LTC4282_VIN_5V, 1319 LTC4282_VIN_12V, 1320 LTC4282_VIN_24V, 1321 }; 1322 1323 static int ltc4282_setup(struct ltc4282_state *st, struct device *dev) 1324 { 1325 const char *divider; 1326 u32 val, vin_mode; 1327 int ret; 1328 1329 /* The part has an eeprom so let's get the needed defaults from it */ 1330 ret = ltc4282_get_defaults(st, &vin_mode); 1331 if (ret) 1332 return ret; 1333 1334 /* default to 1 milli-ohm so we can probe without FW properties */ 1335 st->rsense = 1 * (NANO / MILLI); 1336 ret = device_property_read_u32(dev, "adi,rsense-nano-ohms", 1337 &st->rsense); 1338 if (!ret) { 1339 if (st->rsense < CENTI) 1340 return dev_err_probe(dev, -EINVAL, 1341 "adi,rsense-nano-ohms too small (< %lu)\n", 1342 CENTI); 1343 } 1344 1345 /* 1346 * The resolution for rsense is tenths of micro (eg: 62.5 uOhm) which 1347 * means we need nano in the bindings. However, to make things easier to 1348 * handle (with respect to overflows) we divide it by 100 as we don't 1349 * really need the last two digits. 1350 */ 1351 st->rsense /= CENTI; 1352 1353 val = vin_mode; 1354 ret = device_property_read_u32(dev, "adi,vin-mode-microvolt", &val); 1355 if (!ret) { 1356 switch (val) { 1357 case 3300000: 1358 val = LTC4282_VIN_3_3V; 1359 break; 1360 case 5000000: 1361 val = LTC4282_VIN_5V; 1362 break; 1363 case 12000000: 1364 val = LTC4282_VIN_12V; 1365 break; 1366 case 24000000: 1367 val = LTC4282_VIN_24V; 1368 break; 1369 default: 1370 return dev_err_probe(dev, -EINVAL, 1371 "Invalid val(%u) for vin-mode-microvolt\n", 1372 val); 1373 } 1374 1375 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1376 LTC4282_CTRL_VIN_MODE_MASK, 1377 FIELD_PREP(LTC4282_CTRL_VIN_MODE_MASK, val)); 1378 if (ret) 1379 return ret; 1380 1381 /* Foldback mode should also be set to the input voltage */ 1382 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 1383 LTC4282_FOLDBACK_MODE_MASK, 1384 FIELD_PREP(LTC4282_FOLDBACK_MODE_MASK, val)); 1385 if (ret) 1386 return ret; 1387 } 1388 1389 st->vfs_out = ltc4282_vfs_milli[val]; 1390 st->vdd = ltc4282_vdd_milli[val]; 1391 1392 ret = device_property_read_u32(dev, "adi,current-limit-sense-microvolt", 1393 &st->vsense_max); 1394 if (!ret) { 1395 int reg_val; 1396 1397 switch (st->vsense_max) { 1398 case 12500: 1399 reg_val = 0; 1400 break; 1401 case 15625: 1402 reg_val = 1; 1403 break; 1404 case 18750: 1405 reg_val = 2; 1406 break; 1407 case 21875: 1408 reg_val = 3; 1409 break; 1410 case 25000: 1411 reg_val = 4; 1412 break; 1413 case 28125: 1414 reg_val = 5; 1415 break; 1416 case 31250: 1417 reg_val = 6; 1418 break; 1419 case 34375: 1420 reg_val = 7; 1421 break; 1422 default: 1423 return dev_err_probe(dev, -EINVAL, 1424 "Invalid val(%u) for adi,current-limit-microvolt\n", 1425 st->vsense_max); 1426 } 1427 1428 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 1429 LTC4282_ILIM_ADJUST_MASK, 1430 FIELD_PREP(LTC4282_ILIM_ADJUST_MASK, reg_val)); 1431 if (ret) 1432 return ret; 1433 } 1434 1435 ret = ltc4282_set_max_limits(st); 1436 if (ret) 1437 return ret; 1438 1439 ret = device_property_read_string(dev, "adi,overvoltage-dividers", 1440 ÷r); 1441 if (!ret) { 1442 int div = match_string(ltc4282_dividers, 1443 ARRAY_SIZE(ltc4282_dividers), divider); 1444 if (div < 0) 1445 return dev_err_probe(dev, -EINVAL, 1446 "Invalid val(%s) for adi,overvoltage-divider\n", 1447 divider); 1448 1449 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1450 LTC4282_CTRL_OV_MODE_MASK, 1451 FIELD_PREP(LTC4282_CTRL_OV_MODE_MASK, div)); 1452 } 1453 1454 ret = device_property_read_string(dev, "adi,undervoltage-dividers", 1455 ÷r); 1456 if (!ret) { 1457 int div = match_string(ltc4282_dividers, 1458 ARRAY_SIZE(ltc4282_dividers), divider); 1459 if (div < 0) 1460 return dev_err_probe(dev, -EINVAL, 1461 "Invalid val(%s) for adi,undervoltage-divider\n", 1462 divider); 1463 1464 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1465 LTC4282_CTRL_UV_MODE_MASK, 1466 FIELD_PREP(LTC4282_CTRL_UV_MODE_MASK, div)); 1467 } 1468 1469 if (device_property_read_bool(dev, "adi,overcurrent-retry")) { 1470 ret = regmap_set_bits(st->map, LTC4282_CTRL_LSB, 1471 LTC4282_CTRL_OC_RETRY_MASK); 1472 if (ret) 1473 return ret; 1474 } 1475 1476 if (device_property_read_bool(dev, "adi,overvoltage-retry-disable")) { 1477 ret = regmap_clear_bits(st->map, LTC4282_CTRL_LSB, 1478 LTC4282_CTRL_OV_RETRY_MASK); 1479 if (ret) 1480 return ret; 1481 } 1482 1483 if (device_property_read_bool(dev, "adi,undervoltage-retry-disable")) { 1484 ret = regmap_clear_bits(st->map, LTC4282_CTRL_LSB, 1485 LTC4282_CTRL_UV_RETRY_MASK); 1486 if (ret) 1487 return ret; 1488 } 1489 1490 if (device_property_read_bool(dev, "adi,fault-log-enable")) { 1491 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_FAULT_LOG_EN_MASK); 1492 if (ret) 1493 return ret; 1494 } 1495 1496 ret = device_property_read_u32(dev, "adi,fet-bad-timeout-ms", &val); 1497 if (!ret) { 1498 if (val > LTC4282_FET_BAD_MAX_TIMEOUT) 1499 return dev_err_probe(dev, -EINVAL, 1500 "Invalid value(%u) for adi,fet-bad-timeout-ms", 1501 val); 1502 1503 ret = regmap_write(st->map, LTC4282_FET_BAD_FAULT_TIMEOUT, val); 1504 if (ret) 1505 return ret; 1506 } 1507 1508 return ltc4282_gpio_setup(st, dev); 1509 } 1510 1511 static bool ltc4282_readable_reg(struct device *dev, unsigned int reg) 1512 { 1513 if (reg == LTC4282_RESERVED_1 || reg == LTC4282_RESERVED_2) 1514 return false; 1515 1516 return true; 1517 } 1518 1519 static bool ltc4282_writable_reg(struct device *dev, unsigned int reg) 1520 { 1521 if (reg == LTC4282_STATUS_LSB || reg == LTC4282_STATUS_MSB) 1522 return false; 1523 if (reg == LTC4282_RESERVED_1 || reg == LTC4282_RESERVED_2) 1524 return false; 1525 1526 return true; 1527 } 1528 1529 static const struct regmap_config ltc4282_regmap_config = { 1530 .reg_bits = 8, 1531 .val_bits = 8, 1532 .max_register = LTC4282_RESERVED_3, 1533 .readable_reg = ltc4282_readable_reg, 1534 .writeable_reg = ltc4282_writable_reg, 1535 }; 1536 1537 static const struct hwmon_channel_info * const ltc4282_info[] = { 1538 HWMON_CHANNEL_INFO(in, 1539 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1540 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1541 HWMON_I_MAX_ALARM | HWMON_I_ENABLE | 1542 HWMON_I_RESET_HISTORY | HWMON_I_FAULT | 1543 HWMON_I_LABEL, 1544 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1545 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1546 HWMON_I_MAX_ALARM | HWMON_I_LCRIT_ALARM | 1547 HWMON_I_CRIT_ALARM | HWMON_I_ENABLE | 1548 HWMON_I_RESET_HISTORY | HWMON_I_LABEL, 1549 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1550 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1551 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1552 HWMON_I_LABEL), 1553 HWMON_CHANNEL_INFO(curr, 1554 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | 1555 HWMON_C_MAX | HWMON_C_MIN | HWMON_C_MIN_ALARM | 1556 HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM | 1557 HWMON_C_RESET_HISTORY | HWMON_C_LABEL), 1558 HWMON_CHANNEL_INFO(power, 1559 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | 1560 HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN | 1561 HWMON_P_MAX_ALARM | HWMON_P_MIN_ALARM | 1562 HWMON_P_RESET_HISTORY | HWMON_P_LABEL), 1563 HWMON_CHANNEL_INFO(energy, 1564 HWMON_E_ENABLE), 1565 HWMON_CHANNEL_INFO(energy64, 1566 HWMON_E_INPUT), 1567 NULL 1568 }; 1569 1570 static const struct hwmon_ops ltc4282_hwmon_ops = { 1571 .read = ltc4282_read, 1572 .write = ltc4282_write, 1573 .is_visible = ltc4282_is_visible, 1574 .read_string = ltc4282_read_labels, 1575 }; 1576 1577 static const struct hwmon_chip_info ltc4282_chip_info = { 1578 .ops = <c4282_hwmon_ops, 1579 .info = ltc4282_info, 1580 }; 1581 1582 static int ltc4282_show_fault_log(void *arg, u64 *val, u32 mask) 1583 { 1584 struct ltc4282_state *st = arg; 1585 long alarm; 1586 int ret; 1587 1588 ret = ltc4282_read_alarm(st, LTC4282_FAULT_LOG, mask, &alarm); 1589 if (ret) 1590 return ret; 1591 1592 *val = alarm; 1593 1594 return 0; 1595 } 1596 1597 static int ltc4282_show_curr1_crit_fault_log(void *arg, u64 *val) 1598 { 1599 return ltc4282_show_fault_log(arg, val, LTC4282_OC_FAULT_MASK); 1600 } 1601 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_curr1_crit_fault_log, 1602 ltc4282_show_curr1_crit_fault_log, NULL, "%llu\n"); 1603 1604 static int ltc4282_show_in1_lcrit_fault_log(void *arg, u64 *val) 1605 { 1606 return ltc4282_show_fault_log(arg, val, LTC4282_UV_FAULT_MASK); 1607 } 1608 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_in1_lcrit_fault_log, 1609 ltc4282_show_in1_lcrit_fault_log, NULL, "%llu\n"); 1610 1611 static int ltc4282_show_in1_crit_fault_log(void *arg, u64 *val) 1612 { 1613 return ltc4282_show_fault_log(arg, val, LTC4282_OV_FAULT_MASK); 1614 } 1615 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_in1_crit_fault_log, 1616 ltc4282_show_in1_crit_fault_log, NULL, "%llu\n"); 1617 1618 static int ltc4282_show_fet_bad_fault_log(void *arg, u64 *val) 1619 { 1620 return ltc4282_show_fault_log(arg, val, LTC4282_FET_BAD_FAULT_MASK); 1621 } 1622 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_fet_bad_fault_log, 1623 ltc4282_show_fet_bad_fault_log, NULL, "%llu\n"); 1624 1625 static int ltc4282_show_fet_short_fault_log(void *arg, u64 *val) 1626 { 1627 return ltc4282_show_fault_log(arg, val, LTC4282_FET_SHORT_FAULT_MASK); 1628 } 1629 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_fet_short_fault_log, 1630 ltc4282_show_fet_short_fault_log, NULL, "%llu\n"); 1631 1632 static int ltc4282_show_power1_bad_fault_log(void *arg, u64 *val) 1633 { 1634 return ltc4282_show_fault_log(arg, val, LTC4282_POWER_BAD_FAULT_MASK); 1635 } 1636 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_power1_bad_fault_log, 1637 ltc4282_show_power1_bad_fault_log, NULL, "%llu\n"); 1638 1639 static void ltc4282_debugfs_init(struct ltc4282_state *st, struct i2c_client *i2c) 1640 { 1641 debugfs_create_file_unsafe("power1_bad_fault_log", 0400, i2c->debugfs, st, 1642 <c4282_power1_bad_fault_log); 1643 debugfs_create_file_unsafe("in0_fet_short_fault_log", 0400, i2c->debugfs, st, 1644 <c4282_fet_short_fault_log); 1645 debugfs_create_file_unsafe("in0_fet_bad_fault_log", 0400, i2c->debugfs, st, 1646 <c4282_fet_bad_fault_log); 1647 debugfs_create_file_unsafe("in1_crit_fault_log", 0400, i2c->debugfs, st, 1648 <c4282_in1_crit_fault_log); 1649 debugfs_create_file_unsafe("in1_lcrit_fault_log", 0400, i2c->debugfs, st, 1650 <c4282_in1_lcrit_fault_log); 1651 debugfs_create_file_unsafe("curr1_crit_fault_log", 0400, i2c->debugfs, st, 1652 <c4282_curr1_crit_fault_log); 1653 } 1654 1655 static int ltc4282_probe(struct i2c_client *i2c) 1656 { 1657 struct device *dev = &i2c->dev, *hwmon; 1658 struct ltc4282_state *st; 1659 int ret; 1660 1661 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 1662 if (!st) 1663 return -ENOMEM; 1664 1665 st->map = devm_regmap_init_i2c(i2c, <c4282_regmap_config); 1666 if (IS_ERR(st->map)) 1667 return dev_err_probe(dev, PTR_ERR(st->map), 1668 "failed regmap init\n"); 1669 1670 /* Soft reset */ 1671 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_RESET_MASK); 1672 if (ret) 1673 return ret; 1674 1675 /* Yes, it's big but it is as specified in the datasheet */ 1676 msleep(3200); 1677 1678 ret = ltc428_clks_setup(st, dev); 1679 if (ret) 1680 return ret; 1681 1682 ret = ltc4282_setup(st, dev); 1683 if (ret) 1684 return ret; 1685 1686 hwmon = devm_hwmon_device_register_with_info(dev, "ltc4282", st, 1687 <c4282_chip_info, NULL); 1688 if (IS_ERR(hwmon)) 1689 return PTR_ERR(hwmon); 1690 1691 ltc4282_debugfs_init(st, i2c); 1692 1693 return 0; 1694 } 1695 1696 static const struct of_device_id ltc4282_of_match[] = { 1697 { .compatible = "adi,ltc4282" }, 1698 {} 1699 }; 1700 MODULE_DEVICE_TABLE(of, ltc4282_of_match); 1701 1702 static struct i2c_driver ltc4282_driver = { 1703 .driver = { 1704 .name = "ltc4282", 1705 .of_match_table = ltc4282_of_match, 1706 }, 1707 .probe = ltc4282_probe, 1708 }; 1709 module_i2c_driver(ltc4282_driver); 1710 1711 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1712 MODULE_DESCRIPTION("LTC4282 I2C High Current Hot Swap Controller"); 1713 MODULE_LICENSE("GPL"); 1714