1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C 4 * 5 * Copyright 2023 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/cleanup.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/hwmon.h> 15 #include <linux/i2c.h> 16 #include <linux/math.h> 17 #include <linux/minmax.h> 18 #include <linux/module.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/regmap.h> 21 #include <linux/property.h> 22 #include <linux/string.h> 23 #include <linux/units.h> 24 #include <linux/util_macros.h> 25 26 #define LTC4282_CTRL_LSB 0x00 27 #define LTC4282_CTRL_OV_RETRY_MASK BIT(0) 28 #define LTC4282_CTRL_UV_RETRY_MASK BIT(1) 29 #define LTC4282_CTRL_OC_RETRY_MASK BIT(2) 30 #define LTC4282_CTRL_ON_ACTIVE_LOW_MASK BIT(5) 31 #define LTC4282_CTRL_ON_DELAY_MASK BIT(6) 32 #define LTC4282_CTRL_MSB 0x01 33 #define LTC4282_CTRL_VIN_MODE_MASK GENMASK(1, 0) 34 #define LTC4282_CTRL_OV_MODE_MASK GENMASK(3, 2) 35 #define LTC4282_CTRL_UV_MODE_MASK GENMASK(5, 4) 36 #define LTC4282_FAULT_LOG 0x04 37 #define LTC4282_OV_FAULT_MASK BIT(0) 38 #define LTC4282_UV_FAULT_MASK BIT(1) 39 #define LTC4282_VDD_FAULT_MASK \ 40 (LTC4282_OV_FAULT_MASK | LTC4282_UV_FAULT_MASK) 41 #define LTC4282_OC_FAULT_MASK BIT(2) 42 #define LTC4282_POWER_BAD_FAULT_MASK BIT(3) 43 #define LTC4282_FET_SHORT_FAULT_MASK BIT(5) 44 #define LTC4282_FET_BAD_FAULT_MASK BIT(6) 45 #define LTC4282_FET_FAILURE_FAULT_MASK \ 46 (LTC4282_FET_SHORT_FAULT_MASK | LTC4282_FET_BAD_FAULT_MASK) 47 #define LTC4282_ADC_ALERT_LOG 0x05 48 #define LTC4282_GPIO_ALARM_L_MASK BIT(0) 49 #define LTC4282_GPIO_ALARM_H_MASK BIT(1) 50 #define LTC4282_VSOURCE_ALARM_L_MASK BIT(2) 51 #define LTC4282_VSOURCE_ALARM_H_MASK BIT(3) 52 #define LTC4282_VSENSE_ALARM_L_MASK BIT(4) 53 #define LTC4282_VSENSE_ALARM_H_MASK BIT(5) 54 #define LTC4282_POWER_ALARM_L_MASK BIT(6) 55 #define LTC4282_POWER_ALARM_H_MASK BIT(7) 56 #define LTC4282_FET_BAD_FAULT_TIMEOUT 0x06 57 #define LTC4282_FET_BAD_MAX_TIMEOUT 255 58 #define LTC4282_GPIO_CONFIG 0x07 59 #define LTC4282_GPIO_2_FET_STRESS_MASK BIT(1) 60 #define LTC4282_GPIO_1_CONFIG_MASK GENMASK(5, 4) 61 #define LTC4282_VGPIO_MIN 0x08 62 #define LTC4282_VGPIO_MAX 0x09 63 #define LTC4282_VSOURCE_MIN 0x0a 64 #define LTC4282_VSOURCE_MAX 0x0b 65 #define LTC4282_VSENSE_MIN 0x0c 66 #define LTC4282_VSENSE_MAX 0x0d 67 #define LTC4282_POWER_MIN 0x0e 68 #define LTC4282_POWER_MAX 0x0f 69 #define LTC4282_CLK_DIV 0x10 70 #define LTC4282_CLK_DIV_MASK GENMASK(4, 0) 71 #define LTC4282_CLKOUT_MASK GENMASK(6, 5) 72 #define LTC4282_ILIM_ADJUST 0x11 73 #define LTC4282_GPIO_MODE_MASK BIT(1) 74 #define LTC4282_VDD_MONITOR_MASK BIT(2) 75 #define LTC4282_FOLDBACK_MODE_MASK GENMASK(4, 3) 76 #define LTC4282_ILIM_ADJUST_MASK GENMASK(7, 5) 77 #define LTC4282_ENERGY 0x12 78 #define LTC4282_TIME_COUNTER 0x18 79 #define LTC4282_ALERT_CTRL 0x1c 80 #define LTC4282_ALERT_OUT_MASK BIT(6) 81 #define LTC4282_ADC_CTRL 0x1d 82 #define LTC4282_FAULT_LOG_EN_MASK BIT(2) 83 #define LTC4282_METER_HALT_MASK BIT(5) 84 #define LTC4282_METER_RESET_MASK BIT(6) 85 #define LTC4282_RESET_MASK BIT(7) 86 #define LTC4282_STATUS_LSB 0x1e 87 #define LTC4282_OV_STATUS_MASK BIT(0) 88 #define LTC4282_UV_STATUS_MASK BIT(1) 89 #define LTC4282_VDD_STATUS_MASK \ 90 (LTC4282_OV_STATUS_MASK | LTC4282_UV_STATUS_MASK) 91 #define LTC4282_OC_STATUS_MASK BIT(2) 92 #define LTC4282_POWER_GOOD_MASK BIT(3) 93 #define LTC4282_FET_FAILURE_MASK GENMASK(6, 5) 94 #define LTC4282_STATUS_MSB 0x1f 95 #define LTC4282_RESERVED_1 0x32 96 #define LTC4282_RESERVED_2 0x33 97 #define LTC4282_VGPIO 0x34 98 #define LTC4282_VGPIO_LOWEST 0x36 99 #define LTC4282_VGPIO_HIGHEST 0x38 100 #define LTC4282_VSOURCE 0x3a 101 #define LTC4282_VSOURCE_LOWEST 0x3c 102 #define LTC4282_VSOURCE_HIGHEST 0x3e 103 #define LTC4282_VSENSE 0x40 104 #define LTC4282_VSENSE_LOWEST 0x42 105 #define LTC4282_VSENSE_HIGHEST 0x44 106 #define LTC4282_POWER 0x46 107 #define LTC4282_POWER_LOWEST 0x48 108 #define LTC4282_POWER_HIGHEST 0x4a 109 #define LTC4282_RESERVED_3 0x50 110 111 #define LTC4282_CLKIN_MIN (250 * KILO) 112 #define LTC4282_CLKIN_MAX (15500 * KILO) 113 #define LTC4282_CLKIN_RANGE (LTC4282_CLKIN_MAX - LTC4282_CLKIN_MIN + 1) 114 #define LTC4282_CLKOUT_SYSTEM (250 * KILO) 115 #define LTC4282_CLKOUT_CNV 15 116 117 enum { 118 LTC4282_CHAN_VSOURCE, 119 LTC4282_CHAN_VDD, 120 LTC4282_CHAN_VGPIO, 121 }; 122 123 struct ltc4282_cache { 124 u32 in_max_raw; 125 u32 in_min_raw; 126 long in_highest; 127 long in_lowest; 128 bool en; 129 }; 130 131 struct ltc4282_state { 132 struct regmap *map; 133 struct clk_hw clk_hw; 134 /* 135 * Used to cache values for VDD/VSOURCE depending which will be used 136 * when hwmon is not enabled for that channel. Needed because they share 137 * the same registers. 138 */ 139 struct ltc4282_cache in0_1_cache[LTC4282_CHAN_VGPIO]; 140 u32 vsense_max; 141 long power_max; 142 u32 rsense; 143 u16 vdd; 144 u16 vfs_out; 145 bool energy_en; 146 }; 147 148 enum { 149 LTC4282_CLKOUT_NONE, 150 LTC4282_CLKOUT_INT, 151 LTC4282_CLKOUT_TICK, 152 }; 153 154 static int ltc4282_set_rate(struct clk_hw *hw, 155 unsigned long rate, unsigned long parent_rate) 156 { 157 struct ltc4282_state *st = container_of(hw, struct ltc4282_state, 158 clk_hw); 159 u32 val = LTC4282_CLKOUT_INT; 160 161 if (rate == LTC4282_CLKOUT_CNV) 162 val = LTC4282_CLKOUT_TICK; 163 164 return regmap_update_bits(st->map, LTC4282_CLK_DIV, LTC4282_CLKOUT_MASK, 165 FIELD_PREP(LTC4282_CLKOUT_MASK, val)); 166 } 167 168 /* 169 * Note the 15HZ conversion rate assumes 12bit ADC which is what we are 170 * supporting for now. 171 */ 172 static const unsigned int ltc4282_out_rates[] = { 173 LTC4282_CLKOUT_CNV, LTC4282_CLKOUT_SYSTEM 174 }; 175 176 static int ltc4282_determine_rate(struct clk_hw *hw, 177 struct clk_rate_request *req) 178 { 179 int idx = find_closest(req->rate, ltc4282_out_rates, 180 ARRAY_SIZE(ltc4282_out_rates)); 181 182 req->rate = ltc4282_out_rates[idx]; 183 184 return 0; 185 } 186 187 static unsigned long ltc4282_recalc_rate(struct clk_hw *hw, 188 unsigned long parent) 189 { 190 struct ltc4282_state *st = container_of(hw, struct ltc4282_state, 191 clk_hw); 192 u32 clkdiv; 193 int ret; 194 195 ret = regmap_read(st->map, LTC4282_CLK_DIV, &clkdiv); 196 if (ret) 197 return 0; 198 199 clkdiv = FIELD_GET(LTC4282_CLKOUT_MASK, clkdiv); 200 if (!clkdiv) 201 return 0; 202 if (clkdiv == LTC4282_CLKOUT_INT) 203 return LTC4282_CLKOUT_SYSTEM; 204 205 return LTC4282_CLKOUT_CNV; 206 } 207 208 static void ltc4282_disable(struct clk_hw *clk_hw) 209 { 210 struct ltc4282_state *st = container_of(clk_hw, struct ltc4282_state, 211 clk_hw); 212 213 regmap_clear_bits(st->map, LTC4282_CLK_DIV, LTC4282_CLKOUT_MASK); 214 } 215 216 static int ltc4282_read_voltage_word(const struct ltc4282_state *st, u32 reg, 217 u32 fs, long *val) 218 { 219 __be16 in; 220 int ret; 221 222 ret = regmap_bulk_read(st->map, reg, &in, sizeof(in)); 223 if (ret) 224 return ret; 225 226 /* 227 * This is also used to calculate current in which case fs comes in 228 * 10 * uV. Hence the ULL usage. 229 */ 230 *val = DIV_ROUND_CLOSEST_ULL(be16_to_cpu(in) * (u64)fs, U16_MAX); 231 return 0; 232 } 233 234 static int ltc4282_read_voltage_byte_cached(const struct ltc4282_state *st, 235 u32 reg, u32 fs, long *val, 236 u32 *cached_raw) 237 { 238 int ret; 239 u32 in; 240 241 if (cached_raw) { 242 in = *cached_raw; 243 } else { 244 ret = regmap_read(st->map, reg, &in); 245 if (ret) 246 return ret; 247 } 248 249 *val = DIV_ROUND_CLOSEST(in * fs, U8_MAX); 250 return 0; 251 } 252 253 static int ltc4282_read_voltage_byte(const struct ltc4282_state *st, u32 reg, 254 u32 fs, long *val) 255 { 256 return ltc4282_read_voltage_byte_cached(st, reg, fs, val, NULL); 257 } 258 259 static int __ltc4282_read_alarm(struct ltc4282_state *st, u32 reg, u32 mask, 260 long *val) 261 { 262 u32 alarm; 263 int ret; 264 265 ret = regmap_read(st->map, reg, &alarm); 266 if (ret) 267 return ret; 268 269 *val = !!(alarm & mask); 270 271 /* if not status/fault logs, clear the alarm after reading it */ 272 if (reg != LTC4282_STATUS_LSB && reg != LTC4282_FAULT_LOG) 273 return regmap_clear_bits(st->map, reg, mask); 274 275 return 0; 276 } 277 278 static int ltc4282_read_alarm(struct ltc4282_state *st, u32 reg, u32 mask, 279 long *val) 280 { 281 return __ltc4282_read_alarm(st, reg, mask, val); 282 } 283 284 static int ltc4282_vdd_source_read_in(struct ltc4282_state *st, u32 channel, 285 long *val) 286 { 287 if (!st->in0_1_cache[channel].en) 288 return -ENODATA; 289 290 return ltc4282_read_voltage_word(st, LTC4282_VSOURCE, st->vfs_out, val); 291 } 292 293 static int ltc4282_vdd_source_read_hist(struct ltc4282_state *st, u32 reg, 294 u32 channel, long *cached, long *val) 295 { 296 int ret; 297 298 if (!st->in0_1_cache[channel].en) { 299 *val = *cached; 300 return 0; 301 } 302 303 ret = ltc4282_read_voltage_word(st, reg, st->vfs_out, val); 304 if (ret) 305 return ret; 306 307 *cached = *val; 308 return 0; 309 } 310 311 static int ltc4282_vdd_source_read_lim(struct ltc4282_state *st, u32 reg, 312 u32 channel, u32 *cached, long *val) 313 { 314 if (!st->in0_1_cache[channel].en) 315 return ltc4282_read_voltage_byte_cached(st, reg, st->vfs_out, 316 val, cached); 317 318 return ltc4282_read_voltage_byte(st, reg, st->vfs_out, val); 319 } 320 321 static int ltc4282_vdd_source_read_alm(struct ltc4282_state *st, u32 mask, 322 u32 channel, long *val) 323 { 324 if (!st->in0_1_cache[channel].en) { 325 /* 326 * Do this otherwise alarms can get confused because we clear 327 * them after reading them. So, if someone mistakenly reads 328 * VSOURCE right before VDD (or the other way around), we might 329 * get no alarm just because it was cleared when reading VSOURCE 330 * and had no time for a new conversion and thus having the 331 * alarm again. 332 */ 333 *val = 0; 334 return 0; 335 } 336 337 return __ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, mask, val); 338 } 339 340 static int ltc4282_read_in(struct ltc4282_state *st, u32 attr, long *val, 341 u32 channel) 342 { 343 switch (attr) { 344 case hwmon_in_input: 345 if (channel == LTC4282_CHAN_VGPIO) 346 return ltc4282_read_voltage_word(st, LTC4282_VGPIO, 347 1280, val); 348 349 return ltc4282_vdd_source_read_in(st, channel, val); 350 case hwmon_in_highest: 351 if (channel == LTC4282_CHAN_VGPIO) 352 return ltc4282_read_voltage_word(st, 353 LTC4282_VGPIO_HIGHEST, 354 1280, val); 355 356 return ltc4282_vdd_source_read_hist(st, LTC4282_VSOURCE_HIGHEST, 357 channel, 358 &st->in0_1_cache[channel].in_highest, val); 359 case hwmon_in_lowest: 360 if (channel == LTC4282_CHAN_VGPIO) 361 return ltc4282_read_voltage_word(st, LTC4282_VGPIO_LOWEST, 362 1280, val); 363 364 return ltc4282_vdd_source_read_hist(st, LTC4282_VSOURCE_LOWEST, 365 channel, 366 &st->in0_1_cache[channel].in_lowest, val); 367 case hwmon_in_max_alarm: 368 if (channel == LTC4282_CHAN_VGPIO) 369 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 370 LTC4282_GPIO_ALARM_H_MASK, 371 val); 372 373 return ltc4282_vdd_source_read_alm(st, 374 LTC4282_VSOURCE_ALARM_H_MASK, 375 channel, val); 376 case hwmon_in_min_alarm: 377 if (channel == LTC4282_CHAN_VGPIO) 378 ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 379 LTC4282_GPIO_ALARM_L_MASK, val); 380 381 return ltc4282_vdd_source_read_alm(st, 382 LTC4282_VSOURCE_ALARM_L_MASK, 383 channel, val); 384 case hwmon_in_crit_alarm: 385 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 386 LTC4282_OV_STATUS_MASK, val); 387 case hwmon_in_lcrit_alarm: 388 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 389 LTC4282_UV_STATUS_MASK, val); 390 case hwmon_in_max: 391 if (channel == LTC4282_CHAN_VGPIO) 392 return ltc4282_read_voltage_byte(st, LTC4282_VGPIO_MAX, 393 1280, val); 394 395 return ltc4282_vdd_source_read_lim(st, LTC4282_VSOURCE_MAX, 396 channel, 397 &st->in0_1_cache[channel].in_max_raw, val); 398 case hwmon_in_min: 399 if (channel == LTC4282_CHAN_VGPIO) 400 return ltc4282_read_voltage_byte(st, LTC4282_VGPIO_MIN, 401 1280, val); 402 403 return ltc4282_vdd_source_read_lim(st, LTC4282_VSOURCE_MIN, 404 channel, 405 &st->in0_1_cache[channel].in_min_raw, val); 406 case hwmon_in_enable: 407 *val = st->in0_1_cache[channel].en; 408 return 0; 409 case hwmon_in_fault: 410 /* 411 * We report failure if we detect either a fer_bad or a 412 * fet_short in the status register. 413 */ 414 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 415 LTC4282_FET_FAILURE_MASK, val); 416 default: 417 return -EOPNOTSUPP; 418 } 419 } 420 421 static int ltc4282_read_current_word(const struct ltc4282_state *st, u32 reg, 422 long *val) 423 { 424 long in; 425 int ret; 426 427 /* 428 * We pass in full scale in 10 * micro (note that 40 is already 429 * millivolt) so we have better approximations to calculate current. 430 */ 431 ret = ltc4282_read_voltage_word(st, reg, DECA * 40 * MILLI, &in); 432 if (ret) 433 return ret; 434 435 *val = DIV_ROUND_CLOSEST(in * MILLI, st->rsense); 436 437 return 0; 438 } 439 440 static int ltc4282_read_current_byte(const struct ltc4282_state *st, u32 reg, 441 long *val) 442 { 443 long in; 444 int ret; 445 446 ret = ltc4282_read_voltage_byte(st, reg, DECA * 40 * MILLI, &in); 447 if (ret) 448 return ret; 449 450 *val = DIV_ROUND_CLOSEST(in * MILLI, st->rsense); 451 452 return 0; 453 } 454 455 static int ltc4282_read_curr(struct ltc4282_state *st, const u32 attr, 456 long *val) 457 { 458 switch (attr) { 459 case hwmon_curr_input: 460 return ltc4282_read_current_word(st, LTC4282_VSENSE, val); 461 case hwmon_curr_highest: 462 return ltc4282_read_current_word(st, LTC4282_VSENSE_HIGHEST, 463 val); 464 case hwmon_curr_lowest: 465 return ltc4282_read_current_word(st, LTC4282_VSENSE_LOWEST, 466 val); 467 case hwmon_curr_max: 468 return ltc4282_read_current_byte(st, LTC4282_VSENSE_MAX, val); 469 case hwmon_curr_min: 470 return ltc4282_read_current_byte(st, LTC4282_VSENSE_MIN, val); 471 case hwmon_curr_max_alarm: 472 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 473 LTC4282_VSENSE_ALARM_H_MASK, val); 474 case hwmon_curr_min_alarm: 475 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 476 LTC4282_VSENSE_ALARM_L_MASK, val); 477 case hwmon_curr_crit_alarm: 478 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 479 LTC4282_OC_STATUS_MASK, val); 480 default: 481 return -EOPNOTSUPP; 482 } 483 } 484 485 static int ltc4282_read_power_word(const struct ltc4282_state *st, u32 reg, 486 long *val) 487 { 488 u64 temp = DECA * 40ULL * st->vfs_out * BIT(16), temp_2; 489 __be16 raw; 490 u16 power; 491 int ret; 492 493 ret = regmap_bulk_read(st->map, reg, &raw, sizeof(raw)); 494 if (ret) 495 return ret; 496 497 power = be16_to_cpu(raw); 498 /* 499 * Power is given by: 500 * P = CODE(16b) * 0.040 * Vfs(out) * 2^16 / ((2^16 - 1)^2 * Rsense) 501 */ 502 if (check_mul_overflow(power * temp, MICRO, &temp_2)) { 503 temp = DIV_ROUND_CLOSEST_ULL(power * temp, U16_MAX); 504 *val = DIV64_U64_ROUND_CLOSEST(temp * MICRO, 505 U16_MAX * (u64)st->rsense); 506 return 0; 507 } 508 509 *val = DIV64_U64_ROUND_CLOSEST(temp_2, 510 st->rsense * int_pow(U16_MAX, 2)); 511 512 return 0; 513 } 514 515 static int ltc4282_read_power_byte(const struct ltc4282_state *st, u32 reg, 516 long *val) 517 { 518 u32 power; 519 u64 temp; 520 int ret; 521 522 ret = regmap_read(st->map, reg, &power); 523 if (ret) 524 return ret; 525 526 temp = power * 40 * DECA * st->vfs_out * BIT_ULL(8); 527 *val = DIV64_U64_ROUND_CLOSEST(temp * MICRO, 528 int_pow(U8_MAX, 2) * st->rsense); 529 530 return 0; 531 } 532 533 static int ltc4282_read_energy(const struct ltc4282_state *st, s64 *val) 534 { 535 u64 temp, energy; 536 __be64 raw; 537 int ret; 538 539 ret = regmap_bulk_read(st->map, LTC4282_ENERGY, &raw, 6); 540 if (ret) 541 return ret; 542 543 energy = be64_to_cpu(raw) >> 16; 544 /* 545 * The formula for energy is given by: 546 * E = CODE(48b) * 0.040 * Vfs(out) * Tconv * 256 / 547 * ((2^16 - 1)^2 * Rsense) 548 * 549 * Since we only support 12bit ADC, Tconv = 0.065535s. Passing Vfs(out) 550 * and 0.040 to mV and Tconv to us, we can simplify the formula to: 551 * E = CODE(48b) * 40 * Vfs(out) * 256 / (U16_MAX * Rsense) 552 * 553 * As Rsense can have tenths of micro-ohm resolution, we need to 554 * multiply by DECA to get microujoule. 555 */ 556 if (check_mul_overflow(DECA * st->vfs_out * 40 * BIT(8), energy, &temp)) { 557 temp = DIV_ROUND_CLOSEST(DECA * st->vfs_out * 40 * BIT(8), U16_MAX); 558 *val = DIV_ROUND_CLOSEST_ULL(temp * energy, st->rsense); 559 return 0; 560 } 561 562 *val = DIV64_U64_ROUND_CLOSEST(temp, U16_MAX * (u64)st->rsense); 563 564 return 0; 565 } 566 567 static int ltc4282_read_power(struct ltc4282_state *st, const u32 attr, 568 long *val) 569 { 570 switch (attr) { 571 case hwmon_power_input: 572 return ltc4282_read_power_word(st, LTC4282_POWER, val); 573 case hwmon_power_input_highest: 574 return ltc4282_read_power_word(st, LTC4282_POWER_HIGHEST, val); 575 case hwmon_power_input_lowest: 576 return ltc4282_read_power_word(st, LTC4282_POWER_LOWEST, val); 577 case hwmon_power_max_alarm: 578 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 579 LTC4282_POWER_ALARM_H_MASK, val); 580 case hwmon_power_min_alarm: 581 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 582 LTC4282_POWER_ALARM_L_MASK, val); 583 case hwmon_power_max: 584 return ltc4282_read_power_byte(st, LTC4282_POWER_MAX, val); 585 case hwmon_power_min: 586 return ltc4282_read_power_byte(st, LTC4282_POWER_MIN, val); 587 default: 588 return -EOPNOTSUPP; 589 } 590 } 591 592 static int ltc4282_read(struct device *dev, enum hwmon_sensor_types type, 593 u32 attr, int channel, long *val) 594 { 595 struct ltc4282_state *st = dev_get_drvdata(dev); 596 597 switch (type) { 598 case hwmon_in: 599 return ltc4282_read_in(st, attr, val, channel); 600 case hwmon_curr: 601 return ltc4282_read_curr(st, attr, val); 602 case hwmon_power: 603 return ltc4282_read_power(st, attr, val); 604 case hwmon_energy: 605 *val = st->energy_en; 606 return 0; 607 case hwmon_energy64: 608 if (st->energy_en) 609 return ltc4282_read_energy(st, (s64 *)val); 610 return -ENODATA; 611 default: 612 return -EOPNOTSUPP; 613 } 614 } 615 616 static int ltc4282_write_power_byte(const struct ltc4282_state *st, u32 reg, 617 long val) 618 { 619 u32 power; 620 u64 temp; 621 622 if (val > st->power_max) 623 val = st->power_max; 624 625 temp = val * int_pow(U8_MAX, 2) * st->rsense; 626 power = DIV64_U64_ROUND_CLOSEST(temp, 627 MICRO * DECA * 256ULL * st->vfs_out * 40); 628 629 return regmap_write(st->map, reg, power); 630 } 631 632 static int ltc4282_write_power_word(const struct ltc4282_state *st, u32 reg, 633 long val) 634 { 635 u64 temp = int_pow(U16_MAX, 2) * st->rsense, temp_2; 636 __be16 __raw; 637 u16 code; 638 639 if (check_mul_overflow(temp, val, &temp_2)) { 640 temp = DIV_ROUND_CLOSEST_ULL(temp, DECA * MICRO); 641 code = DIV64_U64_ROUND_CLOSEST(temp * val, 642 40ULL * BIT(16) * st->vfs_out); 643 } else { 644 temp = DECA * MICRO * 40ULL * BIT(16) * st->vfs_out; 645 code = DIV64_U64_ROUND_CLOSEST(temp_2, temp); 646 } 647 648 __raw = cpu_to_be16(code); 649 return regmap_bulk_write(st->map, reg, &__raw, sizeof(__raw)); 650 } 651 652 static int __ltc4282_in_write_history(const struct ltc4282_state *st, u32 reg, 653 long lowest, long highest, u32 fs) 654 { 655 __be16 __raw; 656 u16 tmp; 657 int ret; 658 659 tmp = DIV_ROUND_CLOSEST(U16_MAX * lowest, fs); 660 661 __raw = cpu_to_be16(tmp); 662 663 ret = regmap_bulk_write(st->map, reg, &__raw, 2); 664 if (ret) 665 return ret; 666 667 tmp = DIV_ROUND_CLOSEST(U16_MAX * highest, fs); 668 669 __raw = cpu_to_be16(tmp); 670 671 return regmap_bulk_write(st->map, reg + 2, &__raw, 2); 672 } 673 674 static int ltc4282_in_write_history(struct ltc4282_state *st, u32 reg, 675 long lowest, long highest, u32 fs) 676 { 677 return __ltc4282_in_write_history(st, reg, lowest, highest, fs); 678 } 679 680 static int ltc4282_power_reset_hist(struct ltc4282_state *st) 681 { 682 int ret; 683 684 ret = ltc4282_write_power_word(st, LTC4282_POWER_LOWEST, 685 st->power_max); 686 if (ret) 687 return ret; 688 689 ret = ltc4282_write_power_word(st, LTC4282_POWER_HIGHEST, 0); 690 if (ret) 691 return ret; 692 693 /* now, let's also clear possible power_bad fault logs */ 694 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 695 LTC4282_POWER_BAD_FAULT_MASK); 696 } 697 698 static int ltc4282_write_power(struct ltc4282_state *st, u32 attr, 699 long val) 700 { 701 switch (attr) { 702 case hwmon_power_max: 703 return ltc4282_write_power_byte(st, LTC4282_POWER_MAX, val); 704 case hwmon_power_min: 705 return ltc4282_write_power_byte(st, LTC4282_POWER_MIN, val); 706 case hwmon_power_reset_history: 707 return ltc4282_power_reset_hist(st); 708 default: 709 return -EOPNOTSUPP; 710 } 711 } 712 713 static int ltc4282_write_voltage_byte_cached(const struct ltc4282_state *st, 714 u32 reg, u32 fs, long val, 715 u32 *cache_raw) 716 { 717 u32 in; 718 719 val = clamp_val(val, 0, fs); 720 in = DIV_ROUND_CLOSEST(val * U8_MAX, fs); 721 722 if (cache_raw) { 723 *cache_raw = in; 724 return 0; 725 } 726 727 return regmap_write(st->map, reg, in); 728 } 729 730 static int ltc4282_write_voltage_byte(const struct ltc4282_state *st, u32 reg, 731 u32 fs, long val) 732 { 733 return ltc4282_write_voltage_byte_cached(st, reg, fs, val, NULL); 734 } 735 736 static int ltc4282_cache_history(struct ltc4282_state *st, u32 channel) 737 { 738 long val; 739 int ret; 740 741 ret = ltc4282_read_voltage_word(st, LTC4282_VSOURCE_LOWEST, st->vfs_out, 742 &val); 743 if (ret) 744 return ret; 745 746 st->in0_1_cache[channel].in_lowest = val; 747 748 ret = ltc4282_read_voltage_word(st, LTC4282_VSOURCE_HIGHEST, 749 st->vfs_out, &val); 750 if (ret) 751 return ret; 752 753 st->in0_1_cache[channel].in_highest = val; 754 755 ret = regmap_read(st->map, LTC4282_VSOURCE_MIN, 756 &st->in0_1_cache[channel].in_min_raw); 757 if (ret) 758 return ret; 759 760 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 761 &st->in0_1_cache[channel].in_max_raw); 762 } 763 764 static int ltc4282_cache_sync(struct ltc4282_state *st, u32 channel) 765 { 766 int ret; 767 768 ret = __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 769 st->in0_1_cache[channel].in_lowest, 770 st->in0_1_cache[channel].in_highest, 771 st->vfs_out); 772 if (ret) 773 return ret; 774 775 ret = regmap_write(st->map, LTC4282_VSOURCE_MIN, 776 st->in0_1_cache[channel].in_min_raw); 777 if (ret) 778 return ret; 779 780 return regmap_write(st->map, LTC4282_VSOURCE_MAX, 781 st->in0_1_cache[channel].in_max_raw); 782 } 783 784 static int ltc4282_vdd_source_write_lim(struct ltc4282_state *st, u32 reg, 785 int channel, u32 *cache, long val) 786 { 787 int ret; 788 789 if (st->in0_1_cache[channel].en) 790 ret = ltc4282_write_voltage_byte(st, reg, st->vfs_out, val); 791 else 792 ret = ltc4282_write_voltage_byte_cached(st, reg, st->vfs_out, 793 val, cache); 794 795 return ret; 796 } 797 798 static int ltc4282_vdd_source_reset_hist(struct ltc4282_state *st, int channel) 799 { 800 long lowest = st->vfs_out; 801 int ret; 802 803 if (channel == LTC4282_CHAN_VDD) 804 lowest = st->vdd; 805 806 if (st->in0_1_cache[channel].en) { 807 ret = __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 808 lowest, 0, st->vfs_out); 809 if (ret) 810 return ret; 811 } 812 813 st->in0_1_cache[channel].in_lowest = lowest; 814 st->in0_1_cache[channel].in_highest = 0; 815 816 /* 817 * We are also clearing possible fault logs in reset_history. Clearing 818 * the logs might be important when the auto retry bits are not enabled 819 * as the chip only enables the output again after having these logs 820 * cleared. As some of these logs are related to limits, it makes sense 821 * to clear them in here. For VDD, we need to clear under/over voltage 822 * events. For VSOURCE, fet_short and fet_bad... 823 */ 824 if (channel == LTC4282_CHAN_VSOURCE) 825 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 826 LTC4282_FET_FAILURE_FAULT_MASK); 827 828 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 829 LTC4282_VDD_FAULT_MASK); 830 } 831 832 /* 833 * We need to mux between VSOURCE and VDD which means they are mutually 834 * exclusive. Moreover, we can't really disable both VDD and VSOURCE as the ADC 835 * is continuously running (we cannot independently halt it without also 836 * stopping VGPIO). Hence, the logic is that disabling or enabling VDD will 837 * automatically have the reverse effect on VSOURCE and vice-versa. 838 */ 839 static int ltc4282_vdd_source_enable(struct ltc4282_state *st, int channel, 840 long val) 841 { 842 int ret, other_chan = ~channel & 0x1; 843 u8 __val = val; 844 845 if (st->in0_1_cache[channel].en == !!val) 846 return 0; 847 848 /* clearing the bit makes the ADC to monitor VDD */ 849 if (channel == LTC4282_CHAN_VDD) 850 __val = !__val; 851 852 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 853 LTC4282_VDD_MONITOR_MASK, 854 FIELD_PREP(LTC4282_VDD_MONITOR_MASK, !!__val)); 855 if (ret) 856 return ret; 857 858 st->in0_1_cache[channel].en = !!val; 859 st->in0_1_cache[other_chan].en = !val; 860 861 if (st->in0_1_cache[channel].en) { 862 /* 863 * Then, we are disabling @other_chan. Let's save it's current 864 * history. 865 */ 866 ret = ltc4282_cache_history(st, other_chan); 867 if (ret) 868 return ret; 869 870 return ltc4282_cache_sync(st, channel); 871 } 872 /* 873 * Then, we are enabling @other_chan. We need to do the opposite from 874 * above. 875 */ 876 ret = ltc4282_cache_history(st, channel); 877 if (ret) 878 return ret; 879 880 return ltc4282_cache_sync(st, other_chan); 881 } 882 883 static int ltc4282_write_in(struct ltc4282_state *st, u32 attr, long val, 884 int channel) 885 { 886 switch (attr) { 887 case hwmon_in_max: 888 if (channel == LTC4282_CHAN_VGPIO) 889 return ltc4282_write_voltage_byte(st, LTC4282_VGPIO_MAX, 890 1280, val); 891 892 return ltc4282_vdd_source_write_lim(st, LTC4282_VSOURCE_MAX, 893 channel, 894 &st->in0_1_cache[channel].in_max_raw, val); 895 case hwmon_in_min: 896 if (channel == LTC4282_CHAN_VGPIO) 897 return ltc4282_write_voltage_byte(st, LTC4282_VGPIO_MIN, 898 1280, val); 899 900 return ltc4282_vdd_source_write_lim(st, LTC4282_VSOURCE_MIN, 901 channel, 902 &st->in0_1_cache[channel].in_min_raw, val); 903 case hwmon_in_reset_history: 904 if (channel == LTC4282_CHAN_VGPIO) 905 return ltc4282_in_write_history(st, 906 LTC4282_VGPIO_LOWEST, 907 1280, 0, 1280); 908 909 return ltc4282_vdd_source_reset_hist(st, channel); 910 case hwmon_in_enable: 911 return ltc4282_vdd_source_enable(st, channel, val); 912 default: 913 return -EOPNOTSUPP; 914 } 915 } 916 917 static int ltc4282_curr_reset_hist(struct ltc4282_state *st) 918 { 919 int ret; 920 921 ret = __ltc4282_in_write_history(st, LTC4282_VSENSE_LOWEST, 922 st->vsense_max, 0, 40 * MILLI); 923 if (ret) 924 return ret; 925 926 /* now, let's also clear possible overcurrent fault logs */ 927 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 928 LTC4282_OC_FAULT_MASK); 929 } 930 931 static int ltc4282_write_curr(struct ltc4282_state *st, u32 attr, 932 long val) 933 { 934 /* need to pass it in millivolt */ 935 u32 in = DIV_ROUND_CLOSEST_ULL((u64)val * st->rsense, DECA * MICRO); 936 937 switch (attr) { 938 case hwmon_curr_max: 939 return ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MAX, 40, 940 in); 941 case hwmon_curr_min: 942 return ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MIN, 40, 943 in); 944 case hwmon_curr_reset_history: 945 return ltc4282_curr_reset_hist(st); 946 default: 947 return -EOPNOTSUPP; 948 } 949 } 950 951 static int ltc4282_energy_enable_set(struct ltc4282_state *st, long val) 952 { 953 int ret; 954 955 /* setting the bit halts the meter */ 956 ret = regmap_update_bits(st->map, LTC4282_ADC_CTRL, 957 LTC4282_METER_HALT_MASK, 958 FIELD_PREP(LTC4282_METER_HALT_MASK, !val)); 959 if (ret) 960 return ret; 961 962 st->energy_en = !!val; 963 964 return 0; 965 } 966 967 static int ltc4282_write(struct device *dev, 968 enum hwmon_sensor_types type, 969 u32 attr, int channel, long val) 970 { 971 struct ltc4282_state *st = dev_get_drvdata(dev); 972 973 switch (type) { 974 case hwmon_power: 975 return ltc4282_write_power(st, attr, val); 976 case hwmon_in: 977 return ltc4282_write_in(st, attr, val, channel); 978 case hwmon_curr: 979 return ltc4282_write_curr(st, attr, val); 980 case hwmon_energy: 981 return ltc4282_energy_enable_set(st, val); 982 default: 983 return -EOPNOTSUPP; 984 } 985 } 986 987 static umode_t ltc4282_in_is_visible(const struct ltc4282_state *st, u32 attr) 988 { 989 switch (attr) { 990 case hwmon_in_input: 991 case hwmon_in_highest: 992 case hwmon_in_lowest: 993 case hwmon_in_max_alarm: 994 case hwmon_in_min_alarm: 995 case hwmon_in_label: 996 case hwmon_in_lcrit_alarm: 997 case hwmon_in_crit_alarm: 998 case hwmon_in_fault: 999 return 0444; 1000 case hwmon_in_max: 1001 case hwmon_in_min: 1002 case hwmon_in_enable: 1003 return 0644; 1004 case hwmon_in_reset_history: 1005 return 0200; 1006 default: 1007 return 0; 1008 } 1009 } 1010 1011 static umode_t ltc4282_curr_is_visible(u32 attr) 1012 { 1013 switch (attr) { 1014 case hwmon_curr_input: 1015 case hwmon_curr_highest: 1016 case hwmon_curr_lowest: 1017 case hwmon_curr_max_alarm: 1018 case hwmon_curr_min_alarm: 1019 case hwmon_curr_crit_alarm: 1020 case hwmon_curr_label: 1021 return 0444; 1022 case hwmon_curr_max: 1023 case hwmon_curr_min: 1024 return 0644; 1025 case hwmon_curr_reset_history: 1026 return 0200; 1027 default: 1028 return 0; 1029 } 1030 } 1031 1032 static umode_t ltc4282_power_is_visible(u32 attr) 1033 { 1034 switch (attr) { 1035 case hwmon_power_input: 1036 case hwmon_power_input_highest: 1037 case hwmon_power_input_lowest: 1038 case hwmon_power_label: 1039 case hwmon_power_max_alarm: 1040 case hwmon_power_min_alarm: 1041 return 0444; 1042 case hwmon_power_max: 1043 case hwmon_power_min: 1044 return 0644; 1045 case hwmon_power_reset_history: 1046 return 0200; 1047 default: 1048 return 0; 1049 } 1050 } 1051 1052 static umode_t ltc4282_is_visible(const void *data, 1053 enum hwmon_sensor_types type, 1054 u32 attr, int channel) 1055 { 1056 switch (type) { 1057 case hwmon_in: 1058 return ltc4282_in_is_visible(data, attr); 1059 case hwmon_curr: 1060 return ltc4282_curr_is_visible(attr); 1061 case hwmon_power: 1062 return ltc4282_power_is_visible(attr); 1063 case hwmon_energy: 1064 /* hwmon_energy_enable */ 1065 return 0644; 1066 case hwmon_energy64: 1067 /* hwmon_energy_input */ 1068 return 0444; 1069 default: 1070 return 0; 1071 } 1072 } 1073 1074 static const char * const ltc4282_in_strs[] = { 1075 "VSOURCE", "VDD", "VGPIO" 1076 }; 1077 1078 static int ltc4282_read_labels(struct device *dev, 1079 enum hwmon_sensor_types type, 1080 u32 attr, int channel, const char **str) 1081 { 1082 switch (type) { 1083 case hwmon_in: 1084 *str = ltc4282_in_strs[channel]; 1085 return 0; 1086 case hwmon_curr: 1087 *str = "ISENSE"; 1088 return 0; 1089 case hwmon_power: 1090 *str = "Power"; 1091 return 0; 1092 default: 1093 return -EOPNOTSUPP; 1094 } 1095 } 1096 1097 static const struct clk_ops ltc4282_ops = { 1098 .recalc_rate = ltc4282_recalc_rate, 1099 .determine_rate = ltc4282_determine_rate, 1100 .set_rate = ltc4282_set_rate, 1101 .disable = ltc4282_disable, 1102 }; 1103 1104 static int ltc428_clk_provider_setup(struct ltc4282_state *st, 1105 struct device *dev) 1106 { 1107 struct clk_init_data init; 1108 int ret; 1109 1110 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1111 return 0; 1112 1113 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", 1114 fwnode_get_name(dev_fwnode(dev))); 1115 if (!init.name) 1116 return -ENOMEM; 1117 1118 init.ops = <c4282_ops; 1119 init.flags = CLK_GET_RATE_NOCACHE; 1120 st->clk_hw.init = &init; 1121 1122 ret = devm_clk_hw_register(dev, &st->clk_hw); 1123 if (ret) 1124 return ret; 1125 1126 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1127 &st->clk_hw); 1128 } 1129 1130 static int ltc428_clks_setup(struct ltc4282_state *st, struct device *dev) 1131 { 1132 unsigned long rate; 1133 struct clk *clkin; 1134 u32 val; 1135 int ret; 1136 1137 ret = ltc428_clk_provider_setup(st, dev); 1138 if (ret) 1139 return ret; 1140 1141 clkin = devm_clk_get_optional_enabled(dev, NULL); 1142 if (IS_ERR(clkin)) 1143 return dev_err_probe(dev, PTR_ERR(clkin), 1144 "Failed to get clkin"); 1145 if (!clkin) 1146 return 0; 1147 1148 rate = clk_get_rate(clkin); 1149 if (!in_range(rate, LTC4282_CLKIN_MIN, LTC4282_CLKIN_RANGE)) 1150 return dev_err_probe(dev, -EINVAL, 1151 "Invalid clkin range(%lu) [%lu %lu]\n", 1152 rate, LTC4282_CLKIN_MIN, 1153 LTC4282_CLKIN_MAX); 1154 1155 /* 1156 * Clocks faster than 250KHZ should be reduced to 250KHZ. The clock 1157 * frequency is divided by twice the value in the register. 1158 */ 1159 val = rate / (2 * LTC4282_CLKIN_MIN); 1160 1161 return regmap_update_bits(st->map, LTC4282_CLK_DIV, 1162 LTC4282_CLK_DIV_MASK, 1163 FIELD_PREP(LTC4282_CLK_DIV_MASK, val)); 1164 } 1165 1166 static const int ltc4282_curr_lim_uv[] = { 1167 12500, 15625, 18750, 21875, 25000, 28125, 31250, 34375 1168 }; 1169 1170 static int ltc4282_get_defaults(struct ltc4282_state *st, u32 *vin_mode) 1171 { 1172 u32 reg_val, ilm_adjust; 1173 int ret; 1174 1175 ret = regmap_read(st->map, LTC4282_ADC_CTRL, ®_val); 1176 if (ret) 1177 return ret; 1178 1179 st->energy_en = !FIELD_GET(LTC4282_METER_HALT_MASK, reg_val); 1180 1181 ret = regmap_read(st->map, LTC4282_CTRL_MSB, ®_val); 1182 if (ret) 1183 return ret; 1184 1185 *vin_mode = FIELD_GET(LTC4282_CTRL_VIN_MODE_MASK, reg_val); 1186 1187 ret = regmap_read(st->map, LTC4282_ILIM_ADJUST, ®_val); 1188 if (ret) 1189 return ret; 1190 1191 ilm_adjust = FIELD_GET(LTC4282_ILIM_ADJUST_MASK, reg_val); 1192 st->vsense_max = ltc4282_curr_lim_uv[ilm_adjust]; 1193 1194 st->in0_1_cache[LTC4282_CHAN_VSOURCE].en = FIELD_GET(LTC4282_VDD_MONITOR_MASK, 1195 ilm_adjust); 1196 if (!st->in0_1_cache[LTC4282_CHAN_VSOURCE].en) { 1197 st->in0_1_cache[LTC4282_CHAN_VDD].en = true; 1198 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 1199 &st->in0_1_cache[LTC4282_CHAN_VSOURCE].in_max_raw); 1200 } 1201 1202 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 1203 &st->in0_1_cache[LTC4282_CHAN_VDD].in_max_raw); 1204 } 1205 1206 /* 1207 * Set max limits for ISENSE and Power as that depends on the max voltage on 1208 * rsense that is defined in ILIM_ADJUST. This is specially important for power 1209 * because for some rsense and vfsout values, if we allow the default raw 255 1210 * value, that would overflow long in 32bit archs when reading back the max 1211 * power limit. 1212 * 1213 * Also set meaningful historic values for VDD and VSOURCE 1214 * (0 would not mean much). 1215 */ 1216 static int ltc4282_set_max_limits(struct ltc4282_state *st) 1217 { 1218 int ret; 1219 1220 ret = ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MAX, 40 * MILLI, 1221 st->vsense_max); 1222 if (ret) 1223 return ret; 1224 1225 /* Power is given by ISENSE * Vout. */ 1226 st->power_max = DIV_ROUND_CLOSEST(st->vsense_max * DECA * MILLI, st->rsense) * st->vfs_out; 1227 ret = ltc4282_write_power_byte(st, LTC4282_POWER_MAX, st->power_max); 1228 if (ret) 1229 return ret; 1230 1231 if (st->in0_1_cache[LTC4282_CHAN_VDD].en) { 1232 st->in0_1_cache[LTC4282_CHAN_VSOURCE].in_lowest = st->vfs_out; 1233 return __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 1234 st->vdd, 0, st->vfs_out); 1235 } 1236 1237 st->in0_1_cache[LTC4282_CHAN_VDD].in_lowest = st->vdd; 1238 return __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 1239 st->vfs_out, 0, st->vfs_out); 1240 } 1241 1242 static const char * const ltc4282_gpio1_modes[] = { 1243 "power_bad", "power_good" 1244 }; 1245 1246 static const char * const ltc4282_gpio2_modes[] = { 1247 "adc_input", "stress_fet" 1248 }; 1249 1250 static int ltc4282_gpio_setup(struct ltc4282_state *st, struct device *dev) 1251 { 1252 const char *func = NULL; 1253 int ret; 1254 1255 ret = device_property_read_string(dev, "adi,gpio1-mode", &func); 1256 if (!ret) { 1257 ret = match_string(ltc4282_gpio1_modes, 1258 ARRAY_SIZE(ltc4282_gpio1_modes), func); 1259 if (ret < 0) 1260 return dev_err_probe(dev, ret, 1261 "Invalid func(%s) for gpio1\n", 1262 func); 1263 1264 ret = regmap_update_bits(st->map, LTC4282_GPIO_CONFIG, 1265 LTC4282_GPIO_1_CONFIG_MASK, 1266 FIELD_PREP(LTC4282_GPIO_1_CONFIG_MASK, ret)); 1267 if (ret) 1268 return ret; 1269 } 1270 1271 ret = device_property_read_string(dev, "adi,gpio2-mode", &func); 1272 if (!ret) { 1273 ret = match_string(ltc4282_gpio2_modes, 1274 ARRAY_SIZE(ltc4282_gpio2_modes), func); 1275 if (ret < 0) 1276 return dev_err_probe(dev, ret, 1277 "Invalid func(%s) for gpio2\n", 1278 func); 1279 if (!ret) { 1280 /* setting the bit to 1 so the ADC to monitors GPIO2 */ 1281 ret = regmap_set_bits(st->map, LTC4282_ILIM_ADJUST, 1282 LTC4282_GPIO_MODE_MASK); 1283 } else { 1284 ret = regmap_update_bits(st->map, LTC4282_GPIO_CONFIG, 1285 LTC4282_GPIO_2_FET_STRESS_MASK, 1286 FIELD_PREP(LTC4282_GPIO_2_FET_STRESS_MASK, 1)); 1287 } 1288 1289 if (ret) 1290 return ret; 1291 } 1292 1293 if (!device_property_read_bool(dev, "adi,gpio3-monitor-enable")) 1294 return 0; 1295 1296 if (func && !strcmp(func, "adc_input")) 1297 return dev_err_probe(dev, -EINVAL, 1298 "Cannot have both gpio2 and gpio3 muxed into the ADC"); 1299 1300 return regmap_clear_bits(st->map, LTC4282_ILIM_ADJUST, 1301 LTC4282_GPIO_MODE_MASK); 1302 } 1303 1304 static const char * const ltc4282_dividers[] = { 1305 "external", "vdd_5_percent", "vdd_10_percent", "vdd_15_percent" 1306 }; 1307 1308 /* This maps the Vout full scale for the given Vin mode */ 1309 static const u16 ltc4282_vfs_milli[] = { 5540, 8320, 16640, 33280 }; 1310 1311 static const u16 ltc4282_vdd_milli[] = { 3300, 5000, 12000, 24000 }; 1312 1313 enum { 1314 LTC4282_VIN_3_3V, 1315 LTC4282_VIN_5V, 1316 LTC4282_VIN_12V, 1317 LTC4282_VIN_24V, 1318 }; 1319 1320 static int ltc4282_setup(struct ltc4282_state *st, struct device *dev) 1321 { 1322 const char *divider; 1323 u32 val, vin_mode; 1324 int ret; 1325 1326 /* The part has an eeprom so let's get the needed defaults from it */ 1327 ret = ltc4282_get_defaults(st, &vin_mode); 1328 if (ret) 1329 return ret; 1330 1331 ret = device_property_read_u32(dev, "adi,rsense-nano-ohms", 1332 &st->rsense); 1333 if (ret) 1334 return dev_err_probe(dev, ret, 1335 "Failed to read adi,rsense-nano-ohms\n"); 1336 if (st->rsense < CENTI) 1337 return dev_err_probe(dev, -EINVAL, 1338 "adi,rsense-nano-ohms too small (< %lu)\n", 1339 CENTI); 1340 1341 /* 1342 * The resolution for rsense is tenths of micro (eg: 62.5 uOhm) which 1343 * means we need nano in the bindings. However, to make things easier to 1344 * handle (with respect to overflows) we divide it by 100 as we don't 1345 * really need the last two digits. 1346 */ 1347 st->rsense /= CENTI; 1348 1349 val = vin_mode; 1350 ret = device_property_read_u32(dev, "adi,vin-mode-microvolt", &val); 1351 if (!ret) { 1352 switch (val) { 1353 case 3300000: 1354 val = LTC4282_VIN_3_3V; 1355 break; 1356 case 5000000: 1357 val = LTC4282_VIN_5V; 1358 break; 1359 case 12000000: 1360 val = LTC4282_VIN_12V; 1361 break; 1362 case 24000000: 1363 val = LTC4282_VIN_24V; 1364 break; 1365 default: 1366 return dev_err_probe(dev, -EINVAL, 1367 "Invalid val(%u) for vin-mode-microvolt\n", 1368 val); 1369 } 1370 1371 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1372 LTC4282_CTRL_VIN_MODE_MASK, 1373 FIELD_PREP(LTC4282_CTRL_VIN_MODE_MASK, val)); 1374 if (ret) 1375 return ret; 1376 1377 /* Foldback mode should also be set to the input voltage */ 1378 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 1379 LTC4282_FOLDBACK_MODE_MASK, 1380 FIELD_PREP(LTC4282_FOLDBACK_MODE_MASK, val)); 1381 if (ret) 1382 return ret; 1383 } 1384 1385 st->vfs_out = ltc4282_vfs_milli[val]; 1386 st->vdd = ltc4282_vdd_milli[val]; 1387 1388 ret = device_property_read_u32(dev, "adi,current-limit-sense-microvolt", 1389 &st->vsense_max); 1390 if (!ret) { 1391 int reg_val; 1392 1393 switch (val) { 1394 case 12500: 1395 reg_val = 0; 1396 break; 1397 case 15625: 1398 reg_val = 1; 1399 break; 1400 case 18750: 1401 reg_val = 2; 1402 break; 1403 case 21875: 1404 reg_val = 3; 1405 break; 1406 case 25000: 1407 reg_val = 4; 1408 break; 1409 case 28125: 1410 reg_val = 5; 1411 break; 1412 case 31250: 1413 reg_val = 6; 1414 break; 1415 case 34375: 1416 reg_val = 7; 1417 break; 1418 default: 1419 return dev_err_probe(dev, -EINVAL, 1420 "Invalid val(%u) for adi,current-limit-microvolt\n", 1421 st->vsense_max); 1422 } 1423 1424 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 1425 LTC4282_ILIM_ADJUST_MASK, 1426 FIELD_PREP(LTC4282_ILIM_ADJUST_MASK, reg_val)); 1427 if (ret) 1428 return ret; 1429 } 1430 1431 ret = ltc4282_set_max_limits(st); 1432 if (ret) 1433 return ret; 1434 1435 ret = device_property_read_string(dev, "adi,overvoltage-dividers", 1436 ÷r); 1437 if (!ret) { 1438 int div = match_string(ltc4282_dividers, 1439 ARRAY_SIZE(ltc4282_dividers), divider); 1440 if (div < 0) 1441 return dev_err_probe(dev, -EINVAL, 1442 "Invalid val(%s) for adi,overvoltage-divider\n", 1443 divider); 1444 1445 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1446 LTC4282_CTRL_OV_MODE_MASK, 1447 FIELD_PREP(LTC4282_CTRL_OV_MODE_MASK, div)); 1448 } 1449 1450 ret = device_property_read_string(dev, "adi,undervoltage-dividers", 1451 ÷r); 1452 if (!ret) { 1453 int div = match_string(ltc4282_dividers, 1454 ARRAY_SIZE(ltc4282_dividers), divider); 1455 if (div < 0) 1456 return dev_err_probe(dev, -EINVAL, 1457 "Invalid val(%s) for adi,undervoltage-divider\n", 1458 divider); 1459 1460 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1461 LTC4282_CTRL_UV_MODE_MASK, 1462 FIELD_PREP(LTC4282_CTRL_UV_MODE_MASK, div)); 1463 } 1464 1465 if (device_property_read_bool(dev, "adi,overcurrent-retry")) { 1466 ret = regmap_set_bits(st->map, LTC4282_CTRL_LSB, 1467 LTC4282_CTRL_OC_RETRY_MASK); 1468 if (ret) 1469 return ret; 1470 } 1471 1472 if (device_property_read_bool(dev, "adi,overvoltage-retry-disable")) { 1473 ret = regmap_clear_bits(st->map, LTC4282_CTRL_LSB, 1474 LTC4282_CTRL_OV_RETRY_MASK); 1475 if (ret) 1476 return ret; 1477 } 1478 1479 if (device_property_read_bool(dev, "adi,undervoltage-retry-disable")) { 1480 ret = regmap_clear_bits(st->map, LTC4282_CTRL_LSB, 1481 LTC4282_CTRL_UV_RETRY_MASK); 1482 if (ret) 1483 return ret; 1484 } 1485 1486 if (device_property_read_bool(dev, "adi,fault-log-enable")) { 1487 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_FAULT_LOG_EN_MASK); 1488 if (ret) 1489 return ret; 1490 } 1491 1492 ret = device_property_read_u32(dev, "adi,fet-bad-timeout-ms", &val); 1493 if (!ret) { 1494 if (val > LTC4282_FET_BAD_MAX_TIMEOUT) 1495 return dev_err_probe(dev, -EINVAL, 1496 "Invalid value(%u) for adi,fet-bad-timeout-ms", 1497 val); 1498 1499 ret = regmap_write(st->map, LTC4282_FET_BAD_FAULT_TIMEOUT, val); 1500 if (ret) 1501 return ret; 1502 } 1503 1504 return ltc4282_gpio_setup(st, dev); 1505 } 1506 1507 static bool ltc4282_readable_reg(struct device *dev, unsigned int reg) 1508 { 1509 if (reg == LTC4282_RESERVED_1 || reg == LTC4282_RESERVED_2) 1510 return false; 1511 1512 return true; 1513 } 1514 1515 static bool ltc4282_writable_reg(struct device *dev, unsigned int reg) 1516 { 1517 if (reg == LTC4282_STATUS_LSB || reg == LTC4282_STATUS_MSB) 1518 return false; 1519 if (reg == LTC4282_RESERVED_1 || reg == LTC4282_RESERVED_2) 1520 return false; 1521 1522 return true; 1523 } 1524 1525 static const struct regmap_config ltc4282_regmap_config = { 1526 .reg_bits = 8, 1527 .val_bits = 8, 1528 .max_register = LTC4282_RESERVED_3, 1529 .readable_reg = ltc4282_readable_reg, 1530 .writeable_reg = ltc4282_writable_reg, 1531 }; 1532 1533 static const struct hwmon_channel_info * const ltc4282_info[] = { 1534 HWMON_CHANNEL_INFO(in, 1535 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1536 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1537 HWMON_I_MAX_ALARM | HWMON_I_ENABLE | 1538 HWMON_I_RESET_HISTORY | HWMON_I_FAULT | 1539 HWMON_I_LABEL, 1540 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1541 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1542 HWMON_I_MAX_ALARM | HWMON_I_LCRIT_ALARM | 1543 HWMON_I_CRIT_ALARM | HWMON_I_ENABLE | 1544 HWMON_I_RESET_HISTORY | HWMON_I_LABEL, 1545 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1546 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1547 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1548 HWMON_I_LABEL), 1549 HWMON_CHANNEL_INFO(curr, 1550 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | 1551 HWMON_C_MAX | HWMON_C_MIN | HWMON_C_MIN_ALARM | 1552 HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM | 1553 HWMON_C_RESET_HISTORY | HWMON_C_LABEL), 1554 HWMON_CHANNEL_INFO(power, 1555 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | 1556 HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN | 1557 HWMON_P_MAX_ALARM | HWMON_P_MIN_ALARM | 1558 HWMON_P_RESET_HISTORY | HWMON_P_LABEL), 1559 HWMON_CHANNEL_INFO(energy, 1560 HWMON_E_ENABLE), 1561 HWMON_CHANNEL_INFO(energy64, 1562 HWMON_E_INPUT), 1563 NULL 1564 }; 1565 1566 static const struct hwmon_ops ltc4282_hwmon_ops = { 1567 .read = ltc4282_read, 1568 .write = ltc4282_write, 1569 .is_visible = ltc4282_is_visible, 1570 .read_string = ltc4282_read_labels, 1571 }; 1572 1573 static const struct hwmon_chip_info ltc4282_chip_info = { 1574 .ops = <c4282_hwmon_ops, 1575 .info = ltc4282_info, 1576 }; 1577 1578 static int ltc4282_show_fault_log(void *arg, u64 *val, u32 mask) 1579 { 1580 struct ltc4282_state *st = arg; 1581 long alarm; 1582 int ret; 1583 1584 ret = ltc4282_read_alarm(st, LTC4282_FAULT_LOG, mask, &alarm); 1585 if (ret) 1586 return ret; 1587 1588 *val = alarm; 1589 1590 return 0; 1591 } 1592 1593 static int ltc4282_show_curr1_crit_fault_log(void *arg, u64 *val) 1594 { 1595 return ltc4282_show_fault_log(arg, val, LTC4282_OC_FAULT_MASK); 1596 } 1597 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_curr1_crit_fault_log, 1598 ltc4282_show_curr1_crit_fault_log, NULL, "%llu\n"); 1599 1600 static int ltc4282_show_in1_lcrit_fault_log(void *arg, u64 *val) 1601 { 1602 return ltc4282_show_fault_log(arg, val, LTC4282_UV_FAULT_MASK); 1603 } 1604 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_in1_lcrit_fault_log, 1605 ltc4282_show_in1_lcrit_fault_log, NULL, "%llu\n"); 1606 1607 static int ltc4282_show_in1_crit_fault_log(void *arg, u64 *val) 1608 { 1609 return ltc4282_show_fault_log(arg, val, LTC4282_OV_FAULT_MASK); 1610 } 1611 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_in1_crit_fault_log, 1612 ltc4282_show_in1_crit_fault_log, NULL, "%llu\n"); 1613 1614 static int ltc4282_show_fet_bad_fault_log(void *arg, u64 *val) 1615 { 1616 return ltc4282_show_fault_log(arg, val, LTC4282_FET_BAD_FAULT_MASK); 1617 } 1618 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_fet_bad_fault_log, 1619 ltc4282_show_fet_bad_fault_log, NULL, "%llu\n"); 1620 1621 static int ltc4282_show_fet_short_fault_log(void *arg, u64 *val) 1622 { 1623 return ltc4282_show_fault_log(arg, val, LTC4282_FET_SHORT_FAULT_MASK); 1624 } 1625 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_fet_short_fault_log, 1626 ltc4282_show_fet_short_fault_log, NULL, "%llu\n"); 1627 1628 static int ltc4282_show_power1_bad_fault_log(void *arg, u64 *val) 1629 { 1630 return ltc4282_show_fault_log(arg, val, LTC4282_POWER_BAD_FAULT_MASK); 1631 } 1632 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_power1_bad_fault_log, 1633 ltc4282_show_power1_bad_fault_log, NULL, "%llu\n"); 1634 1635 static void ltc4282_debugfs_init(struct ltc4282_state *st, struct i2c_client *i2c) 1636 { 1637 debugfs_create_file_unsafe("power1_bad_fault_log", 0400, i2c->debugfs, st, 1638 <c4282_power1_bad_fault_log); 1639 debugfs_create_file_unsafe("in0_fet_short_fault_log", 0400, i2c->debugfs, st, 1640 <c4282_fet_short_fault_log); 1641 debugfs_create_file_unsafe("in0_fet_bad_fault_log", 0400, i2c->debugfs, st, 1642 <c4282_fet_bad_fault_log); 1643 debugfs_create_file_unsafe("in1_crit_fault_log", 0400, i2c->debugfs, st, 1644 <c4282_in1_crit_fault_log); 1645 debugfs_create_file_unsafe("in1_lcrit_fault_log", 0400, i2c->debugfs, st, 1646 <c4282_in1_lcrit_fault_log); 1647 debugfs_create_file_unsafe("curr1_crit_fault_log", 0400, i2c->debugfs, st, 1648 <c4282_curr1_crit_fault_log); 1649 } 1650 1651 static int ltc4282_probe(struct i2c_client *i2c) 1652 { 1653 struct device *dev = &i2c->dev, *hwmon; 1654 struct ltc4282_state *st; 1655 int ret; 1656 1657 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 1658 if (!st) 1659 return -ENOMEM; 1660 1661 st->map = devm_regmap_init_i2c(i2c, <c4282_regmap_config); 1662 if (IS_ERR(st->map)) 1663 return dev_err_probe(dev, PTR_ERR(st->map), 1664 "failed regmap init\n"); 1665 1666 /* Soft reset */ 1667 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_RESET_MASK); 1668 if (ret) 1669 return ret; 1670 1671 /* Yes, it's big but it is as specified in the datasheet */ 1672 msleep(3200); 1673 1674 ret = ltc428_clks_setup(st, dev); 1675 if (ret) 1676 return ret; 1677 1678 ret = ltc4282_setup(st, dev); 1679 if (ret) 1680 return ret; 1681 1682 hwmon = devm_hwmon_device_register_with_info(dev, "ltc4282", st, 1683 <c4282_chip_info, NULL); 1684 if (IS_ERR(hwmon)) 1685 return PTR_ERR(hwmon); 1686 1687 ltc4282_debugfs_init(st, i2c); 1688 1689 return 0; 1690 } 1691 1692 static const struct of_device_id ltc4282_of_match[] = { 1693 { .compatible = "adi,ltc4282" }, 1694 {} 1695 }; 1696 MODULE_DEVICE_TABLE(of, ltc4282_of_match); 1697 1698 static struct i2c_driver ltc4282_driver = { 1699 .driver = { 1700 .name = "ltc4282", 1701 .of_match_table = ltc4282_of_match, 1702 }, 1703 .probe = ltc4282_probe, 1704 }; 1705 module_i2c_driver(ltc4282_driver); 1706 1707 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1708 MODULE_DESCRIPTION("LTC4282 I2C High Current Hot Swap Controller"); 1709 MODULE_LICENSE("GPL"); 1710