1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C 4 * 5 * Copyright 2023 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/cleanup.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/hwmon.h> 15 #include <linux/i2c.h> 16 #include <linux/math.h> 17 #include <linux/minmax.h> 18 #include <linux/module.h> 19 #include <linux/regmap.h> 20 #include <linux/property.h> 21 #include <linux/string.h> 22 #include <linux/units.h> 23 #include <linux/util_macros.h> 24 25 #define LTC4282_CTRL_LSB 0x00 26 #define LTC4282_CTRL_OV_RETRY_MASK BIT(0) 27 #define LTC4282_CTRL_UV_RETRY_MASK BIT(1) 28 #define LTC4282_CTRL_OC_RETRY_MASK BIT(2) 29 #define LTC4282_CTRL_ON_ACTIVE_LOW_MASK BIT(5) 30 #define LTC4282_CTRL_ON_DELAY_MASK BIT(6) 31 #define LTC4282_CTRL_MSB 0x01 32 #define LTC4282_CTRL_VIN_MODE_MASK GENMASK(1, 0) 33 #define LTC4282_CTRL_OV_MODE_MASK GENMASK(3, 2) 34 #define LTC4282_CTRL_UV_MODE_MASK GENMASK(5, 4) 35 #define LTC4282_FAULT_LOG 0x04 36 #define LTC4282_OV_FAULT_MASK BIT(0) 37 #define LTC4282_UV_FAULT_MASK BIT(1) 38 #define LTC4282_VDD_FAULT_MASK \ 39 (LTC4282_OV_FAULT_MASK | LTC4282_UV_FAULT_MASK) 40 #define LTC4282_OC_FAULT_MASK BIT(2) 41 #define LTC4282_POWER_BAD_FAULT_MASK BIT(3) 42 #define LTC4282_FET_SHORT_FAULT_MASK BIT(5) 43 #define LTC4282_FET_BAD_FAULT_MASK BIT(6) 44 #define LTC4282_FET_FAILURE_FAULT_MASK \ 45 (LTC4282_FET_SHORT_FAULT_MASK | LTC4282_FET_BAD_FAULT_MASK) 46 #define LTC4282_ADC_ALERT_LOG 0x05 47 #define LTC4282_GPIO_ALARM_L_MASK BIT(0) 48 #define LTC4282_GPIO_ALARM_H_MASK BIT(1) 49 #define LTC4282_VSOURCE_ALARM_L_MASK BIT(2) 50 #define LTC4282_VSOURCE_ALARM_H_MASK BIT(3) 51 #define LTC4282_VSENSE_ALARM_L_MASK BIT(4) 52 #define LTC4282_VSENSE_ALARM_H_MASK BIT(5) 53 #define LTC4282_POWER_ALARM_L_MASK BIT(6) 54 #define LTC4282_POWER_ALARM_H_MASK BIT(7) 55 #define LTC4282_FET_BAD_FAULT_TIMEOUT 0x06 56 #define LTC4282_FET_BAD_MAX_TIMEOUT 255 57 #define LTC4282_GPIO_CONFIG 0x07 58 #define LTC4282_GPIO_2_FET_STRESS_MASK BIT(1) 59 #define LTC4282_GPIO_1_CONFIG_MASK GENMASK(5, 4) 60 #define LTC4282_VGPIO_MIN 0x08 61 #define LTC4282_VGPIO_MAX 0x09 62 #define LTC4282_VSOURCE_MIN 0x0a 63 #define LTC4282_VSOURCE_MAX 0x0b 64 #define LTC4282_VSENSE_MIN 0x0c 65 #define LTC4282_VSENSE_MAX 0x0d 66 #define LTC4282_POWER_MIN 0x0e 67 #define LTC4282_POWER_MAX 0x0f 68 #define LTC4282_CLK_DIV 0x10 69 #define LTC4282_CLK_DIV_MASK GENMASK(4, 0) 70 #define LTC4282_CLKOUT_MASK GENMASK(6, 5) 71 #define LTC4282_ILIM_ADJUST 0x11 72 #define LTC4282_GPIO_MODE_MASK BIT(1) 73 #define LTC4282_VDD_MONITOR_MASK BIT(2) 74 #define LTC4282_FOLDBACK_MODE_MASK GENMASK(4, 3) 75 #define LTC4282_ILIM_ADJUST_MASK GENMASK(7, 5) 76 #define LTC4282_ENERGY 0x12 77 #define LTC4282_TIME_COUNTER 0x18 78 #define LTC4282_ALERT_CTRL 0x1c 79 #define LTC4282_ALERT_OUT_MASK BIT(6) 80 #define LTC4282_ADC_CTRL 0x1d 81 #define LTC4282_FAULT_LOG_EN_MASK BIT(2) 82 #define LTC4282_METER_HALT_MASK BIT(5) 83 #define LTC4282_METER_RESET_MASK BIT(6) 84 #define LTC4282_RESET_MASK BIT(7) 85 #define LTC4282_STATUS_LSB 0x1e 86 #define LTC4282_OV_STATUS_MASK BIT(0) 87 #define LTC4282_UV_STATUS_MASK BIT(1) 88 #define LTC4282_VDD_STATUS_MASK \ 89 (LTC4282_OV_STATUS_MASK | LTC4282_UV_STATUS_MASK) 90 #define LTC4282_OC_STATUS_MASK BIT(2) 91 #define LTC4282_POWER_GOOD_MASK BIT(3) 92 #define LTC4282_FET_FAILURE_MASK GENMASK(6, 5) 93 #define LTC4282_STATUS_MSB 0x1f 94 #define LTC4282_RESERVED_1 0x32 95 #define LTC4282_RESERVED_2 0x33 96 #define LTC4282_VGPIO 0x34 97 #define LTC4282_VGPIO_LOWEST 0x36 98 #define LTC4282_VGPIO_HIGHEST 0x38 99 #define LTC4282_VSOURCE 0x3a 100 #define LTC4282_VSOURCE_LOWEST 0x3c 101 #define LTC4282_VSOURCE_HIGHEST 0x3e 102 #define LTC4282_VSENSE 0x40 103 #define LTC4282_VSENSE_LOWEST 0x42 104 #define LTC4282_VSENSE_HIGHEST 0x44 105 #define LTC4282_POWER 0x46 106 #define LTC4282_POWER_LOWEST 0x48 107 #define LTC4282_POWER_HIGHEST 0x4a 108 #define LTC4282_RESERVED_3 0x50 109 110 #define LTC4282_CLKIN_MIN (250 * KILO) 111 #define LTC4282_CLKIN_MAX (15500 * KILO) 112 #define LTC4282_CLKIN_RANGE (LTC4282_CLKIN_MAX - LTC4282_CLKIN_MIN + 1) 113 #define LTC4282_CLKOUT_SYSTEM (250 * KILO) 114 #define LTC4282_CLKOUT_CNV 15 115 116 enum { 117 LTC4282_CHAN_VSOURCE, 118 LTC4282_CHAN_VDD, 119 LTC4282_CHAN_VGPIO, 120 }; 121 122 struct ltc4282_cache { 123 u32 in_max_raw; 124 u32 in_min_raw; 125 long in_highest; 126 long in_lowest; 127 bool en; 128 }; 129 130 struct ltc4282_state { 131 struct regmap *map; 132 struct clk_hw clk_hw; 133 /* 134 * Used to cache values for VDD/VSOURCE depending which will be used 135 * when hwmon is not enabled for that channel. Needed because they share 136 * the same registers. 137 */ 138 struct ltc4282_cache in0_1_cache[LTC4282_CHAN_VGPIO]; 139 u32 vsense_max; 140 long power_max; 141 u32 rsense; 142 u16 vdd; 143 u16 vfs_out; 144 bool energy_en; 145 }; 146 147 enum { 148 LTC4282_CLKOUT_NONE, 149 LTC4282_CLKOUT_INT, 150 LTC4282_CLKOUT_TICK, 151 }; 152 153 static int ltc4282_set_rate(struct clk_hw *hw, 154 unsigned long rate, unsigned long parent_rate) 155 { 156 struct ltc4282_state *st = container_of(hw, struct ltc4282_state, 157 clk_hw); 158 u32 val = LTC4282_CLKOUT_INT; 159 160 if (rate == LTC4282_CLKOUT_CNV) 161 val = LTC4282_CLKOUT_TICK; 162 163 return regmap_update_bits(st->map, LTC4282_CLK_DIV, LTC4282_CLKOUT_MASK, 164 FIELD_PREP(LTC4282_CLKOUT_MASK, val)); 165 } 166 167 /* 168 * Note the 15HZ conversion rate assumes 12bit ADC which is what we are 169 * supporting for now. 170 */ 171 static const unsigned int ltc4282_out_rates[] = { 172 LTC4282_CLKOUT_CNV, LTC4282_CLKOUT_SYSTEM 173 }; 174 175 static int ltc4282_determine_rate(struct clk_hw *hw, 176 struct clk_rate_request *req) 177 { 178 int idx = find_closest(req->rate, ltc4282_out_rates, 179 ARRAY_SIZE(ltc4282_out_rates)); 180 181 req->rate = ltc4282_out_rates[idx]; 182 183 return 0; 184 } 185 186 static unsigned long ltc4282_recalc_rate(struct clk_hw *hw, 187 unsigned long parent) 188 { 189 struct ltc4282_state *st = container_of(hw, struct ltc4282_state, 190 clk_hw); 191 u32 clkdiv; 192 int ret; 193 194 ret = regmap_read(st->map, LTC4282_CLK_DIV, &clkdiv); 195 if (ret) 196 return 0; 197 198 clkdiv = FIELD_GET(LTC4282_CLKOUT_MASK, clkdiv); 199 if (!clkdiv) 200 return 0; 201 if (clkdiv == LTC4282_CLKOUT_INT) 202 return LTC4282_CLKOUT_SYSTEM; 203 204 return LTC4282_CLKOUT_CNV; 205 } 206 207 static void ltc4282_disable(struct clk_hw *clk_hw) 208 { 209 struct ltc4282_state *st = container_of(clk_hw, struct ltc4282_state, 210 clk_hw); 211 212 regmap_clear_bits(st->map, LTC4282_CLK_DIV, LTC4282_CLKOUT_MASK); 213 } 214 215 static int ltc4282_read_voltage_word(const struct ltc4282_state *st, u32 reg, 216 u32 fs, long *val) 217 { 218 __be16 in; 219 int ret; 220 221 ret = regmap_bulk_read(st->map, reg, &in, sizeof(in)); 222 if (ret) 223 return ret; 224 225 /* 226 * This is also used to calculate current in which case fs comes in 227 * 10 * uV. Hence the ULL usage. 228 */ 229 *val = DIV_ROUND_CLOSEST_ULL(be16_to_cpu(in) * (u64)fs, U16_MAX); 230 return 0; 231 } 232 233 static int ltc4282_read_voltage_byte_cached(const struct ltc4282_state *st, 234 u32 reg, u32 fs, long *val, 235 u32 *cached_raw) 236 { 237 int ret; 238 u32 in; 239 240 if (cached_raw) { 241 in = *cached_raw; 242 } else { 243 ret = regmap_read(st->map, reg, &in); 244 if (ret) 245 return ret; 246 } 247 248 *val = DIV_ROUND_CLOSEST(in * fs, U8_MAX); 249 return 0; 250 } 251 252 static int ltc4282_read_voltage_byte(const struct ltc4282_state *st, u32 reg, 253 u32 fs, long *val) 254 { 255 return ltc4282_read_voltage_byte_cached(st, reg, fs, val, NULL); 256 } 257 258 static int __ltc4282_read_alarm(struct ltc4282_state *st, u32 reg, u32 mask, 259 long *val) 260 { 261 u32 alarm; 262 int ret; 263 264 ret = regmap_read(st->map, reg, &alarm); 265 if (ret) 266 return ret; 267 268 *val = !!(alarm & mask); 269 270 /* if not status/fault logs, clear the alarm after reading it */ 271 if (reg != LTC4282_STATUS_LSB && reg != LTC4282_FAULT_LOG) 272 return regmap_clear_bits(st->map, reg, mask); 273 274 return 0; 275 } 276 277 static int ltc4282_read_alarm(struct ltc4282_state *st, u32 reg, u32 mask, 278 long *val) 279 { 280 return __ltc4282_read_alarm(st, reg, mask, val); 281 } 282 283 static int ltc4282_vdd_source_read_in(struct ltc4282_state *st, u32 channel, 284 long *val) 285 { 286 if (!st->in0_1_cache[channel].en) 287 return -ENODATA; 288 289 return ltc4282_read_voltage_word(st, LTC4282_VSOURCE, st->vfs_out, val); 290 } 291 292 static int ltc4282_vdd_source_read_hist(struct ltc4282_state *st, u32 reg, 293 u32 channel, long *cached, long *val) 294 { 295 int ret; 296 297 if (!st->in0_1_cache[channel].en) { 298 *val = *cached; 299 return 0; 300 } 301 302 ret = ltc4282_read_voltage_word(st, reg, st->vfs_out, val); 303 if (ret) 304 return ret; 305 306 *cached = *val; 307 return 0; 308 } 309 310 static int ltc4282_vdd_source_read_lim(struct ltc4282_state *st, u32 reg, 311 u32 channel, u32 *cached, long *val) 312 { 313 if (!st->in0_1_cache[channel].en) 314 return ltc4282_read_voltage_byte_cached(st, reg, st->vfs_out, 315 val, cached); 316 317 return ltc4282_read_voltage_byte(st, reg, st->vfs_out, val); 318 } 319 320 static int ltc4282_vdd_source_read_alm(struct ltc4282_state *st, u32 mask, 321 u32 channel, long *val) 322 { 323 if (!st->in0_1_cache[channel].en) { 324 /* 325 * Do this otherwise alarms can get confused because we clear 326 * them after reading them. So, if someone mistakenly reads 327 * VSOURCE right before VDD (or the other way around), we might 328 * get no alarm just because it was cleared when reading VSOURCE 329 * and had no time for a new conversion and thus having the 330 * alarm again. 331 */ 332 *val = 0; 333 return 0; 334 } 335 336 return __ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, mask, val); 337 } 338 339 static int ltc4282_read_in(struct ltc4282_state *st, u32 attr, long *val, 340 u32 channel) 341 { 342 switch (attr) { 343 case hwmon_in_input: 344 if (channel == LTC4282_CHAN_VGPIO) 345 return ltc4282_read_voltage_word(st, LTC4282_VGPIO, 346 1280, val); 347 348 return ltc4282_vdd_source_read_in(st, channel, val); 349 case hwmon_in_highest: 350 if (channel == LTC4282_CHAN_VGPIO) 351 return ltc4282_read_voltage_word(st, 352 LTC4282_VGPIO_HIGHEST, 353 1280, val); 354 355 return ltc4282_vdd_source_read_hist(st, LTC4282_VSOURCE_HIGHEST, 356 channel, 357 &st->in0_1_cache[channel].in_highest, val); 358 case hwmon_in_lowest: 359 if (channel == LTC4282_CHAN_VGPIO) 360 return ltc4282_read_voltage_word(st, LTC4282_VGPIO_LOWEST, 361 1280, val); 362 363 return ltc4282_vdd_source_read_hist(st, LTC4282_VSOURCE_LOWEST, 364 channel, 365 &st->in0_1_cache[channel].in_lowest, val); 366 case hwmon_in_max_alarm: 367 if (channel == LTC4282_CHAN_VGPIO) 368 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 369 LTC4282_GPIO_ALARM_H_MASK, 370 val); 371 372 return ltc4282_vdd_source_read_alm(st, 373 LTC4282_VSOURCE_ALARM_H_MASK, 374 channel, val); 375 case hwmon_in_min_alarm: 376 if (channel == LTC4282_CHAN_VGPIO) 377 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 378 LTC4282_GPIO_ALARM_L_MASK, val); 379 380 return ltc4282_vdd_source_read_alm(st, 381 LTC4282_VSOURCE_ALARM_L_MASK, 382 channel, val); 383 case hwmon_in_crit_alarm: 384 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 385 LTC4282_OV_STATUS_MASK, val); 386 case hwmon_in_lcrit_alarm: 387 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 388 LTC4282_UV_STATUS_MASK, val); 389 case hwmon_in_max: 390 if (channel == LTC4282_CHAN_VGPIO) 391 return ltc4282_read_voltage_byte(st, LTC4282_VGPIO_MAX, 392 1280, val); 393 394 return ltc4282_vdd_source_read_lim(st, LTC4282_VSOURCE_MAX, 395 channel, 396 &st->in0_1_cache[channel].in_max_raw, val); 397 case hwmon_in_min: 398 if (channel == LTC4282_CHAN_VGPIO) 399 return ltc4282_read_voltage_byte(st, LTC4282_VGPIO_MIN, 400 1280, val); 401 402 return ltc4282_vdd_source_read_lim(st, LTC4282_VSOURCE_MIN, 403 channel, 404 &st->in0_1_cache[channel].in_min_raw, val); 405 case hwmon_in_enable: 406 *val = st->in0_1_cache[channel].en; 407 return 0; 408 case hwmon_in_fault: 409 /* 410 * We report failure if we detect either a fer_bad or a 411 * fet_short in the status register. 412 */ 413 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 414 LTC4282_FET_FAILURE_MASK, val); 415 default: 416 return -EOPNOTSUPP; 417 } 418 } 419 420 static int ltc4282_read_current_word(const struct ltc4282_state *st, u32 reg, 421 long *val) 422 { 423 long in; 424 int ret; 425 426 /* 427 * We pass in full scale in 10 * micro (note that 40 is already 428 * millivolt) so we have better approximations to calculate current. 429 */ 430 ret = ltc4282_read_voltage_word(st, reg, DECA * 40 * MILLI, &in); 431 if (ret) 432 return ret; 433 434 *val = DIV_ROUND_CLOSEST(in * MILLI, st->rsense); 435 436 return 0; 437 } 438 439 static int ltc4282_read_current_byte(const struct ltc4282_state *st, u32 reg, 440 long *val) 441 { 442 long in; 443 int ret; 444 445 ret = ltc4282_read_voltage_byte(st, reg, DECA * 40 * MILLI, &in); 446 if (ret) 447 return ret; 448 449 *val = DIV_ROUND_CLOSEST(in * MILLI, st->rsense); 450 451 return 0; 452 } 453 454 static int ltc4282_read_curr(struct ltc4282_state *st, const u32 attr, 455 long *val) 456 { 457 switch (attr) { 458 case hwmon_curr_input: 459 return ltc4282_read_current_word(st, LTC4282_VSENSE, val); 460 case hwmon_curr_highest: 461 return ltc4282_read_current_word(st, LTC4282_VSENSE_HIGHEST, 462 val); 463 case hwmon_curr_lowest: 464 return ltc4282_read_current_word(st, LTC4282_VSENSE_LOWEST, 465 val); 466 case hwmon_curr_max: 467 return ltc4282_read_current_byte(st, LTC4282_VSENSE_MAX, val); 468 case hwmon_curr_min: 469 return ltc4282_read_current_byte(st, LTC4282_VSENSE_MIN, val); 470 case hwmon_curr_max_alarm: 471 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 472 LTC4282_VSENSE_ALARM_H_MASK, val); 473 case hwmon_curr_min_alarm: 474 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 475 LTC4282_VSENSE_ALARM_L_MASK, val); 476 case hwmon_curr_crit_alarm: 477 return ltc4282_read_alarm(st, LTC4282_STATUS_LSB, 478 LTC4282_OC_STATUS_MASK, val); 479 default: 480 return -EOPNOTSUPP; 481 } 482 } 483 484 static int ltc4282_read_power_word(const struct ltc4282_state *st, u32 reg, 485 long *val) 486 { 487 u64 temp = DECA * 40ULL * st->vfs_out * BIT(16), temp_2; 488 __be16 raw; 489 u16 power; 490 int ret; 491 492 ret = regmap_bulk_read(st->map, reg, &raw, sizeof(raw)); 493 if (ret) 494 return ret; 495 496 power = be16_to_cpu(raw); 497 /* 498 * Power is given by: 499 * P = CODE(16b) * 0.040 * Vfs(out) * 2^16 / ((2^16 - 1)^2 * Rsense) 500 */ 501 if (check_mul_overflow(power * temp, MICRO, &temp_2)) { 502 temp = DIV_ROUND_CLOSEST_ULL(power * temp, U16_MAX); 503 *val = DIV64_U64_ROUND_CLOSEST(temp * MICRO, 504 U16_MAX * (u64)st->rsense); 505 return 0; 506 } 507 508 *val = DIV64_U64_ROUND_CLOSEST(temp_2, 509 st->rsense * int_pow(U16_MAX, 2)); 510 511 return 0; 512 } 513 514 static int ltc4282_read_power_byte(const struct ltc4282_state *st, u32 reg, 515 long *val) 516 { 517 u32 power; 518 u64 temp; 519 int ret; 520 521 ret = regmap_read(st->map, reg, &power); 522 if (ret) 523 return ret; 524 525 temp = power * 40 * DECA * st->vfs_out * BIT_ULL(8); 526 *val = DIV64_U64_ROUND_CLOSEST(temp * MICRO, 527 int_pow(U8_MAX, 2) * st->rsense); 528 529 return 0; 530 } 531 532 static int ltc4282_read_energy(const struct ltc4282_state *st, s64 *val) 533 { 534 u64 temp, energy; 535 __be64 raw; 536 int ret; 537 538 ret = regmap_bulk_read(st->map, LTC4282_ENERGY, &raw, 6); 539 if (ret) 540 return ret; 541 542 energy = be64_to_cpu(raw) >> 16; 543 /* 544 * The formula for energy is given by: 545 * E = CODE(48b) * 0.040 * Vfs(out) * Tconv * 256 / 546 * ((2^16 - 1)^2 * Rsense) 547 * 548 * Since we only support 12bit ADC, Tconv = 0.065535s. Passing Vfs(out) 549 * and 0.040 to mV and Tconv to us, we can simplify the formula to: 550 * E = CODE(48b) * 40 * Vfs(out) * 256 / (U16_MAX * Rsense) 551 * 552 * As Rsense can have tenths of micro-ohm resolution, we need to 553 * multiply by DECA to get microujoule. 554 */ 555 if (check_mul_overflow(DECA * st->vfs_out * 40 * BIT(8), energy, &temp)) { 556 temp = DIV_ROUND_CLOSEST(DECA * st->vfs_out * 40 * BIT(8), U16_MAX); 557 *val = DIV_ROUND_CLOSEST_ULL(temp * energy, st->rsense); 558 return 0; 559 } 560 561 *val = DIV64_U64_ROUND_CLOSEST(temp, U16_MAX * (u64)st->rsense); 562 563 return 0; 564 } 565 566 static int ltc4282_read_power(struct ltc4282_state *st, const u32 attr, 567 long *val) 568 { 569 switch (attr) { 570 case hwmon_power_input: 571 return ltc4282_read_power_word(st, LTC4282_POWER, val); 572 case hwmon_power_input_highest: 573 return ltc4282_read_power_word(st, LTC4282_POWER_HIGHEST, val); 574 case hwmon_power_input_lowest: 575 return ltc4282_read_power_word(st, LTC4282_POWER_LOWEST, val); 576 case hwmon_power_max_alarm: 577 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 578 LTC4282_POWER_ALARM_H_MASK, val); 579 case hwmon_power_min_alarm: 580 return ltc4282_read_alarm(st, LTC4282_ADC_ALERT_LOG, 581 LTC4282_POWER_ALARM_L_MASK, val); 582 case hwmon_power_max: 583 return ltc4282_read_power_byte(st, LTC4282_POWER_MAX, val); 584 case hwmon_power_min: 585 return ltc4282_read_power_byte(st, LTC4282_POWER_MIN, val); 586 default: 587 return -EOPNOTSUPP; 588 } 589 } 590 591 static int ltc4282_read(struct device *dev, enum hwmon_sensor_types type, 592 u32 attr, int channel, long *val) 593 { 594 struct ltc4282_state *st = dev_get_drvdata(dev); 595 596 switch (type) { 597 case hwmon_in: 598 return ltc4282_read_in(st, attr, val, channel); 599 case hwmon_curr: 600 return ltc4282_read_curr(st, attr, val); 601 case hwmon_power: 602 return ltc4282_read_power(st, attr, val); 603 case hwmon_energy: 604 *val = st->energy_en; 605 return 0; 606 case hwmon_energy64: 607 if (st->energy_en) 608 return ltc4282_read_energy(st, (s64 *)val); 609 return -ENODATA; 610 default: 611 return -EOPNOTSUPP; 612 } 613 } 614 615 static int ltc4282_write_power_byte(const struct ltc4282_state *st, u32 reg, 616 long val) 617 { 618 u32 power; 619 u64 temp; 620 621 if (val > st->power_max) 622 val = st->power_max; 623 624 temp = val * int_pow(U8_MAX, 2) * st->rsense; 625 power = DIV64_U64_ROUND_CLOSEST(temp, 626 MICRO * DECA * 256ULL * st->vfs_out * 40); 627 628 return regmap_write(st->map, reg, power); 629 } 630 631 static int ltc4282_write_power_word(const struct ltc4282_state *st, u32 reg, 632 long val) 633 { 634 u64 temp = int_pow(U16_MAX, 2) * st->rsense, temp_2; 635 __be16 __raw; 636 u16 code; 637 638 if (check_mul_overflow(temp, val, &temp_2)) { 639 temp = DIV_ROUND_CLOSEST_ULL(temp, DECA * MICRO); 640 code = DIV64_U64_ROUND_CLOSEST(temp * val, 641 40ULL * BIT(16) * st->vfs_out); 642 } else { 643 temp = DECA * MICRO * 40ULL * BIT(16) * st->vfs_out; 644 code = DIV64_U64_ROUND_CLOSEST(temp_2, temp); 645 } 646 647 __raw = cpu_to_be16(code); 648 return regmap_bulk_write(st->map, reg, &__raw, sizeof(__raw)); 649 } 650 651 static int __ltc4282_in_write_history(const struct ltc4282_state *st, u32 reg, 652 long lowest, long highest, u32 fs) 653 { 654 __be16 __raw; 655 u16 tmp; 656 int ret; 657 658 tmp = DIV_ROUND_CLOSEST(U16_MAX * lowest, fs); 659 660 __raw = cpu_to_be16(tmp); 661 662 ret = regmap_bulk_write(st->map, reg, &__raw, 2); 663 if (ret) 664 return ret; 665 666 tmp = DIV_ROUND_CLOSEST(U16_MAX * highest, fs); 667 668 __raw = cpu_to_be16(tmp); 669 670 return regmap_bulk_write(st->map, reg + 2, &__raw, 2); 671 } 672 673 static int ltc4282_in_write_history(struct ltc4282_state *st, u32 reg, 674 long lowest, long highest, u32 fs) 675 { 676 return __ltc4282_in_write_history(st, reg, lowest, highest, fs); 677 } 678 679 static int ltc4282_power_reset_hist(struct ltc4282_state *st) 680 { 681 int ret; 682 683 ret = ltc4282_write_power_word(st, LTC4282_POWER_LOWEST, 684 st->power_max); 685 if (ret) 686 return ret; 687 688 ret = ltc4282_write_power_word(st, LTC4282_POWER_HIGHEST, 0); 689 if (ret) 690 return ret; 691 692 /* now, let's also clear possible power_bad fault logs */ 693 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 694 LTC4282_POWER_BAD_FAULT_MASK); 695 } 696 697 static int ltc4282_write_power(struct ltc4282_state *st, u32 attr, 698 long val) 699 { 700 switch (attr) { 701 case hwmon_power_max: 702 return ltc4282_write_power_byte(st, LTC4282_POWER_MAX, val); 703 case hwmon_power_min: 704 return ltc4282_write_power_byte(st, LTC4282_POWER_MIN, val); 705 case hwmon_power_reset_history: 706 return ltc4282_power_reset_hist(st); 707 default: 708 return -EOPNOTSUPP; 709 } 710 } 711 712 static int ltc4282_write_voltage_byte_cached(const struct ltc4282_state *st, 713 u32 reg, u32 fs, long val, 714 u32 *cache_raw) 715 { 716 u32 in; 717 718 val = clamp_val(val, 0, fs); 719 in = DIV_ROUND_CLOSEST(val * U8_MAX, fs); 720 721 if (cache_raw) { 722 *cache_raw = in; 723 return 0; 724 } 725 726 return regmap_write(st->map, reg, in); 727 } 728 729 static int ltc4282_write_voltage_byte(const struct ltc4282_state *st, u32 reg, 730 u32 fs, long val) 731 { 732 return ltc4282_write_voltage_byte_cached(st, reg, fs, val, NULL); 733 } 734 735 static int ltc4282_cache_history(struct ltc4282_state *st, u32 channel) 736 { 737 long val; 738 int ret; 739 740 ret = ltc4282_read_voltage_word(st, LTC4282_VSOURCE_LOWEST, st->vfs_out, 741 &val); 742 if (ret) 743 return ret; 744 745 st->in0_1_cache[channel].in_lowest = val; 746 747 ret = ltc4282_read_voltage_word(st, LTC4282_VSOURCE_HIGHEST, 748 st->vfs_out, &val); 749 if (ret) 750 return ret; 751 752 st->in0_1_cache[channel].in_highest = val; 753 754 ret = regmap_read(st->map, LTC4282_VSOURCE_MIN, 755 &st->in0_1_cache[channel].in_min_raw); 756 if (ret) 757 return ret; 758 759 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 760 &st->in0_1_cache[channel].in_max_raw); 761 } 762 763 static int ltc4282_cache_sync(struct ltc4282_state *st, u32 channel) 764 { 765 int ret; 766 767 ret = __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 768 st->in0_1_cache[channel].in_lowest, 769 st->in0_1_cache[channel].in_highest, 770 st->vfs_out); 771 if (ret) 772 return ret; 773 774 ret = regmap_write(st->map, LTC4282_VSOURCE_MIN, 775 st->in0_1_cache[channel].in_min_raw); 776 if (ret) 777 return ret; 778 779 return regmap_write(st->map, LTC4282_VSOURCE_MAX, 780 st->in0_1_cache[channel].in_max_raw); 781 } 782 783 static int ltc4282_vdd_source_write_lim(struct ltc4282_state *st, u32 reg, 784 int channel, u32 *cache, long val) 785 { 786 int ret; 787 788 if (st->in0_1_cache[channel].en) 789 ret = ltc4282_write_voltage_byte(st, reg, st->vfs_out, val); 790 else 791 ret = ltc4282_write_voltage_byte_cached(st, reg, st->vfs_out, 792 val, cache); 793 794 return ret; 795 } 796 797 static int ltc4282_vdd_source_reset_hist(struct ltc4282_state *st, int channel) 798 { 799 long lowest = st->vfs_out; 800 int ret; 801 802 if (channel == LTC4282_CHAN_VDD) 803 lowest = st->vdd; 804 805 if (st->in0_1_cache[channel].en) { 806 ret = __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 807 lowest, 0, st->vfs_out); 808 if (ret) 809 return ret; 810 } 811 812 st->in0_1_cache[channel].in_lowest = lowest; 813 st->in0_1_cache[channel].in_highest = 0; 814 815 /* 816 * We are also clearing possible fault logs in reset_history. Clearing 817 * the logs might be important when the auto retry bits are not enabled 818 * as the chip only enables the output again after having these logs 819 * cleared. As some of these logs are related to limits, it makes sense 820 * to clear them in here. For VDD, we need to clear under/over voltage 821 * events. For VSOURCE, fet_short and fet_bad... 822 */ 823 if (channel == LTC4282_CHAN_VSOURCE) 824 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 825 LTC4282_FET_FAILURE_FAULT_MASK); 826 827 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 828 LTC4282_VDD_FAULT_MASK); 829 } 830 831 /* 832 * We need to mux between VSOURCE and VDD which means they are mutually 833 * exclusive. Moreover, we can't really disable both VDD and VSOURCE as the ADC 834 * is continuously running (we cannot independently halt it without also 835 * stopping VGPIO). Hence, the logic is that disabling or enabling VDD will 836 * automatically have the reverse effect on VSOURCE and vice-versa. 837 */ 838 static int ltc4282_vdd_source_enable(struct ltc4282_state *st, int channel, 839 long val) 840 { 841 int ret, other_chan = ~channel & 0x1; 842 u8 __val = val; 843 844 if (st->in0_1_cache[channel].en == !!val) 845 return 0; 846 847 /* clearing the bit makes the ADC to monitor VDD */ 848 if (channel == LTC4282_CHAN_VDD) 849 __val = !__val; 850 851 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 852 LTC4282_VDD_MONITOR_MASK, 853 FIELD_PREP(LTC4282_VDD_MONITOR_MASK, !!__val)); 854 if (ret) 855 return ret; 856 857 st->in0_1_cache[channel].en = !!val; 858 st->in0_1_cache[other_chan].en = !val; 859 860 if (st->in0_1_cache[channel].en) { 861 /* 862 * Then, we are disabling @other_chan. Let's save it's current 863 * history. 864 */ 865 ret = ltc4282_cache_history(st, other_chan); 866 if (ret) 867 return ret; 868 869 return ltc4282_cache_sync(st, channel); 870 } 871 /* 872 * Then, we are enabling @other_chan. We need to do the opposite from 873 * above. 874 */ 875 ret = ltc4282_cache_history(st, channel); 876 if (ret) 877 return ret; 878 879 return ltc4282_cache_sync(st, other_chan); 880 } 881 882 static int ltc4282_write_in(struct ltc4282_state *st, u32 attr, long val, 883 int channel) 884 { 885 switch (attr) { 886 case hwmon_in_max: 887 if (channel == LTC4282_CHAN_VGPIO) 888 return ltc4282_write_voltage_byte(st, LTC4282_VGPIO_MAX, 889 1280, val); 890 891 return ltc4282_vdd_source_write_lim(st, LTC4282_VSOURCE_MAX, 892 channel, 893 &st->in0_1_cache[channel].in_max_raw, val); 894 case hwmon_in_min: 895 if (channel == LTC4282_CHAN_VGPIO) 896 return ltc4282_write_voltage_byte(st, LTC4282_VGPIO_MIN, 897 1280, val); 898 899 return ltc4282_vdd_source_write_lim(st, LTC4282_VSOURCE_MIN, 900 channel, 901 &st->in0_1_cache[channel].in_min_raw, val); 902 case hwmon_in_reset_history: 903 if (channel == LTC4282_CHAN_VGPIO) 904 return ltc4282_in_write_history(st, 905 LTC4282_VGPIO_LOWEST, 906 1280, 0, 1280); 907 908 return ltc4282_vdd_source_reset_hist(st, channel); 909 case hwmon_in_enable: 910 return ltc4282_vdd_source_enable(st, channel, val); 911 default: 912 return -EOPNOTSUPP; 913 } 914 } 915 916 static int ltc4282_curr_reset_hist(struct ltc4282_state *st) 917 { 918 int ret; 919 920 ret = __ltc4282_in_write_history(st, LTC4282_VSENSE_LOWEST, 921 st->vsense_max, 0, 40 * MILLI); 922 if (ret) 923 return ret; 924 925 /* now, let's also clear possible overcurrent fault logs */ 926 return regmap_clear_bits(st->map, LTC4282_FAULT_LOG, 927 LTC4282_OC_FAULT_MASK); 928 } 929 930 static int ltc4282_write_curr(struct ltc4282_state *st, u32 attr, 931 long val) 932 { 933 /* need to pass it in millivolt */ 934 u32 in = DIV_ROUND_CLOSEST_ULL((u64)val * st->rsense, DECA * MICRO); 935 936 switch (attr) { 937 case hwmon_curr_max: 938 return ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MAX, 40, 939 in); 940 case hwmon_curr_min: 941 return ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MIN, 40, 942 in); 943 case hwmon_curr_reset_history: 944 return ltc4282_curr_reset_hist(st); 945 default: 946 return -EOPNOTSUPP; 947 } 948 } 949 950 static int ltc4282_energy_enable_set(struct ltc4282_state *st, long val) 951 { 952 int ret; 953 954 /* setting the bit halts the meter */ 955 ret = regmap_update_bits(st->map, LTC4282_ADC_CTRL, 956 LTC4282_METER_HALT_MASK, 957 FIELD_PREP(LTC4282_METER_HALT_MASK, !val)); 958 if (ret) 959 return ret; 960 961 st->energy_en = !!val; 962 963 return 0; 964 } 965 966 static int ltc4282_write(struct device *dev, 967 enum hwmon_sensor_types type, 968 u32 attr, int channel, long val) 969 { 970 struct ltc4282_state *st = dev_get_drvdata(dev); 971 972 switch (type) { 973 case hwmon_power: 974 return ltc4282_write_power(st, attr, val); 975 case hwmon_in: 976 return ltc4282_write_in(st, attr, val, channel); 977 case hwmon_curr: 978 return ltc4282_write_curr(st, attr, val); 979 case hwmon_energy: 980 return ltc4282_energy_enable_set(st, val); 981 default: 982 return -EOPNOTSUPP; 983 } 984 } 985 986 static umode_t ltc4282_in_is_visible(const struct ltc4282_state *st, u32 attr) 987 { 988 switch (attr) { 989 case hwmon_in_input: 990 case hwmon_in_highest: 991 case hwmon_in_lowest: 992 case hwmon_in_max_alarm: 993 case hwmon_in_min_alarm: 994 case hwmon_in_label: 995 case hwmon_in_lcrit_alarm: 996 case hwmon_in_crit_alarm: 997 case hwmon_in_fault: 998 return 0444; 999 case hwmon_in_max: 1000 case hwmon_in_min: 1001 case hwmon_in_enable: 1002 return 0644; 1003 case hwmon_in_reset_history: 1004 return 0200; 1005 default: 1006 return 0; 1007 } 1008 } 1009 1010 static umode_t ltc4282_curr_is_visible(u32 attr) 1011 { 1012 switch (attr) { 1013 case hwmon_curr_input: 1014 case hwmon_curr_highest: 1015 case hwmon_curr_lowest: 1016 case hwmon_curr_max_alarm: 1017 case hwmon_curr_min_alarm: 1018 case hwmon_curr_crit_alarm: 1019 case hwmon_curr_label: 1020 return 0444; 1021 case hwmon_curr_max: 1022 case hwmon_curr_min: 1023 return 0644; 1024 case hwmon_curr_reset_history: 1025 return 0200; 1026 default: 1027 return 0; 1028 } 1029 } 1030 1031 static umode_t ltc4282_power_is_visible(u32 attr) 1032 { 1033 switch (attr) { 1034 case hwmon_power_input: 1035 case hwmon_power_input_highest: 1036 case hwmon_power_input_lowest: 1037 case hwmon_power_label: 1038 case hwmon_power_max_alarm: 1039 case hwmon_power_min_alarm: 1040 return 0444; 1041 case hwmon_power_max: 1042 case hwmon_power_min: 1043 return 0644; 1044 case hwmon_power_reset_history: 1045 return 0200; 1046 default: 1047 return 0; 1048 } 1049 } 1050 1051 static umode_t ltc4282_is_visible(const void *data, 1052 enum hwmon_sensor_types type, 1053 u32 attr, int channel) 1054 { 1055 switch (type) { 1056 case hwmon_in: 1057 return ltc4282_in_is_visible(data, attr); 1058 case hwmon_curr: 1059 return ltc4282_curr_is_visible(attr); 1060 case hwmon_power: 1061 return ltc4282_power_is_visible(attr); 1062 case hwmon_energy: 1063 /* hwmon_energy_enable */ 1064 return 0644; 1065 case hwmon_energy64: 1066 /* hwmon_energy_input */ 1067 return 0444; 1068 default: 1069 return 0; 1070 } 1071 } 1072 1073 static const char * const ltc4282_in_strs[] = { 1074 "VSOURCE", "VDD", "VGPIO" 1075 }; 1076 1077 static int ltc4282_read_labels(struct device *dev, 1078 enum hwmon_sensor_types type, 1079 u32 attr, int channel, const char **str) 1080 { 1081 switch (type) { 1082 case hwmon_in: 1083 *str = ltc4282_in_strs[channel]; 1084 return 0; 1085 case hwmon_curr: 1086 *str = "ISENSE"; 1087 return 0; 1088 case hwmon_power: 1089 *str = "Power"; 1090 return 0; 1091 default: 1092 return -EOPNOTSUPP; 1093 } 1094 } 1095 1096 static const struct clk_ops ltc4282_ops = { 1097 .recalc_rate = ltc4282_recalc_rate, 1098 .determine_rate = ltc4282_determine_rate, 1099 .set_rate = ltc4282_set_rate, 1100 .disable = ltc4282_disable, 1101 }; 1102 1103 static int ltc428_clk_provider_setup(struct ltc4282_state *st, 1104 struct device *dev) 1105 { 1106 struct clk_init_data init; 1107 int ret; 1108 1109 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1110 return 0; 1111 1112 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", 1113 fwnode_get_name(dev_fwnode(dev))); 1114 if (!init.name) 1115 return -ENOMEM; 1116 1117 init.ops = <c4282_ops; 1118 init.flags = CLK_GET_RATE_NOCACHE; 1119 st->clk_hw.init = &init; 1120 1121 ret = devm_clk_hw_register(dev, &st->clk_hw); 1122 if (ret) 1123 return ret; 1124 1125 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1126 &st->clk_hw); 1127 } 1128 1129 static int ltc428_clks_setup(struct ltc4282_state *st, struct device *dev) 1130 { 1131 unsigned long rate; 1132 struct clk *clkin; 1133 u32 val; 1134 int ret; 1135 1136 ret = ltc428_clk_provider_setup(st, dev); 1137 if (ret) 1138 return ret; 1139 1140 clkin = devm_clk_get_optional_enabled(dev, NULL); 1141 if (IS_ERR(clkin)) 1142 return dev_err_probe(dev, PTR_ERR(clkin), 1143 "Failed to get clkin"); 1144 if (!clkin) 1145 return 0; 1146 1147 rate = clk_get_rate(clkin); 1148 if (!in_range(rate, LTC4282_CLKIN_MIN, LTC4282_CLKIN_RANGE)) 1149 return dev_err_probe(dev, -EINVAL, 1150 "Invalid clkin range(%lu) [%lu %lu]\n", 1151 rate, LTC4282_CLKIN_MIN, 1152 LTC4282_CLKIN_MAX); 1153 1154 /* 1155 * Clocks faster than 250KHZ should be reduced to 250KHZ. The clock 1156 * frequency is divided by twice the value in the register. 1157 */ 1158 val = rate / (2 * LTC4282_CLKIN_MIN); 1159 1160 return regmap_update_bits(st->map, LTC4282_CLK_DIV, 1161 LTC4282_CLK_DIV_MASK, 1162 FIELD_PREP(LTC4282_CLK_DIV_MASK, val)); 1163 } 1164 1165 static const int ltc4282_curr_lim_uv[] = { 1166 12500, 15625, 18750, 21875, 25000, 28125, 31250, 34375 1167 }; 1168 1169 static int ltc4282_get_defaults(struct ltc4282_state *st, u32 *vin_mode) 1170 { 1171 u32 reg_val, ilm_adjust; 1172 int ret; 1173 1174 ret = regmap_read(st->map, LTC4282_ADC_CTRL, ®_val); 1175 if (ret) 1176 return ret; 1177 1178 st->energy_en = !FIELD_GET(LTC4282_METER_HALT_MASK, reg_val); 1179 1180 ret = regmap_read(st->map, LTC4282_CTRL_MSB, ®_val); 1181 if (ret) 1182 return ret; 1183 1184 *vin_mode = FIELD_GET(LTC4282_CTRL_VIN_MODE_MASK, reg_val); 1185 1186 ret = regmap_read(st->map, LTC4282_ILIM_ADJUST, ®_val); 1187 if (ret) 1188 return ret; 1189 1190 ilm_adjust = FIELD_GET(LTC4282_ILIM_ADJUST_MASK, reg_val); 1191 st->vsense_max = ltc4282_curr_lim_uv[ilm_adjust]; 1192 1193 st->in0_1_cache[LTC4282_CHAN_VSOURCE].en = FIELD_GET(LTC4282_VDD_MONITOR_MASK, 1194 ilm_adjust); 1195 if (!st->in0_1_cache[LTC4282_CHAN_VSOURCE].en) { 1196 st->in0_1_cache[LTC4282_CHAN_VDD].en = true; 1197 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 1198 &st->in0_1_cache[LTC4282_CHAN_VSOURCE].in_max_raw); 1199 } 1200 1201 return regmap_read(st->map, LTC4282_VSOURCE_MAX, 1202 &st->in0_1_cache[LTC4282_CHAN_VDD].in_max_raw); 1203 } 1204 1205 /* 1206 * Set max limits for ISENSE and Power as that depends on the max voltage on 1207 * rsense that is defined in ILIM_ADJUST. This is specially important for power 1208 * because for some rsense and vfsout values, if we allow the default raw 255 1209 * value, that would overflow long in 32bit archs when reading back the max 1210 * power limit. 1211 * 1212 * Also set meaningful historic values for VDD and VSOURCE 1213 * (0 would not mean much). 1214 */ 1215 static int ltc4282_set_max_limits(struct ltc4282_state *st) 1216 { 1217 int ret; 1218 1219 ret = ltc4282_write_voltage_byte(st, LTC4282_VSENSE_MAX, 40 * MILLI, 1220 st->vsense_max); 1221 if (ret) 1222 return ret; 1223 1224 /* Power is given by ISENSE * Vout. */ 1225 st->power_max = DIV_ROUND_CLOSEST(st->vsense_max * DECA * MILLI, st->rsense) * st->vfs_out; 1226 ret = ltc4282_write_power_byte(st, LTC4282_POWER_MAX, st->power_max); 1227 if (ret) 1228 return ret; 1229 1230 if (st->in0_1_cache[LTC4282_CHAN_VDD].en) { 1231 st->in0_1_cache[LTC4282_CHAN_VSOURCE].in_lowest = st->vfs_out; 1232 return __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 1233 st->vdd, 0, st->vfs_out); 1234 } 1235 1236 st->in0_1_cache[LTC4282_CHAN_VDD].in_lowest = st->vdd; 1237 return __ltc4282_in_write_history(st, LTC4282_VSOURCE_LOWEST, 1238 st->vfs_out, 0, st->vfs_out); 1239 } 1240 1241 static const char * const ltc4282_gpio1_modes[] = { 1242 "power_bad", "power_good" 1243 }; 1244 1245 static const char * const ltc4282_gpio2_modes[] = { 1246 "adc_input", "stress_fet" 1247 }; 1248 1249 static int ltc4282_gpio_setup(struct ltc4282_state *st, struct device *dev) 1250 { 1251 const char *func = NULL; 1252 int ret; 1253 1254 ret = device_property_read_string(dev, "adi,gpio1-mode", &func); 1255 if (!ret) { 1256 ret = match_string(ltc4282_gpio1_modes, 1257 ARRAY_SIZE(ltc4282_gpio1_modes), func); 1258 if (ret < 0) 1259 return dev_err_probe(dev, ret, 1260 "Invalid func(%s) for gpio1\n", 1261 func); 1262 1263 ret = regmap_update_bits(st->map, LTC4282_GPIO_CONFIG, 1264 LTC4282_GPIO_1_CONFIG_MASK, 1265 FIELD_PREP(LTC4282_GPIO_1_CONFIG_MASK, ret)); 1266 if (ret) 1267 return ret; 1268 } 1269 1270 ret = device_property_read_string(dev, "adi,gpio2-mode", &func); 1271 if (!ret) { 1272 ret = match_string(ltc4282_gpio2_modes, 1273 ARRAY_SIZE(ltc4282_gpio2_modes), func); 1274 if (ret < 0) 1275 return dev_err_probe(dev, ret, 1276 "Invalid func(%s) for gpio2\n", 1277 func); 1278 if (!ret) { 1279 /* setting the bit to 1 so the ADC to monitors GPIO2 */ 1280 ret = regmap_set_bits(st->map, LTC4282_ILIM_ADJUST, 1281 LTC4282_GPIO_MODE_MASK); 1282 } else { 1283 ret = regmap_update_bits(st->map, LTC4282_GPIO_CONFIG, 1284 LTC4282_GPIO_2_FET_STRESS_MASK, 1285 FIELD_PREP(LTC4282_GPIO_2_FET_STRESS_MASK, 1)); 1286 } 1287 1288 if (ret) 1289 return ret; 1290 } 1291 1292 if (!device_property_read_bool(dev, "adi,gpio3-monitor-enable")) 1293 return 0; 1294 1295 if (func && !strcmp(func, "adc_input")) 1296 return dev_err_probe(dev, -EINVAL, 1297 "Cannot have both gpio2 and gpio3 muxed into the ADC"); 1298 1299 return regmap_clear_bits(st->map, LTC4282_ILIM_ADJUST, 1300 LTC4282_GPIO_MODE_MASK); 1301 } 1302 1303 static const char * const ltc4282_dividers[] = { 1304 "external", "vdd_5_percent", "vdd_10_percent", "vdd_15_percent" 1305 }; 1306 1307 /* This maps the Vout full scale for the given Vin mode */ 1308 static const u16 ltc4282_vfs_milli[] = { 5540, 8320, 16640, 33280 }; 1309 1310 static const u16 ltc4282_vdd_milli[] = { 3300, 5000, 12000, 24000 }; 1311 1312 enum { 1313 LTC4282_VIN_3_3V, 1314 LTC4282_VIN_5V, 1315 LTC4282_VIN_12V, 1316 LTC4282_VIN_24V, 1317 }; 1318 1319 static int ltc4282_setup(struct ltc4282_state *st, struct device *dev) 1320 { 1321 const char *divider; 1322 u32 val, vin_mode; 1323 int ret; 1324 1325 /* The part has an eeprom so let's get the needed defaults from it */ 1326 ret = ltc4282_get_defaults(st, &vin_mode); 1327 if (ret) 1328 return ret; 1329 1330 /* default to 1 milli-ohm so we can probe without FW properties */ 1331 st->rsense = 1 * (NANO / MILLI); 1332 ret = device_property_read_u32(dev, "adi,rsense-nano-ohms", 1333 &st->rsense); 1334 if (!ret) { 1335 if (st->rsense < CENTI) 1336 return dev_err_probe(dev, -EINVAL, 1337 "adi,rsense-nano-ohms too small (< %lu)\n", 1338 CENTI); 1339 } 1340 1341 /* 1342 * The resolution for rsense is tenths of micro (eg: 62.5 uOhm) which 1343 * means we need nano in the bindings. However, to make things easier to 1344 * handle (with respect to overflows) we divide it by 100 as we don't 1345 * really need the last two digits. 1346 */ 1347 st->rsense /= CENTI; 1348 1349 val = vin_mode; 1350 ret = device_property_read_u32(dev, "adi,vin-mode-microvolt", &val); 1351 if (!ret) { 1352 switch (val) { 1353 case 3300000: 1354 val = LTC4282_VIN_3_3V; 1355 break; 1356 case 5000000: 1357 val = LTC4282_VIN_5V; 1358 break; 1359 case 12000000: 1360 val = LTC4282_VIN_12V; 1361 break; 1362 case 24000000: 1363 val = LTC4282_VIN_24V; 1364 break; 1365 default: 1366 return dev_err_probe(dev, -EINVAL, 1367 "Invalid val(%u) for vin-mode-microvolt\n", 1368 val); 1369 } 1370 1371 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1372 LTC4282_CTRL_VIN_MODE_MASK, 1373 FIELD_PREP(LTC4282_CTRL_VIN_MODE_MASK, val)); 1374 if (ret) 1375 return ret; 1376 1377 /* Foldback mode should also be set to the input voltage */ 1378 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 1379 LTC4282_FOLDBACK_MODE_MASK, 1380 FIELD_PREP(LTC4282_FOLDBACK_MODE_MASK, val)); 1381 if (ret) 1382 return ret; 1383 } 1384 1385 st->vfs_out = ltc4282_vfs_milli[val]; 1386 st->vdd = ltc4282_vdd_milli[val]; 1387 1388 ret = device_property_read_u32(dev, "adi,current-limit-sense-microvolt", 1389 &st->vsense_max); 1390 if (!ret) { 1391 int reg_val; 1392 1393 switch (val) { 1394 case 12500: 1395 reg_val = 0; 1396 break; 1397 case 15625: 1398 reg_val = 1; 1399 break; 1400 case 18750: 1401 reg_val = 2; 1402 break; 1403 case 21875: 1404 reg_val = 3; 1405 break; 1406 case 25000: 1407 reg_val = 4; 1408 break; 1409 case 28125: 1410 reg_val = 5; 1411 break; 1412 case 31250: 1413 reg_val = 6; 1414 break; 1415 case 34375: 1416 reg_val = 7; 1417 break; 1418 default: 1419 return dev_err_probe(dev, -EINVAL, 1420 "Invalid val(%u) for adi,current-limit-microvolt\n", 1421 st->vsense_max); 1422 } 1423 1424 ret = regmap_update_bits(st->map, LTC4282_ILIM_ADJUST, 1425 LTC4282_ILIM_ADJUST_MASK, 1426 FIELD_PREP(LTC4282_ILIM_ADJUST_MASK, reg_val)); 1427 if (ret) 1428 return ret; 1429 } 1430 1431 ret = ltc4282_set_max_limits(st); 1432 if (ret) 1433 return ret; 1434 1435 ret = device_property_read_string(dev, "adi,overvoltage-dividers", 1436 ÷r); 1437 if (!ret) { 1438 int div = match_string(ltc4282_dividers, 1439 ARRAY_SIZE(ltc4282_dividers), divider); 1440 if (div < 0) 1441 return dev_err_probe(dev, -EINVAL, 1442 "Invalid val(%s) for adi,overvoltage-divider\n", 1443 divider); 1444 1445 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1446 LTC4282_CTRL_OV_MODE_MASK, 1447 FIELD_PREP(LTC4282_CTRL_OV_MODE_MASK, div)); 1448 } 1449 1450 ret = device_property_read_string(dev, "adi,undervoltage-dividers", 1451 ÷r); 1452 if (!ret) { 1453 int div = match_string(ltc4282_dividers, 1454 ARRAY_SIZE(ltc4282_dividers), divider); 1455 if (div < 0) 1456 return dev_err_probe(dev, -EINVAL, 1457 "Invalid val(%s) for adi,undervoltage-divider\n", 1458 divider); 1459 1460 ret = regmap_update_bits(st->map, LTC4282_CTRL_MSB, 1461 LTC4282_CTRL_UV_MODE_MASK, 1462 FIELD_PREP(LTC4282_CTRL_UV_MODE_MASK, div)); 1463 } 1464 1465 if (device_property_read_bool(dev, "adi,overcurrent-retry")) { 1466 ret = regmap_set_bits(st->map, LTC4282_CTRL_LSB, 1467 LTC4282_CTRL_OC_RETRY_MASK); 1468 if (ret) 1469 return ret; 1470 } 1471 1472 if (device_property_read_bool(dev, "adi,overvoltage-retry-disable")) { 1473 ret = regmap_clear_bits(st->map, LTC4282_CTRL_LSB, 1474 LTC4282_CTRL_OV_RETRY_MASK); 1475 if (ret) 1476 return ret; 1477 } 1478 1479 if (device_property_read_bool(dev, "adi,undervoltage-retry-disable")) { 1480 ret = regmap_clear_bits(st->map, LTC4282_CTRL_LSB, 1481 LTC4282_CTRL_UV_RETRY_MASK); 1482 if (ret) 1483 return ret; 1484 } 1485 1486 if (device_property_read_bool(dev, "adi,fault-log-enable")) { 1487 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_FAULT_LOG_EN_MASK); 1488 if (ret) 1489 return ret; 1490 } 1491 1492 ret = device_property_read_u32(dev, "adi,fet-bad-timeout-ms", &val); 1493 if (!ret) { 1494 if (val > LTC4282_FET_BAD_MAX_TIMEOUT) 1495 return dev_err_probe(dev, -EINVAL, 1496 "Invalid value(%u) for adi,fet-bad-timeout-ms", 1497 val); 1498 1499 ret = regmap_write(st->map, LTC4282_FET_BAD_FAULT_TIMEOUT, val); 1500 if (ret) 1501 return ret; 1502 } 1503 1504 return ltc4282_gpio_setup(st, dev); 1505 } 1506 1507 static bool ltc4282_readable_reg(struct device *dev, unsigned int reg) 1508 { 1509 if (reg == LTC4282_RESERVED_1 || reg == LTC4282_RESERVED_2) 1510 return false; 1511 1512 return true; 1513 } 1514 1515 static bool ltc4282_writable_reg(struct device *dev, unsigned int reg) 1516 { 1517 if (reg == LTC4282_STATUS_LSB || reg == LTC4282_STATUS_MSB) 1518 return false; 1519 if (reg == LTC4282_RESERVED_1 || reg == LTC4282_RESERVED_2) 1520 return false; 1521 1522 return true; 1523 } 1524 1525 static const struct regmap_config ltc4282_regmap_config = { 1526 .reg_bits = 8, 1527 .val_bits = 8, 1528 .max_register = LTC4282_RESERVED_3, 1529 .readable_reg = ltc4282_readable_reg, 1530 .writeable_reg = ltc4282_writable_reg, 1531 }; 1532 1533 static const struct hwmon_channel_info * const ltc4282_info[] = { 1534 HWMON_CHANNEL_INFO(in, 1535 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1536 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1537 HWMON_I_MAX_ALARM | HWMON_I_ENABLE | 1538 HWMON_I_RESET_HISTORY | HWMON_I_FAULT | 1539 HWMON_I_LABEL, 1540 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1541 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1542 HWMON_I_MAX_ALARM | HWMON_I_LCRIT_ALARM | 1543 HWMON_I_CRIT_ALARM | HWMON_I_ENABLE | 1544 HWMON_I_RESET_HISTORY | HWMON_I_LABEL, 1545 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1546 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1547 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1548 HWMON_I_LABEL), 1549 HWMON_CHANNEL_INFO(curr, 1550 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | 1551 HWMON_C_MAX | HWMON_C_MIN | HWMON_C_MIN_ALARM | 1552 HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM | 1553 HWMON_C_RESET_HISTORY | HWMON_C_LABEL), 1554 HWMON_CHANNEL_INFO(power, 1555 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | 1556 HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN | 1557 HWMON_P_MAX_ALARM | HWMON_P_MIN_ALARM | 1558 HWMON_P_RESET_HISTORY | HWMON_P_LABEL), 1559 HWMON_CHANNEL_INFO(energy, 1560 HWMON_E_ENABLE), 1561 HWMON_CHANNEL_INFO(energy64, 1562 HWMON_E_INPUT), 1563 NULL 1564 }; 1565 1566 static const struct hwmon_ops ltc4282_hwmon_ops = { 1567 .read = ltc4282_read, 1568 .write = ltc4282_write, 1569 .is_visible = ltc4282_is_visible, 1570 .read_string = ltc4282_read_labels, 1571 }; 1572 1573 static const struct hwmon_chip_info ltc4282_chip_info = { 1574 .ops = <c4282_hwmon_ops, 1575 .info = ltc4282_info, 1576 }; 1577 1578 static int ltc4282_show_fault_log(void *arg, u64 *val, u32 mask) 1579 { 1580 struct ltc4282_state *st = arg; 1581 long alarm; 1582 int ret; 1583 1584 ret = ltc4282_read_alarm(st, LTC4282_FAULT_LOG, mask, &alarm); 1585 if (ret) 1586 return ret; 1587 1588 *val = alarm; 1589 1590 return 0; 1591 } 1592 1593 static int ltc4282_show_curr1_crit_fault_log(void *arg, u64 *val) 1594 { 1595 return ltc4282_show_fault_log(arg, val, LTC4282_OC_FAULT_MASK); 1596 } 1597 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_curr1_crit_fault_log, 1598 ltc4282_show_curr1_crit_fault_log, NULL, "%llu\n"); 1599 1600 static int ltc4282_show_in1_lcrit_fault_log(void *arg, u64 *val) 1601 { 1602 return ltc4282_show_fault_log(arg, val, LTC4282_UV_FAULT_MASK); 1603 } 1604 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_in1_lcrit_fault_log, 1605 ltc4282_show_in1_lcrit_fault_log, NULL, "%llu\n"); 1606 1607 static int ltc4282_show_in1_crit_fault_log(void *arg, u64 *val) 1608 { 1609 return ltc4282_show_fault_log(arg, val, LTC4282_OV_FAULT_MASK); 1610 } 1611 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_in1_crit_fault_log, 1612 ltc4282_show_in1_crit_fault_log, NULL, "%llu\n"); 1613 1614 static int ltc4282_show_fet_bad_fault_log(void *arg, u64 *val) 1615 { 1616 return ltc4282_show_fault_log(arg, val, LTC4282_FET_BAD_FAULT_MASK); 1617 } 1618 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_fet_bad_fault_log, 1619 ltc4282_show_fet_bad_fault_log, NULL, "%llu\n"); 1620 1621 static int ltc4282_show_fet_short_fault_log(void *arg, u64 *val) 1622 { 1623 return ltc4282_show_fault_log(arg, val, LTC4282_FET_SHORT_FAULT_MASK); 1624 } 1625 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_fet_short_fault_log, 1626 ltc4282_show_fet_short_fault_log, NULL, "%llu\n"); 1627 1628 static int ltc4282_show_power1_bad_fault_log(void *arg, u64 *val) 1629 { 1630 return ltc4282_show_fault_log(arg, val, LTC4282_POWER_BAD_FAULT_MASK); 1631 } 1632 DEFINE_DEBUGFS_ATTRIBUTE(ltc4282_power1_bad_fault_log, 1633 ltc4282_show_power1_bad_fault_log, NULL, "%llu\n"); 1634 1635 static void ltc4282_debugfs_init(struct ltc4282_state *st, struct i2c_client *i2c) 1636 { 1637 debugfs_create_file_unsafe("power1_bad_fault_log", 0400, i2c->debugfs, st, 1638 <c4282_power1_bad_fault_log); 1639 debugfs_create_file_unsafe("in0_fet_short_fault_log", 0400, i2c->debugfs, st, 1640 <c4282_fet_short_fault_log); 1641 debugfs_create_file_unsafe("in0_fet_bad_fault_log", 0400, i2c->debugfs, st, 1642 <c4282_fet_bad_fault_log); 1643 debugfs_create_file_unsafe("in1_crit_fault_log", 0400, i2c->debugfs, st, 1644 <c4282_in1_crit_fault_log); 1645 debugfs_create_file_unsafe("in1_lcrit_fault_log", 0400, i2c->debugfs, st, 1646 <c4282_in1_lcrit_fault_log); 1647 debugfs_create_file_unsafe("curr1_crit_fault_log", 0400, i2c->debugfs, st, 1648 <c4282_curr1_crit_fault_log); 1649 } 1650 1651 static int ltc4282_probe(struct i2c_client *i2c) 1652 { 1653 struct device *dev = &i2c->dev, *hwmon; 1654 struct ltc4282_state *st; 1655 int ret; 1656 1657 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 1658 if (!st) 1659 return -ENOMEM; 1660 1661 st->map = devm_regmap_init_i2c(i2c, <c4282_regmap_config); 1662 if (IS_ERR(st->map)) 1663 return dev_err_probe(dev, PTR_ERR(st->map), 1664 "failed regmap init\n"); 1665 1666 /* Soft reset */ 1667 ret = regmap_set_bits(st->map, LTC4282_ADC_CTRL, LTC4282_RESET_MASK); 1668 if (ret) 1669 return ret; 1670 1671 /* Yes, it's big but it is as specified in the datasheet */ 1672 msleep(3200); 1673 1674 ret = ltc428_clks_setup(st, dev); 1675 if (ret) 1676 return ret; 1677 1678 ret = ltc4282_setup(st, dev); 1679 if (ret) 1680 return ret; 1681 1682 hwmon = devm_hwmon_device_register_with_info(dev, "ltc4282", st, 1683 <c4282_chip_info, NULL); 1684 if (IS_ERR(hwmon)) 1685 return PTR_ERR(hwmon); 1686 1687 ltc4282_debugfs_init(st, i2c); 1688 1689 return 0; 1690 } 1691 1692 static const struct of_device_id ltc4282_of_match[] = { 1693 { .compatible = "adi,ltc4282" }, 1694 {} 1695 }; 1696 MODULE_DEVICE_TABLE(of, ltc4282_of_match); 1697 1698 static struct i2c_driver ltc4282_driver = { 1699 .driver = { 1700 .name = "ltc4282", 1701 .of_match_table = ltc4282_of_match, 1702 }, 1703 .probe = ltc4282_probe, 1704 }; 1705 module_i2c_driver(ltc4282_driver); 1706 1707 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1708 MODULE_DESCRIPTION("LTC4282 I2C High Current Hot Swap Controller"); 1709 MODULE_LICENSE("GPL"); 1710